On Tue, Aug 15, 2017 at 09:19:43AM +0200, Fabien Dessenne wrote:
> Document device tree bindings for the STM32 CRYP.
>
> Signed-off-by: Fabien Dessenne
> ---
> .../devicetree/bindings/crypto/st,stm32-cryp.txt | 20
>
> 1 file changed, 20 insertions(+)
> create mode 100
Am Donnerstag, 17. August 2017, 20:25:17 CEST schrieb PrasannaKumar
Muralidharan:
Hi PrasannaKumar,
> +
> +static int jz4780_rng_generate(struct crypto_rng *tfm,
> +const u8 *src, unsigned int slen,
> +u8 *dst, unsigned int dlen)
> +{
> +
Enable PRNG driver support in MIPS Creator CI20 default config.
Signed-off-by: PrasannaKumar Muralidharan
---
arch/mips/configs/ci20_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index b42cfa7..9f48f2c 10064
Add myself as the maintainer of JZ4780 SoC's PRNG drvier.
Signed-off-by: PrasannaKumar Muralidharan
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 45ec467..ee8c6f6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6733,6 +6733,11 @@ L:
JZ4780 SoC pseudo random number generator driver using crypto framework.
Adding a delay before reading RNG data and disabling RNG after reading
data was suggested by Jeffery Walton.
Tested-by: Mathieu Malaterre
Suggested-by: Jeffrey Walton
Signed-off-by: PrasannaKumar Muralidharan
---
drivers
This patch adds RNG node to jz4780.dtsi.
Signed-off-by: PrasannaKumar Muralidharan
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 1301694..865b9bf 100644
---
Ingenic PRNG registers are a part of the same hardware block as clock
and power stuff. It is handled by CGU driver. Ingenic M200 SoC has power
related registers that are after the PRNG registers. So instead of
shortening the register range use syscon interface to expose regmap.
This regmap is used
This patch series adds support of pseudo random number generator found
in Ingenic's JZ4780 and X1000 SoC.
The PRNG hardware block registers are a part of same hardware block
that has clock and power registers which is handled by CGU driver.
Ingenic M200 SoC contains power related registers that ar
Add devicetree bindings for hardware pseudo random number generator
present in Ingenic JZ4780 SoC.
Signed-off-by: PrasannaKumar Muralidharan
---
.../devicetree/bindings/rng/ingenic,jz4780-rng.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devi
vio_device_id are not supposed to change at runtime. All functions
working with vio_device_id provided by work with
const vio_device_id. So mark the non-const structs as const.
Signed-off-by: Arvind Yadav
---
drivers/char/hw_random/pseries-rng.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
> diff --git a/security/integrity/ima/ima_appraise.c
> b/security/integrity/ima/ima_appraise.c
> index 87d2b601cf8e..5a244ebc61d9 100644
> --- a/security/integrity/ima/ima_appraise.c
> +++ b/security/integrity/ima/ima_appraise.c
> @@ -190,6 +190,64 @@ int ima_read_xattr(struct dentry *dentry,
>
On Fri, 2017-08-04 at 19:03 -0300, Thiago Jung Bauermann wrote:
> This patch introduces the modsig keyword to the IMA policy syntax to
> specify that a given hook should expect the file to have the IMA signature
> appended to it. Here is how it can be used in a rule:
>
> appraise func=KEXEC_KERNEL
Hi, all,
On 08/11/2017 07:05 PM, Marcel Holtmann wrote:
Hi Stephan,
AF_ALG is best suited for crypto use cases where a socket is set up once
and there are lots of reads and writes to justify the setup cost. With
asymmetric crypto, the setup cost is high when you might only use the
socket for a
vio_device_id are not supposed to change at runtime. All functions
working with vio_device_id provided by work with
const vio_device_id. So mark the non-const structs as const.
Signed-off-by: Arvind Yadav
---
drivers/crypto/nx/nx-842-pseries.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
vio_device_id are not supposed to change at runtime. All functions
working with vio_device_id provided by work with
const vio_device_id. So mark the non-const structs as const.
Signed-off-by: Arvind Yadav
---
drivers/crypto/nx/nx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
>From af1b10e1e6aaf67f8dc45ed78de89b0469794a98 Mon Sep 17 00:00:00 2001
From: Kamil Konieczny
Date: Thu, 17 Aug 2017 12:11:36 +0200
Subject: [PATCH] crypto: doc - clarify return values for async hash methods
* fix documentation of return values for crypto_ahash_init(),
crypto_ahash_finup(), cry
On Mon, Aug 07, 2017 at 10:31:20AM -0700, Stefan Agner wrote:
> Use just @ to denote comments which works with gcc and clang.
> Otherwise clang reports an escape sequence error:
> error: invalid % escape in inline assembly string
>
> Use %0-%3 as operand references, this avoids:
> error: inval
On Tue, Aug 08, 2017 at 09:42:47PM +0800, Pan Bian wrote:
> The return value of dma_map_single() should be checked by
> dma_mapping_error(). However, in function ccp_init_dm_workarea(), its
> return value is checked against NULL, which could result in failures.
>
> Signed-off-by: Pan Bian
Patch
On Thu, Aug 03, 2017 at 03:34:12PM +0200, Mogens Lauridsen wrote:
> The direction used in dma_unmap_sg in aes calc is wrong.
> This result in the cache not being invalidated correct when aes
> calculation is done and result has been dma'ed to memory.
> This is seen as sporadic wrong result from aes
On Thu, Aug 03, 2017 at 03:46:35PM +0200, Mogens Lauridsen wrote:
> This driver previously used a spinlock. The spinlock is not
> used any more, but the spinlock variable was still there
> and also being initialized.
>
> Signed-off-by: Mogens Lauridsen
Patch applied. Thanks.
--
Email: Herbert
On Thu, Aug 10, 2017 at 08:42:43PM +0300, Horia Geantă wrote:
>
> Patches 5-9 are the core of the patch set, adding the driver.
> For symmetric encryption the legacy ablkcipher interface is used; the
> plan is to convert to skcipher all CAAM frontends at once at a certain
> point in time.
I'm fine
21 matches
Mail list logo
