On Friday 03 February 2017 11:02 PM, Sasha Levin wrote:
On Mon, Jan 30, 2017 at 7:30 AM, George Cherian
wrote:
This series adds the support for Cavium Cryptographic Accelerarion Unit (CPT)
CPT is available in Cavium's Octeon-Tx SoC series.
The series was tested with ecryptfs and dm-crypt for
On Sat, Feb 04, 2017 at 11:47:38AM +0800, Yisheng Xie wrote:
> On 2016/10/18 1:06, Andy Lutomirski wrote:
> > hw_random carefully avoids using a stack buffer except in
> > add_early_randomness(). This causes a crash in virtio_rng if
> > CONFIG_VMAP_STACK=y.
> I try to understand this patch, but I
Hi Sasha,
Thanks for the reveiw.
On Friday 03 February 2017 12:24 AM, Sasha Levin wrote:
On Mon, Jan 30, 2017 at 7:30 AM, George Cherian
wrote:
diff --git a/drivers/crypto/cavium/cpt/cptvf_main.c
b/drivers/crypto/cavium/cpt/cptvf_main.c
new file mode 100644
index 000..4cf466d
--- /dev/
Hi Andy,
On 2016/10/18 1:06, Andy Lutomirski wrote:
> hw_random carefully avoids using a stack buffer except in
> add_early_randomness(). This causes a crash in virtio_rng if
> CONFIG_VMAP_STACK=y.
I try to understand this patch, but I do not know why it will cause
a crash in virtio_rng with CONF
An ancient gcc bug (first reported in 2003) has apparently resurfaced
on MIPS, where kernelci.org reports an overly large stack frame in the
whirlpool hash algorithm:
crypto/wp512.c:987:1: warning: the frame size of 1112 bytes is larger than 1024
bytes [-Wframe-larger-than=]
With some testing in
On Fri, Feb 3, 2017 at 2:59 AM, Anup Patel wrote:
>
>
> On Thu, Feb 2, 2017 at 11:31 AM, Dan Williams
> wrote:
>>
>> On Wed, Feb 1, 2017 at 8:47 PM, Anup Patel
>> wrote:
>> > The DMAENGINE framework assumes that if PQ offload is supported by a
>> > DMA device then all 256 PQ coefficients are sup
Changes in v4:
- Added Rob Herring's Acked-by to patch 1/3 for bindings doc
- In response to Herbert's comment, in ahash_export() and
ahash_import(), only copy the hash state, not state params
related to cipher or aead algos.
- Noticed that hmac_offset in iproc_reqctx_s and spu_hash_params
Add Northstar2 device tree entry for Broadcom Secure Processing
Unit (SPU) crypto hardware.
Signed-off-by: Steve Lin
Signed-off-by: Rob Rice
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.d
Device tree documentation for Broadcom Secure Processing Unit
(SPU) crypto hardware.
Signed-off-by: Steve Lin
Signed-off-by: Rob Rice
Acked-by: Rob Herring
---
.../devicetree/bindings/crypto/brcm,spu-crypto.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 D
On Mon, Jan 30, 2017 at 7:30 AM, George Cherian
wrote:
> This series adds the support for Cavium Cryptographic Accelerarion Unit (CPT)
> CPT is available in Cavium's Octeon-Tx SoC series.
>
> The series was tested with ecryptfs and dm-crypt for in kernel cryptographic
> offload operations. This dr
In preparation of splitting off the CBC-MAC transform in the CCM
driver into a separate algorithm, define some test cases for the
AES incarnation of cbcmac.
Signed-off-by: Ard Biesheuvel
---
crypto/testmgr.c | 7 +++
crypto/testmgr.h | 60
2 files changed, 67 insertions(+)
On ARMv8 implementations that do not support the Crypto Extensions,
such as the Raspberry Pi 3, the CCM driver falls back to the generic
table based AES implementation to perform the MAC part of the
algorithm, which is slow and not time invariant. So add a CBCMAC
implementation to the shared glue c
Update the generic CCM driver to defer CBC-MAC processing to a
dedicated CBC-MAC ahash transform rather than open coding this
transform (and much of the associated scatterwalk plumbing) in
the CCM driver itself.
This cleans up the code considerably, but more importantly, it allows
the use of alter
This series is primarily directed at improving the performance and security
of CCM on the Rasperry Pi 3. This involves splitting the MAC handling of
CCM into a separate driver so that we can efficiently replace it by something
else using the ordinary algo resolution machinery.
Patch #1 adds some t
On Thu, Feb 2, 2017 at 10:17 AM, Anup Patel wrote:
> The remote processor can have DMAENGINE capabilities and client
> can pass data to be processed via main memory. In such cases,
> the client will require DMAble memory for remote processor.
>
> This patch adds new API mbox_channel_device() which
Hello Herbert,
On 2/2/2017 7:27 PM, Herbert Xu wrote:
On Thu, Jan 26, 2017 at 11:30:04AM +0530, Nitin Kumbhar wrote:
This ECDSA implementation is analogous to the RSA kernel implementation for
signature generation / verification. It extends ECC family of algorithms
like ECDH to support signatu
Hello,
This patch series adds support for Elliptic Curve Digital Signature
Algorithm (ECDSA). To reuse existing ECC functionality, which is
added as part of ECDH, it separates out ECC and ECDH so that
only ECC functionality is available for ECDSA even when ECDH is in
a disabled state.
Patch #1 re
Add functions to copy vli from buffers, to print vli in
big endian format, for vli mod and mod multiplication ops,
ecc point addition and ecc pub key validation.
Signed-off-by: Nitin Kumbhar
---
crypto/ecc.c | 189 ++
1 files changed, 189
This adds support for ECDSA algorithm. This implementation supports
sign and verify functions for ECDSA algorithm using akcipher. As ECDSA
is a signing algorithm dummy functions are added for encrypt() and
decrypt().
Helper routines for parsing public and private ECC keys for ECDSA are
added as we
Update tcrypt module to include a new ECDSA test
modes. It includes:
tcrypt.ko mode=560 for ECDSA sign/verify validation.
tcrypt.ko mode=561 for ECDSA sign/verify op perf in cycles.
tcrypt.ko mode=561 sec= for number of ECDSA sign
verify ops in given time.
Signed-off-by: Nitin Kumbhar
---
cry
Update crypto test manager to include NIST ECDSA
test vectors and various ECDSA tests. These include
tests for ECDSA signing, ECDSA sign-verification,
ECDSA signing and verifying generated signatures and
invalidation of incorrect signatures.
Signed-off-by: Nitin Kumbhar
---
crypto/testmgr.c | 3
Export vli and ECC related functions so that these can
be used by all ECC algorithm modules like ECDH, ECDSA and ECIES.
Signed-off-by: Nitin Kumbhar
---
crypto/ecc.c | 115 +-
crypto/ecc.h | 56
2 files chang
Add ECC operations i.e. vli and ecc point ops as a separate
module under CRYPTO_ECC kconfig. This allows other ECC
algorithms like ECDSA & ECIES to reuse these ops even when ECDH
is disabled with CRYPTO_ECDH kconfig.
With these changes, ECDH specific functions are consolidated
as ECDH helper routi
On Thu, Feb 2, 2017 at 11:31 AM, Dan Williams wrote:
>
> On Wed, Feb 1, 2017 at 8:47 PM, Anup Patel wrote:
> > The DMAENGINE framework assumes that if PQ offload is supported by a
> > DMA device then all 256 PQ coefficients are supported. This assumption
> > does not hold anymore because we now h
On Fri, Jan 27, 2017 at 05:09:04PM -0600, Gary R Hook wrote:
> Eliminate a double-add by creating a new list to manage
> command descriptors when created; move the descriptor to
> the pending list when the command is submitted. This
>
>
> Signed-off-by: Gary R Hook
Patch applied. Thanks.
--
E
On Thu, Feb 02, 2017 at 11:38:55AM +, Ard Biesheuvel wrote:
> The arm64 bit sliced AES core code uses the IV buffer to pass the final
> keystream block back to the glue code if the input is not a multiple of
> the block size, so that the asm code does not have to deal with anything
> except 16
On Sat, Jan 28, 2017 at 11:25:29PM +, Ard Biesheuvel wrote:
> Patch #1 is a fix for the CBC chaining issue that was discussed on the
> mailing list. The driver itself is queued for v4.11, so this fix can go
> right on top.
>
> Patches #2 - #6 clear the cra_alignmasks of various drivers: all NE
On Thu, Feb 02, 2017 at 11:38:56AM +, Ard Biesheuvel wrote:
> The ARM bit sliced AES core code uses the IV buffer to pass the final
> keystream block back to the glue code if the input is not a multiple of
> the block size, so that the asm code does not have to deal with anything
> except 16 by
On Thu, Jan 26, 2017 at 05:07:45PM +0100, Cyrille Pitchen wrote:
> Hi all,
>
> this series of patches has been based and tested on next-20170125 with
> CRYPTO_MANAGER_DISABLED_TESTS not set.
>
> The series adds support to the hmac(shaX) algorithms first, then combines
> both the Atmel SHA and AES
On Fri, Jan 27, 2017 at 03:28:45PM -0600, Gary R Hook wrote:
> An I/O page fault occurs when the IOMMU is enabled on a
> system that supports the v5 CCP. DMA operations use a
> Request ID value that does not match what is expected by
> the IOMMU, resulting in the I/O page fault. Setting the
> Req
On Fri, Jan 27, 2017 at 04:09:04PM +0530, Harsh Jain wrote:
> This patch series is based on Herbert's cryptodev-2.6 tree and depends on
> patch series "Bug Fixes for 4.10". It includes Bug Fixes.
>
> Atul Gupta (2)
> crypto:chcr-Change flow IDs
> crypto:chcr- Fix wrong typecasting
> Harsh Jai
On Tue, Jan 24, 2017 at 10:34:31AM +0530, Harsh Jain wrote:
> This patch series includes critical bug fixes
>
> Atul Gupta (2):
> crypto:chcr- Fix panic on dma_unmap_sg
> crypto:chcr- Check device is allocated before use
All applied. I also added the key length check as I think it can
be exp
On Thu, Jan 26, 2017 at 04:33:00PM +0100, Rabin Vincent wrote:
> From: Rabin Vincent
>
> The documentation states that crypto_ahash_reqsize() provides the size
> of the state structure used by crypto_ahash_export(). But it's actually
> crypto_ahash_statesize() which provides this size.
>
> Sign
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