On Tuesday, April 05, 2016 08:11:19 PM Herbert Xu wrote:
> Christian Lamparter wrote:
> >
> > The crash is caused by a bad read in ppc4xx_rng_enable [0]. From what I
> > can tell, the driver is mapping the crypto control registers. The
> > problem is that they are claimed by the main crypto driver
Dear Sir.
I bring you greetings. My name is Mr.Oliver Seno Lim, I am a staff of Abbey
National Plc. London and heading our regional office in West Africa. Our late
customer named Engr.Ben W.westland, made a fixed deposit amount of
US$7Million.He did not declare any next of kin in any of his pap
> From: Herbert Xu [mailto:herb...@gondor.apana.org.au]
> Sent: Tuesday, April 05, 2016 5:04 AM
> To: megha@linux.intel.com
> Cc: da...@davemloft.net; linux-crypto@vger.kernel.org; linux-
> ker...@vger.kernel.org; tim.c.c...@linux.intel.com; Yu, Fenghua
> ; Dey, Megha
> Subject: Re: [PATCH 2/7
Am Freitag, 8. April 2016, 13:09:02 schrieb Jeffrey Walton:
Hi Jeffrey,
> On Fri, Apr 8, 2016 at 12:55 PM, Stephan Mueller
wrote:
> > Am Freitag, 8. April 2016, 12:54:10 schrieb Jeffrey Walton:
> >
> > Hi Jeffrey,
> >
> >> > +int rsa_check_key_length(unsigned int len)
> >> > +{
> >> > +
On Fri, Apr 8, 2016 at 12:55 PM, Stephan Mueller wrote:
> Am Freitag, 8. April 2016, 12:54:10 schrieb Jeffrey Walton:
>
> Hi Jeffrey,
>
>> > +int rsa_check_key_length(unsigned int len)
>> > +{
>> > + switch (len) {
>> > + case 512:
>> > + case 1024:
>> > + case 1536:
>> > +
Am Freitag, 8. April 2016, 12:54:10 schrieb Jeffrey Walton:
Hi Jeffrey,
> > +int rsa_check_key_length(unsigned int len)
> > +{
> > + switch (len) {
> > + case 512:
> > + case 1024:
> > + case 1536:
> > + case 2048:
> > + case 3072:
> > + case 4096:
> > +
> +int rsa_check_key_length(unsigned int len)
> +{
> + switch (len) {
> + case 512:
> + case 1024:
> + case 1536:
> + case 2048:
> + case 3072:
> + case 4096:
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
That's an unusual rest
Am Mittwoch, 6. April 2016, 16:37:05 schrieb Tudor Ambarus:
Hi Tudor,
> Dedicated to RSA (hardware) implementations that want to use
> raw integers instead of MPI keys.
>
> Signed-off-by: Tudor Ambarus
> ---
> crypto/rsa.c | 15
> crypto/rsa_helper.c | 182
> ++
Am Mittwoch, 6. April 2016, 16:37:56 schrieb Tudor Ambarus:
Hi Tudor,
> Add RSA support to caam driver.
>
> Coauthored-by: Yashpal Dutta
>
> Signed-off-by: Tudor Ambarus
> ---
> drivers/crypto/caam/Kconfig| 12 +
> drivers/crypto/caam/Makefile | 4 +
> drivers/crypto/caam/caampkc.c
On 7 April 2016 at 20:03, Kefeng Wang wrote:
>
>
> On 2016/4/7 22:55, Mathieu Poirier wrote:
>> On 7 April 2016 at 02:23, Kefeng Wang wrote:
>>> This adds the Hisilicon Random Number Generator(RNG) support,
>>> which is found in Hip04 and Hip05 soc.
>>>
>>> Signed-off-by: Kefeng Wang
>>> ---
>>>
According to the Freescale GPL driver code, there are two different
Security Controller (SCC) versions: SCC and SCC2.
The SCC is found on older i.MX SoCs, e.g. the i.MX25. This is the
version implemented and tested here.
As there is no publicly available documentation for this IP core,
all inform
Add documentation for the Freescale Security Controller (SCC)
found on i.MX25 SoCs.
Signed-off-by: Steffen Trumtrar
Acked-by: Rob Herring
---
Changes in v2:
- add clocks to required properties
- add Acked-by
.../devicetree/bindings/crypto/fsl-imx-scc.txt | 21 +
1
Add the Security Controller (SCC) module to the dtsi.
Signed-off-by: Steffen Trumtrar
---
arch/arm/boot/dts/imx25.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 6b1f4bbe6ec6..af6af8741fe5 100644
--- a/arch/arm/b
Hi all,
running a current 4.4.6 kernel on a board using a Freescale P1020, I ran into
an oops when calling crypto_alloc_aead using the talitos driver. I could also
reproduce this using the run-time self tests:
[...]
[1.141095] talitos ffe3.crypto: hwrng
[1.145381] Unable to handle k
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