Hi Linus:
Here is the crypto update for 4.1:
* Added user-space interface for AEAD.
* Added user-space interface for RNG (i.e., pseudo RNG).
* Prevent internal helper algos from being exposed to user-space.
* Merged common code from assembly/C SHA implementations .
* Added ARMv8 SHA1/256.
* Added
On Tue, Apr 14, 2015 at 11:37:01AM -0700, Tadeusz Struk wrote:
> The only problem is it calls init_sync_kiocb(&iocb, NULL) on a different iocb.
> The one that isn't even passed to skcipher_recvmsg()
> skcipher_recvmsg() checks is_sync_kiocb(msg->msg_iocb).
> I just want to make sure that after the
On 04/14/2015 11:26 AM, Al Viro wrote:
>>> @@ -766,8 +765,7 @@ int sock_recvmsg(struct socket *sock, struct msghdr
>>> *msg,
>>> > >
>>> > > init_sync_kiocb(&iocb, NULL);
>>> > > ret = __sock_recvmsg(&iocb, sock, msg, size, flags);
>>> > > - if (-EIOCBQUEUED == ret)
>>> > >
On Tue, Apr 14, 2015 at 11:00:49AM -0700, Tadeusz Struk wrote:
> On 04/11/2015 02:18 PM, Al Viro wrote:
> > @@ -766,8 +765,7 @@ int sock_recvmsg(struct socket *sock, struct msghdr
> > *msg,
> >
> > init_sync_kiocb(&iocb, NULL);
> > ret = __sock_recvmsg(&iocb, sock, msg, size, flags);
> >
On 04/11/2015 02:18 PM, Al Viro wrote:
> @@ -766,8 +765,7 @@ int sock_recvmsg(struct socket *sock, struct msghdr *msg,
>
> init_sync_kiocb(&iocb, NULL);
> ret = __sock_recvmsg(&iocb, sock, msg, size, flags);
> - if (-EIOCBQUEUED == ret)
> - ret = wait_on_sync_kiocb(&io
From: Colin Ian King
backlog is not initialised so in the case where
cpg->eng_st != ENGINE_IDLE it is never initialised and
hence which could lead to an illegal memory dereference
in the statement:
backlog->complete(backlog, -EINPROGRESS);
Discovered with cppcheck static analsys:
[drivers/cry
Hi,
On Tue, Apr 14, 2015 at 01:20:58PM +0200, LABBE Corentin wrote:
> The Security System is a hardware cryptographic accelerator that support
> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
> It could be found on many Allwinner SoC.
>
> This patch enable the Security System on the Allwinner A20 SoC Dev
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.
This patch enable the Security System on the Allwinner A20 SoC Device-tree.
Signed-off-by: LABBE Corentin
---
arch/arm/boot/dts/sun7i-a20.dtsi
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support:
- MD5 and SHA1 hash algorithms
- AES block cipher in CBC/ECB mode with 128/196/256bits keys.
- DES and 3DES block cipher in CBC/ECB mode
Signed-off-by: LABBE
This patch adds documentation for Device-Tree bindings for the Security System
cryptographic accelerator driver.
Signed-off-by: LABBE Corentin
---
Documentation/devicetree/bindings/crypto/sunxi-ss.txt | 9 +
1 file changed, 9 insertions(+)
create mode 100644 Documentation/devicetree/bi
Hello
This is the driver for the Security System included in Allwinner SoC A20.
The Security System (SS for short) is a hardware cryptographic accelerator that
support AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on others Allwinner SoC:
- A10s, A33 and A31 diagram speak about it with
Signed-off-by: LABBE Corentin
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index efbcb50..dd3e27f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -555,6 +555,12 @@ S: Maintained
F: Documentation/i2c/busses/i2c-ali1563
F: drivers/i2c/b
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