The DRBG code contains memset(0) calls to initialize a varaible
that are not necessary as the variable is always overwritten by
the processing.
This patch increases the CTR and Hash DRBGs by about 5%.
Signed-off-by: Stephan Mueller
---
crypto/drbg.c | 18 --
1 file changed, 18 d
Hi,
The following patches increase the performance of the CTR DRBG and Hash
DRBG.
The updates successfully pass the CAVS testing. for Hash DRBG and CTR
DRBG.
Stephan Mueller (2):
crypto: drbg: use single block cipher API
crypto: drbg: remove superflowous memsets
crypto/drbg.c | 57
The CTR DRBG only encrypts one single block at a time. Thus, use the
single block crypto API to avoid additional overhead from the block
chaining modes.
With the patch, the speed of the DRBG increases between 30% and 40%.
The DRBG still passes the CTR DRBG CAVS test.
Signed-off-by: Stephan Muell
[PATCH v1 3/3] crypto: powerpc/md5 - kernel config
Integrate the module into the kernel config tree.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile
index d400bf9..c6b25cba 100644
--- a/arch/powerpc/crypto/Makefile
+++ b/arch/powerpc/cr
[PATCH v1 1/3] crypto: powerpc/md5 - assembler
This is the assembler code for the MD5 implementation.
Handling of algorithm constants has been slightly
changed to reduce register usage and make better use
of cores with multiple ALUs. Thus they are stored as
delta values.
Signed-off-by: Markus Sto
[PATCH v1 2/3] crypto: powerpc/md5 - glue
Glue code for crypto infrastructure. Call the assembler
code where required. Take a little care about small input
data. Kick out early for input chunks < 64 bytes and replace
memset for context cleanup with simple loop.
Signed-off-by: Markus Stockhausen
[PATCH v1 0/3] crypto: powerpc/md5
The following patches add support for optimized MD5
calculation on PPC processors. It completes the previous
patches to provide a comprehensive IPsec algorithm support
for low power routers without hardware crypto acceleration.
The implementation is endian indep
On Sun, Feb 22, 2015 at 09:59:38AM +0100, Markus Stockhausen wrote:
> Define some register aliases for better readability.
>
> Signed-off-by: Markus Stockhausen
All applied. Thanks!
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbe
On Mon, Feb 16, 2015 at 06:09:12PM -0800, Florian Fainelli wrote:
> Hi,
>
> This patchset prepares the driver to be built on non-MIPS bcm63xx
> architectures
> such as the ARM bcm63xx variants, thanks!
>
> Although patch 3 touches a MIPS header file, there should be little to no
> conflicts ther
On Fri, Feb 20, 2015 at 03:37:21PM +1100, Andre Wolokita wrote:
> In omap4_rng_init(), a check of bit 10 of the RNG_CONFIG_REG is done to
> determine
> whether the RNG is running. This is suspicious firstly due to the use of
> RNG_CONTROL_ENABLE_TRNG_MASK and secondly because the same mask is writ
Martin Hicks wrote:
> This is properly defined in the md5 header file.
Please resubmit with sign-off.
Thanks,
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
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On Sat, Feb 28, 2015 at 01:08:03PM +0100, Stephan Mueller wrote:
> Am Samstag, 28. Februar 2015, 23:47:12 schrieb Herbert Xu:
>
> Hi Herbert,
>
> > On Thu, Feb 19, 2015 at 07:56:48AM +0100, Stephan Mueller wrote:
> > > In case of rfc4106(gcm(aes)), the IV is 96 bits. Thus, our constructed
> >
>
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