On Tue, Apr 29, 2014 at 05:38:14PM +0300, Stanimir Varbanov wrote:
>
> This is new for me because I saw similar code in cryptd.c where in
> cryptd_queue_worker() (workqueue context) the backlog->complete() is
> called outside of local_bh_disable().
That's what I thought :)
If you dig deeper you'l
Thanks for the review!
On 04/28/2014 11:50 AM, Herbert Xu wrote:
> On Mon, Apr 14, 2014 at 03:48:37PM +0300, Stanimir Varbanov wrote:
>>
>> +if (backlog)
>> +backlog->complete(backlog, -EINPROGRESS);
>
> The completion function needs to be called with BH disabled.
>
> Cheers,
>
Thanks for the review!
On 04/28/2014 11:18 AM, Herbert Xu wrote:
> On Mon, Apr 14, 2014 at 03:48:40PM +0300, Stanimir Varbanov wrote:
>>
>> +} else if (IS_DES(flags)) {
>> +u32 tmp[DES_EXPKEY_WORDS];
>> +
>> +if (keylen != QCE_DES_KEY_SIZE)
>> +goto
Thanks for the review!
On 04/28/2014 11:00 AM, Herbert Xu wrote:
> On Mon, Apr 14, 2014 at 03:48:40PM +0300, Stanimir Varbanov wrote:
>>
>> +if (IS_AES(flags)) {
>> +switch (keylen) {
>> +case AES_KEYSIZE_128:
>> +case AES_KEYSIZE_256:
>> +
The kernel defines setbits32() and clrbits32() macros only for
Power-based architectures. This patch modifies the Freescale CAAM
driver to add macros for use on ARM architectures.
Signed-off-by: Victoria Milhoan
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/regs.h | 6 ++
1 file cha
Few read only registers like CHAVID, CTPR etc were wrongly defined
as 64 bit registers. This functioned properly on the powerpc platforms.
However ARM SoC's wouldn't function correctly if these registers
are defined as 64 bit. So correcting the definition to two 32 bit registers.
Signed-off-by: Ru
Few read only registers like CHAVID, CTPR etc were wrongly defined
as 64 bit registers. This functioned properly on the powerpc platforms.
However ARM SoC's wouldn't function correctly if these registers
are defined as 64 bit. So correcting the definition to two 32 bit registers.
Signed-off-by: Ru
