Add support for the SEC available on a wide range of PowerQUICC devices,
e.g. MPC8349E, MPC8548E.
this initial version supports authenc(hmac(sha1),cbc(aes)) for use with IPsec.
Signed-off-by: Kim Phillips <[EMAIL PROTECTED]>
---
removed priv->status hw interrupt status assignment. Done tasklet no
On Fri, May 30, 2008 at 07:26:38PM +0200, Adrian-Ken Rüegsegger wrote:
>
> I was wondering why you created your own test vectors. Wouldn't standardized
> test vectors by NIST or ANSI be preferable?
If you could post a patch with those that would be very much
appreciated. Thanks!
--
Visit Opens
On Sat, 31 May 2008 01:12:08 +0400
Evgeniy Polyakov <[EMAIL PROTECTED]> wrote:
> On Fri, May 30, 2008 at 03:48:20PM -0500, Kim Phillips ([EMAIL PROTECTED])
> wrote:
> > sorry, by ISR I meant interrupt status registers. but I can't tell
> > where the suspected simultaneous accesses are. Evgeniy,
On Fri, May 30, 2008 at 03:48:20PM -0500, Kim Phillips ([EMAIL PROTECTED])
wrote:
> sorry, by ISR I meant interrupt status registers. but I can't tell
> where the suspected simultaneous accesses are. Evgeniy, can you point
> out the register accesses you're talking about?
priv->status is access
On Fri, 30 May 2008 15:36:50 -0500
Scott Wood <[EMAIL PROTECTED]> wrote:
> Kim Phillips wrote:
> > On Fri, 30 May 2008 15:19:43 -0500
> > Scott Wood <[EMAIL PROTECTED]> wrote:
> >
> >> Kim Phillips wrote:
> >>> On Fri, 30 May 2008 14:41:17 -0500
> >>> Scott Wood <[EMAIL PROTECTED]> wrote:
> >>>
>
On Fri, 30 May 2008 15:19:43 -0500
Scott Wood <[EMAIL PROTECTED]> wrote:
> Kim Phillips wrote:
> > On Fri, 30 May 2008 14:41:17 -0500
> > Scott Wood <[EMAIL PROTECTED]> wrote:
> >
> >> Kim Phillips wrote:
> >>> On Fri, 30 May 2008 22:09:04 +0400
> >>> Evgeniy Polyakov <[EMAIL PROTECTED]> wrote:
>
Kim Phillips wrote:
On Fri, 30 May 2008 15:19:43 -0500
Scott Wood <[EMAIL PROTECTED]> wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood <[EMAIL PROTECTED]> wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov <[EMAIL PROTECTED]> wrote:
Don't
Kim Phillips wrote:
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood <[EMAIL PROTECTED]> wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov <[EMAIL PROTECTED]> wrote:
Don't you want to protect against simultaneous access to register space
from different CPUs? Or it is
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood <[EMAIL PROTECTED]> wrote:
> Kim Phillips wrote:
> > On Fri, 30 May 2008 22:09:04 +0400
> > Evgeniy Polyakov <[EMAIL PROTECTED]> wrote:
> >> Don't you want to protect against simultaneous access to register space
> >> from different CPUs? Or it is sing
On Fri, May 30, 2008 at 02:41:17PM -0500, Scott Wood ([EMAIL PROTECTED]) wrote:
> >>Don't you want to protect against simultaneous access to register space
> >>from different CPUs? Or it is single processor board only?
> >
> >Doesn't linux mask the IRQ line for the interrupt currently being
> >serv
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov <[EMAIL PROTECTED]> wrote:
Don't you want to protect against simultaneous access to register space
from different CPUs? Or it is single processor board only?
Doesn't linux mask the IRQ line for the interrupt currently bein
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov <[EMAIL PROTECTED]> wrote:
> Hi.
>
> On Thu, May 29, 2008 at 02:12:50PM -0500, Kim Phillips ([EMAIL PROTECTED])
> wrote:
>
> > +static irqreturn_t talitos_interrupt(int irq, void *data)
> > +{
> > + struct device *dev = data;
> > + struct
Hi.
On Thu, May 29, 2008 at 02:12:50PM -0500, Kim Phillips ([EMAIL PROTECTED])
wrote:
> +static irqreturn_t talitos_interrupt(int irq, void *data)
> +{
> + struct device *dev = data;
> + struct talitos_private *priv = dev_get_drvdata(dev);
> +
> + priv->status = in_be32(priv->reg + T
Neil Horman wrote:
> On Sat, May 24, 2008 at 10:06:25AM +1000, Herbert Xu wrote:
>> Could you document the source of these vectors in the patch
>> description please?
>
> Sure, reposting
>
> Patch to add checking of DES3 test vectors using CBC mode. FIPS-140-2
> compliance mandates that any sup
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