[ACTIVITY] 12-15 March 2013

== Progress == - Monday was a public holiday - Studied benchmarks and analysed the rtl/asm for redundant sign extensions - Came up with simple test cases based on this (have 6 test cases now) - Looked at gcc tree documentations and helper macros; tried it by adding more debug dumps for types at

[ACTIVITY] 18-22 March 2013

== Progress == - Worked on VRP based zero/sign extension elimination at tree level - Some regression test cases are failing; investigating them == Plan == - Analyse the reason for test case failure and fix them - Extend the code to handle all the possible cases (currently implemented for subset

[ACTIVITY] 25-28 March 2013

== Progress == working on http://cards.linaro.org/browse/TCWG-14 - All but 2 test cases are passing and extension elimination for the simple cases are eliminated - one of the test failure was due to bug with value range propagation pass. Have to investigate this further. - In one instance even t

[ACTIVITY] 2 - 5 Apr 2013

== Summary == - benchmarking coremark with VRP based extension elimination * extension elimination in some cases affecting other optimizations * With this improvements are marginal (details below) == Plan == - study crc where extension elimination is resulting in bad code - Find a solution ==

[ACTIVITY] 8-12 April 2013

== Summary == - http://cards.linaro.org/browse/TCWG-14 Coremark ARM mode gives about 2% performance improvement with about 1% code size reduction. Thumb2 mode however has performance regression even though code size reduces about 0.6%. Performance regression here is like what we are seeing in E

[ACTIVITY] 15-19 April 2013

== Summary == - http://cards.linaro.org/browse/TCWG-13 - performance regression is due to alignment of function. - there is an increase in runtime of core_state_transition even though there is no difference in the code generated with the patch - Adding nops seems to improve the locality an

[ACTIVITY] 22-26 April 2013

== Summary == - http://cards.linaro.org/browse/TCWG-14 - ran into space issues with chromebook and issues running spec2000 locally due to that. Finally reinstalled Ubuntu on 32GB card and set-up everything. - There is a potential issue with zero/sign extension based VRP. - 254.gap goe

[ACTIVITY] 29 APR - 3 May 2013

http://cards.linaro.org/browse/TCWG-14 - Fixed 254.gap infinite loop. - Got spec2k results locally. - LSHIFT and RSHIFT introduces a performance regression for some benchmarks due to missing md pattern. Disabling it improve performance. http://cards.linaro.org/browse/TCWG-55 - Looked

[ACTIVITY] 6 - 10 May 2013

== Done == http://cards.linaro.org/browse/TCWG-14 - Posted patch upstream for review http://cards.linaro.org/browse/TCWG-55 - benchmarking ongoing with git bisect http://cards.linaro.org/browse/TCWG-14 - Discussed the results with ARM maintainers and pinged the original patch. == Plan

[ACTIVITY] 13-17 May 2013

== Progress == http://cards.linaro.org/browse/TCWG-13 - Resolved http://cards.linaro.org/browse/TCWG-14 - Modified patch Posted upstream for review == Plan == http://cards.linaro.org/browse/TCWG-14 - Address and review comments http://cards.linaro.org/browse/TCWG-55 - Reproduce it a

[ACTIVITY] 21-24 May 2013

== Progress == VRP based zero/sign extension - Got some review comments for the patch and started addressing them - split the patch into two; 1. propagating value range and 2. do rtl expansion - testing in progress specfp regression - Benchmarked spec2k for A15 with trunk and couldn't reproduce

[ACTIVITY] 27-31 May 2013

== Progress == * VRP based zero/sign extension - Tested and posted the latest patch * Better end of loop counter optimisation - Tree level optimization are optimized in mainline - Christophe noted a slight change in asm generated from earlier version - tracked down the patch

Failure to optimise (a/b) and (a%b) into single __aeabi_idivmod call

-linaro/divmodsi4-experiments) Any suggestion for best way to handle this? Thanks, Kugan ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain

Re: Failure to optimise (a/b) and (a%b) into single __aeabi_idivmod call

On 05/06/13 21:27, Matthew Gretton-Dann wrote: Kugan, I don't have the source code to hand but how are the sin()/cos()->sincos() optimizations handled? Thanks Matt. There is a tree level pass to combine sin()/cos() into sincos(). Commit that added this is: http://gcc.gnu.org/viewcvs/

Re: Failure to optimise (a/b) and (a%b) into single __aeabi_idivmod call

On 06/06/13 22:03, Mans Rullgard wrote: On 6 June 2013 12:09, Kugan wrote: On 05/06/13 21:27, Matthew Gretton-Dann wrote: Kugan, I don't have the source code to hand but how are the sin()/cos()->sincos() optimizations handled? Thanks Matt. There is a tree level pass to combine s

[ACTIVITY] 2 - 7 June

== Progress == * Better end of loop counter optimisation - Experimented with fixing the extra instruction. - Found a possible way to fix it. Discussing it with Christophe. * Generate a single call to divmod - Looked at the code including how sin()/cos() -> sincos() handling in gcc.

[ACTIVITY] 11-14 June 2013

== Public Holiday == * Monday, 10 June (4 day week) == Progress == * VRP based zero/sign extension - Pinged the patch. * Generate a single call to divmod - Builtin based implementation bootstrapped and passes regression. - posted patch and initiated discussion (http://gcc.gnu.o

[ACTIVITY] 17-21 June 2013

== Progress == * Generate single call to divmod - Addressed review comments - Proposed a new patch for discussion * spec2k comparison between ARM and x86 - Obtained Profile results for both architectures - Analysing gzip and found some register allocation issues. * VRP based

[ACTIVITY] Week 26

== Progress == * spec2k comparison between ARM and x86 - Specfp on x86 has some failures in trunk - Trying 4.8 now - Analysed some of the benchmarks and documenting them - continuing with the rest. == Plan == * Continue with spec2k comparison between ARM and x86 ___

[ACTIVITY] Week 31

== Progress == - Addressed VRP based zero/sign extension elimination review comments - Make check passes but spec2k gcc fails in results comparison; investigating it - Started again with spec2k comparison for ARM to see potential optimization opportunities - Installed libacovea in Chromebo

[ACTIVITY] Week 32

== Progress == * spec2k comparison between ARM and x86 - Read papers/documents that list gcc optimization/problem for arm - Acovea runs fails in Chromebook; Looking into it - continuing with analysing individual results * VRP based zero/sign extension elimination - Final checks

[ACTIVITY] Aug 12-16

== Progress == * spec2k comparison between ARM and x86 - Trying to reproduce some of the earlier optimization studies - Set up Acovea Trying milepost gcc * VRP based zero/sign extension elimination - Posted the modified patch == Plan == * Continue with spec2k comparison between AR

[ACTIVITY] 19 - 23 August 2013

== Progress == * spec2k comparison between ARM and x86 - Analysis ongoing - Preparing to post the results for internal discussions * Back-porting - Back ported all the assigned one - There are some make check failures for thread related test cases with qemu; investigating it

Re: [ACTIVITY] 19 - 23 August 2013

On 26/08/13 17:21, Yvan Roux wrote: Kugan, * Back-porting - Back ported all the assigned one - There are some make check failures for thread related test cases with qemu; investigating it This are known qemu threading issues, don't spend time on it ;) Thanks Yvan. I

[ACTIVITY] Week 35

== Progress == * spec2k comparison between ARM and x86 - Initiated discussion and addressing the feedback - Looking at register allocation (IRA + Reload) for reduced test case and comparing with x86 - Analysed few more spec2k benchmarks * Back-porting - All the back ports are

[ACTIVITY] 2 - 6 September 2013

== Progress == * spec2k comparison between ARM and x86 - More benchmarks analysed. - Plan to complete first iteration for spec2k-int benchmarks this week * Addressing patch review - Woking on vrp based zero/sign extension elimination based on feedback - Started addressing commen

[ACTIVITY] Week 37

== Progress == * Addressing patch review - Woking on vrp based zero/sign extension elimination based on feedback - Reworked the patch based and posted the first patch - Speck2k benchmarking in progress for second patch and will post once finished. * spec2k comparison between ARM a

[ACTIVITY] 16 -20 September 2013

== Progress == * Addressing patch review - zero/sign extension preparation patch accepted. - Christophe is helping to commit. * spec2k comparison between ARM and x86 - Looked at conditional code generation related code in gcc - looked at ifcvt and code in arm.md and arm.c to und

[ACTIVITY] 23 - 27 September 2013

== Progress == * MPFR and GMP Build error with Latest 4.8 Release - Reproduced MPFR error with a simplified testcase - Found the buggy codesequence and the patch that introduced it. - Looking at solution for this - Reprdouced GMP error with -march=armv7-a and -mthumb - continui

MPFR build issue

-02/msg00861.html added this and I guess it is intentional. Am I missing anything here? Thanks, Kugan ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain

[ACTIVITY] Sept 29 - Oct 4

== Progress == * Lnaro 4.8 Bugfix - Fixed Bugs LP1232017 and LP1234060 - gmp and mpfr make check now clean * spec2k comparison between ARM and x86 - Looked at register allocation issues - Started working on slides for connect == Plan == * Continue with spec2k comparison between A

[ACTIVITY] 8 - 11 October 2013

== Progress == * 4 Day week (October 7th Public Holiday) * 64bit division - Looked at libgcc division implementations - Implemented in C "Align divisor shift dividend method" for procssors without div instrusttion - gcc regression now pass with above * spec2k comparison between ARM

[ACTIVITY] Oct 14-18

== Progress == * 64bit division for targets without 32bit div instructions - Finished the implementation - Benchmarked it - Getting ready to post RFC patch * Connect Slides - Worked on slides for connect * Vector regression in 4.8-2013.09 - Started bisecting to find the issue

[ACTIVITY] 4 November - 8 November 2013

== Progress == - Looked into Cbuild2 and current benchmarking scripts - Talked to Rob to understand the requirements and plan for next 2 weeks - Backported gcc testcase fix that causes regression in Linaro 4.8 for armv5te. == Plan == - Taking leave next week. - Start with benchmarking scripts af

[ACTIVITY] 18-22 Nov 2013

== Progress == - cbuild2 benchmarking - Done the initial frame work (just with one benchmark) and sent out for review - 64bit division for ARMv7-A - Posted the patch and added target hook documentation required == Plan == - Address zero/extension review comments - post 64bit divide patch wit

[ACTIVITY] 25-29 Nov 2013

== Progress == - cbuild2 benchmarking - Resolved access issues and imported into repository - continuing with the missing implementations - 64bit division for ARMv7-A - Algorithm is committed to trunk - enablement patch is posted for review - trunk bootstrapping issue - Setup foun

[ACTIVITY] 02-06 December

== Progress == - aarch64 bootstrapping (TCWG-348 4/10) - worked on this posted patch - 64bit divide for Armv7-a (TCWG-26) - Patched committed and Card closed - http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=205444 - http://gcc.gnu.org/viewcvs/gcc?view=revision&revis

[Weekly] 09-13 DEC 2013

== Progress == - aarch64 bootstrapping (TCWG-348 4/10) - patch committed and card closed - http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=205891 - Integrate benchmarking into Cbuildv2 (TCWG-360 6/10) - Adding missing functionality == Plan == - Continue with Integrate

Re: segfault using __thread variable

On 17/12/13 20:38, Matthew Gretton-Dann wrote: > +Ryan, +Kugan, > > On 17 December 2013 08:45, Michael Hudson-Doyle > wrote: >> Will Newton writes: >> >>> On 17 December 2013 07:53, Michael Hudson-Doyle >>> wrote: >>>> Ah... found it!

[ACTIVITY] 16-20 December 2013

== Progress == - Integrate benchmarking into Cbuildv2 (TCWG-360 7/10) - Implementation mostly complete - Started testing to ensure compatible with cbuild1 - Code available for comments at https://git.linaro.org/toolchain/cbuild2.git/shortlog/refs/heads/benchmarking - Binutils B

[ACTIVITY] 23 - 27 December 2013

== Progress == - Short week (25th and 26th public holidays) - Integrate benchmarking into Cbuildv2 (TCWG-360 4/10) - First cut implementation complete and ready for review - Binutils Bug 16340 (2/10) - Posted modified patch after regression testing and analysing the results == P

[ACTIVITY] 30 December 2013 - 3rd January 2014

== Progress == - Short week (4 Days) - TCWG-291 zero/sign extension elimination 4/10 - made re-factoring and ran the regression - benchmarking in progress - TCWG-134 divmod 4/10 - converted into latest pass structure and re-based the patch - found some regression failures

[ACTIVITY] 6-10 January 2014

== Progress == - Zero/sign extension elimination - experimented and discussed upstream. Still no confirmation (2/10) - Bug investigation LP1267122 and LP1263576 (6/10) - CBUILD2 Benchmarking (2/10) - More testing on chrome book == Plan == - Finish CBUILD2 Benchmarking - set-u

[ACTIVITY] 13 - 17 January 2014

== Progress == - TLS GOT binutils patch and gcc fix for aarch64_build_constant are committed upstream. (1/10) - TCWG-360 (closed) (1/10) - TCWG-349 (closed) (4/10) - set-up trunk daily regression (4/10) - Resolved issues running address sanitiser with qemu - started running daily cr

[ACTIVITY] 20 - 24 January 2014

== Misc == - Monday 27/01/2014 - Public holiday == Progress == - LP#1191909: gold and -flto always fails with an internal error on arm-linux-gnueabi* (2/10) - Reproduced it and Looking into the implementation for best fix. -c11-atomic-exec-5.c (4/10) - Issue is due to missing targe

TARGET_ATOMIC_ASSIGN_EXPAND_FENV

be left as NULL_TREE if no code is required in a particular place. The default implementation leaves all three expressions as NULL_TREE. The __atomic_feraiseexcept function from libatomic may be of use as part of the code generated in *update. Thanks, Kugan

[ACTIVITY] 27 - 31 January 2014

== Progress == * 4 Day week (Monday Public Holiday) (6/10) * Posted patches for bugs assigned https://sourceware.org/ml/binutils/2014-01/msg00332.html http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60034 http://gcc.gnu.org/ml/gcc-patches/2014-02/msg00048.html * TARGET_ATOMIC_ASSIGN_EXPAND_FENV

[ACTIVITY] 3 -7 February 2014

== Progress == - Started implementing TARGET_ATOMIC_ASSIGN_EXPAND_FENV (5/10) - Regression testing with the implementation; found some issues and discussed with Matt - Working on fixing them - Patch for Vectorizer generates unaligned access when -mno-unaligned-access committed upstream (2/10)

"invalid expression as operand" in aarch64 inline asm

f I however increase the alignment of .rodata where .LANCHOR0 is defined, this passes. Is alignment of BITS_PER_UNIT valid for SYMBOL_REF? If I change it as I am doing this attached patch, is there anything else I need to do. Thanks, Kugan diff --git a/gcc/config/aarch64/aarch64.c b/gcc/conf

[ACTIVITY] 10-14 FEB 2014

== Progress == - vectorizer (7/10) - Looked into vectorizer target-hooks - enablement of half-float for vectorising; dropped the patch after discussing - Started analysing code generated with unlimited model - gcc 4.8 regression (1/10) - Built Novemnebr and December release (native wi

Re: [ACTIVITY] 10-14 FEB 2014

Hi Ryan, I don’t have any JIRA tickets created for these issues/bugs (there are launchpad bug entries). Do you want me to create JIRA tickets when there isn’t any? Thanks, Kugan On 20/02/14 15:48, Ryan Arnold wrote: > Hi Kugan, in the future it'd help me immensely if you could referen

Re: "invalid expression as operand" in aarch64 inline asm

On 20/02/14 20:18, Matthew Gretton-Dann wrote: > On 12 February 2014 02:29, Kugan wrote: >> Hi, >> >> I finally got around to checking the attached patch for the >> https://bugs.launchpad.net/ubuntu/+source/gcc-4.8/+bug/1270789 >> >> I noticed attached p

[ACTIVITY] Feb 17-21

== Progress == - TCWG-394 (5/10) - Found one more issue, regression tested and posted the patch upstream for review - http://gcc.gnu.org/ml/gcc-patches/2014-02/msg01282.html. - TCWG-395 (1/10) - Started with a google doc for wiki update - Speck regression analysis with 4.7, 4.8 Nov and Dec

[ACTIVITY] Week 11

== Progress == 4 Day week (10/03/2014 - Public holiday) https://cards.linaro.org/browse/CARD-1210 (6/10) - Implemented patch to fix it and bootstrapped gcc - Regression testing pending https://support.linaro.org/tickets/727 (2/10) - Looks like a tool-chain bug - Looking into it https://

[Weekly] 17-21 MAR 2014

== Progress == CARD-1210 - optimizing prologue/epilogue With -fomit-frame-pointer (4/10) - regression tested the patch and fixed issues - Dropping the patch and closing the card as it has been worked on at arm. TCWG-15 - zero/sign extension elimination for crc (3/10) - Looked at crc and lo

[ACTIVITY] 24 - 28 March 2014

== Progress == - TCWG-413 Spec2006 (7/10) - Investigated compiler error for 481.wrf with FSF 4.8.2. Issue is due to aarch64_cm pattern (fcmle and fcmlt supports only #0 as third val). This is already fixed in trunk and Linaro 4.8. - Ran profiling to analyse 4.9 regressions. Started looking in

[ACTIVITY] 1 - 4 April 2014

- TCWG-413 Spec2006 (5/10) - Analysed 456.hmmer - In the process of opening performance bug reports - Started looking at 453.povray - TCWG-291 CRC (2/10) - Not seeing performance improvement with redundant "and" instruction gone - Analysing with perf to see the reason - LP1301335 (3/10)

Re: issue in Compiling GCC for ARMv7-a | Cortex-A9 | Hard Float | vpfv3-d16

686, it is a cross compiler. Is there any specific reason why you don’t want to use toolchain binary releases for this? If you want to build a toolchain yourself, you could consider using a tool like crosstool-ng. Thanks, Kugan ___ linaro-toolchain m

[ACTIVITY] 7 - 11 April 2014

== Progress == * TCWG-413 Spec2006 (6/10) - Setup chroot for aarch64 - Created rootfs with 4.8/trunk and spec2006 - booted created rootfs on foundation model with ubuntu kernel * TCWG-291 CRC (3/10) - posted vrp patch upstream - with that seeing expected performance improvement - analy

[ACTIVITY] 14 - 18 April 2014

== Progress == * TCWG-238 (4/10) - Created scripts and spectools for spec2006 to work with cbuild2 * TCWG-413 Spec2006 (4/10) - Worked out Spec2006 config and src.alt for v1.1 src we have to work correctly - Got it to work natively with Maxim's scripts - Did a trail run in apm openembedde

Re: [ACTIVITY] Week 17

On 26/04/14 03:08, Renato Golin wrote: > == Progress == > > * Holidays (3 days) > - Clearing emails/tasks backlog > - Some post-trip illness > > * AArch64 vs. ARM64 > - Comparing performance of both back-ends What is AArch64 vs. ARM64. Is that something specific

[ACTIVITY] 21-25 April 2014

== Progress == * Short week (21st and 25th are public holidays) (4/10) * TCWG-447 (5/10) * Implemented and tested fenv target hooks, necessary built-ins and md patterns * Posted RFC patches for review for both arm and aarch64 * http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01743.html * http

[ACTIVITY] 28 April - 2 May 2014

== Progress == * TCWG-447 (5/10) * Re-spin few versions of the patches and posted after testing based on reviews. * http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01743.html * http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01744.html * TCWG-413 Spec2006 (5/10) * Updated the scripts to deploy l

[ACTIVITY] 5 - 9 May 2014

== Progress == * TCWG-413 (5/10) - Rebuild FSF 4.8, Linaro 4.8 and Linaro 4.9 releases for aarch64 with crosstool-ng (Kept all the dependencies same and used different gcc). - Lost all the config for running benchmark on the test-machine and set it up again. - Re-ran spec2k benchmarking and res

[RFC][AArch64] Remove CORE_REGS form reg_class

alternate; this might get confused with this. Attached RFC patch removes it. regression tested for aarch64-none-linux-gnu on qemu-aarch64 with now new regression. Is this OK ? Thanks, Kugan gcc/ 2014-05-14 Kugan Vivekanandarajah * config/aarch64/aarch64.c (aarch64_regno_regclass

[ACTIVITY] 12 - 16 May 2014

== Progress == * TCWG-413 (8/10) sha1 performance - Looked at IRA dumps and aarch64 target hooks. - GCC now uses FP registers as register class and this results in lots of fmovs for the test-case. - Discussed in list and tried spill_class hook for aarch64. This helps sha1. - Regression tested t

Re: Using binfmt_misc for cross testing

amount of time we will have to wait to get the session active might be too long depending on the target classes availability. Thanks Kugan > 4. Testing is fired up as if it is normal "native" testing. Whenever kernel > is given an ARM binary to execute -- it passes it off to w

[ACTIVITY] 19 - 23 May 2014

== Progress == * Zero/sign extension elimination (TCWG-15) (9/10) - Initiated discussion and started working on alternate approach to handle this. - Gone through couple of prototype to understand approach. - Finshed first implrmentation; Needs cleanup and some failiures in regression needs fi

[ACTIVITY] 26 - 30 May 2014

== Progress == * Zero/sign extension elimination (TCWG-15) (7/10) - regression tested and fixed all the issues - final bootstrap and regression testing for arm and x86_64 are ongoing - will post the patch for comment after checking the results * benchmarking (TCWG-468) (1/10) - Set-up chr

[ACTIVITY] 2 - 6 May 2014

== Progress == * Zero/sign extension elimination (TCWG-15) (2/10) - Posted patch for comment * benchmarking (TCWG-468) (1/10) - Ran a53 benchmarks * regressions (7/10) - THUMB1 regression for ARM fenv * Issue due to thumb1 not supporting mrc/mcr. Patch to fix this is posted for review.

[ACTIVITY] 9 - 13 June 2014

== Progress == * Public holiday (2/10) * Benchmarking and regression testing (TCWG-468) (8/10) - Ran release benchmarking in chrome-book - Set-up package build environment and ran ubutest - spec2k benchmarking of patches that was included in 2014.06 release on aarch64 == Plan == * Benchma

[ACTIVITY] 16-20 June 2014

== Progress == * Benchmarking and regression testing (TCWG-468) (3/10) - More aarch64 spec2k benchmarking of patches and against fsf 4.9 release - Spec2k a15 benchmarking on chromebook * Zero/sign extension elimination (TCWG-15) (5/10) - Fixed regressions found and broke the patch into two

Re: [Weekly] 23-27 JUNE 2014

> - Provide ldp/stp peephole optimization for Aarch64 [TCWG-446] [2/10] In case you are not aware of, there was an earlier attempt for this and the patch was posted here: https://gcc.gnu.org/ml/gcc-patches/2013-03/msg01051.html Thanks, Ku

[ACTIVITY] 23 - 27 June 2014

== Progress == * Zero/sign extension elimination (TCWG-15) (10/10) - Posted two patches for review and gone through few iterations - Looked at flag_wrapv and !flag_strict_overflow regressions * ARM (and possibly some other targets) truncates negative values and this makes them incompatible wi

Re: [ACTIVITY] 23 - 27 June 2014

will happen only when #define POINTERS_EXTEND_UNSIGNED -1. That means ia64 and s390 seems to be the only targets to test. But Jakub suggested ia64-hpux or x86_64-linux -mx32. Not sure how x86_64-linux -mx32 will fall into this. Thanks, kugan ___ lina

[ACTIVITY] 30 June - 4 July 2014

== Progress == Zero/sign extension elimination (TCWG-291) 10/10 - Patch updated based on review comments. - Regression tested with standard set-up - Created test-cases. - Set-up additional architectures for validation * aarch64-none-elf --with-abi=ilp32 (Foundation model) * aarch64-none-linu

[ACTIVITY] 7-11 July 2014

== Progress == - 8th and 9th on holiday (4/10) - Zero/sign extension elimination (TCWG-291) 3/10 * Patch one is accepted * Posted the modified patch 2 after some discussions * Started analysing the code generated for coremark and spec2k * Looks there are more places that can be improved.

Re: [ACTIVITY] Week 30

s just for the hardware > we have in the lab... It could be the kernel version we use in lab. AFAIK, Charles had some luck profiling with perf on newer kernel. I am not sure about the version though. Thanks, Kugan ___ linaro-toolchain mailing list

[ACTIVITY] 28 July - 1 August 2014

== Progress == - Travelling from TCWG sprint (2/10) - Zero/sign extension elimination (TCWG-291) 2/10 * Posted the modified patch and some discussions. Further testing. -SHA1 regression (TCWG-468) 4/10 * Looked at IRA's uses of back end cost model. It might be a limitation (See the notes be

Re: [ACTIVITY] 28 July - 1 August 2014

of time. I saw one of your old patch for enabling "?" in IRA (I cant find the link now). Is that problem fixed now ? Thanks, Kugan ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain

[ACTIVITY] 4 - 8 August 2014

== Progress == TCWG-445 - AArch64 does not generate post-decrement stores. * Issue resolved with Jiong's prologue/epilogue patch committed to trunk. * Closed the card. TCWG-291 - Zero/sign extensions (5/10) * More review and posted patch based on that which was accepted * Ran full set of vali

[ACTIVITY] 11 - 15 August 2014

== Progress == * Looked at implementation options for backlog cards and closed/postponed cards that doss not benefit or cards that require excessive re-architecture that will not be possible now. (5/10) - TCWG-468 - Postponed after detailed study and discussion. - TCWG-412 (Support literal/constan

[ACTIVITY] 18-22 August 2014

== Progress == * TCWG-413 - Release benchmarking (2/10) - Analysed all the patches gone into the release for performance impact * TCWG-521 - Analysed Coremark and Spec2k for uxt/sxt optimizations TCWG-521(3/10) - Studied Coremark and have additional patches in development for missing cases. * bs

[ACTIVITY] 18 - 22 August 2014

== Progress == * Regression on alphaev68-linux-gnu due to uxt/sxt commit (7/10) - built cross alphaev68-linux-gnu and reproduces it with qemu. - Issue is due to PROMOTE_MODE definition and VRP truncating values. - discussed upstream and after a failed patch, it was suggested that the value rang

[ACTIVITY] 1 - 5 September 2014

== Progress == * Regression on alphaev68-linux-gnu due to uxt/sxt commit (6/10) - posted patch for promoted type based VRP after fixing issues found in bootstrapping and regression testing. But had to drop this as this might have performance implications. https://gcc.gnu.org/ml/gcc-patches/2014-09

[ACTIVITY] 22-26 Sept 2014

== Progress == * LR register not used in leaf functions (TCWG-539) (2/10) Posted the patch after regression testing https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01833.html * AArch64 Spec2006 int regression (3/10) - After struggling to boot Juno, found the combination that works - Ran spec2006 i

[ACTIVITY] 29 September - 3 October 2014

== Progress == * LR register not used in leaf functions (TCWG-539) (1/10) Reviewed Jiong's changes. * bug #412 (2/10) - Seems to have been fixed but since there is not specific test-case except that it happens with spec2k gcc, need more work to be entirely sure. * AArch64 Spec2006 int regression

[ACTIVITY] 6-10 October 2014

== Holiday == * Public Holiday (2/10) * Leave (4/10) == Progress == * Zero/sign extension elimination with widening types (4/10) - Started experimented with a pass for widening type. - Verified for one simple test-case. - Bootstrapping is failing and looking into it. == Plan == * Continue wit

[ACTIVITY] 13 - 17 October 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 9/10) - Fixed ICEs and now can build the cross compiler and do the regression testing with qemu - some test-cases are failing due to condition that rely on overflow; this need fixing. - Bootstrapping on AArch64 sti

[ACTIVITY] 20 - 24 October 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 10/10) - Re-wrote the pass from the results of experiments so far - Fixed most of the regression failures - 5 tests are still failing from C/C++/Fortran regression suite. == Plan == * Continue with Zero/

[ACTIVITY] 27-31 October 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 10/10) - Fixed regression failures - Fixed bootstrapping issues for ARM and AArch64 - Re-factored and added some comments - x86-64 Bootstrapped and regression tested for all languages with forced promotion. There i

[ACTIVITY] 3-7 November 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 9/10) - benchmarked Spec2k and the improvements are very small - Coremark fared worse. Looked into the cases and relaxed some of the constraints. - Subsequent passes are also not optimizing some of the expected case

[ACTIVITY] 10 - 14 November 2014

== Progress == * Zero/sign extension elimination with widening types (5/10) - Addressing comments from the review * Improve block memory operations by GCC (TCWG-142 - 5/10) - Looked at gcc/glibc implementations - Experimented with x86_64 vs ARM and found different implementation decis

[ACTIVITY] 17 - 21 November 2014

== Progress == * Zero/sign extension elimination with widening types (2/10) - Addressing comments from the review * Improve block memory operations by GCC (TCWG-142 - 3/10) -Looked at ARM vs AArch64 * BUG #880 (3/10) - Analysed tree dumps. - Updated bug report with the findings. *

[ACTIVITY] 24-28 November 2014

== Progress == * Zero/sign extension elimination with widening types (1/10) - Addressing comments from the review * BUG #398 #412 (5/10) - built kernel revision with provided config and toolchain binary release to reproduce gcc segafult. Couldn’t reproduce it. Since there is no more d

[ACTIVITY] 1-5 December 2014

== Progress == * Compiler-pass to widen computation to back-end promoted mode (6/10) - Addressed most of the comments. testing it. - Re-based the patch to latest type-safe changes - changed the design to remove CONVERT_EXPRs as much as possible and generated AND_EXPR and SEXT_EXPR - Looking

[ACTIVITY] 8 - 12 December 2014

== Progress == * Compiler-pass to widen computation to back-end promoted mode (2/10) - Looking at generated code with benchmarks - some benchmark analysis with coremark * https://cards.linaro.org/browse/TCWG-486 (3/10) - Reviewed Zhenqiang's and Dmitry's patches and experimented - I have a

[ACTIVITY] 29 December 2014 - 2 January 2015

== Progress == * Back from holiday * Public holiday Thursday (2/10) * TCWG-486 (4/10) - Simplified existing patch - Discussed with Zhenqiang * TCWG-555 (4/10) - propagate wrap/overflow information to ssa == Plan == TCWG-486 and TCWG-555 ___ linar

[ACTIVITY] 5 - 9 January 2015

== Progress == * TCWG-486 (4/10) - Ready to start benchmarking - Discussed with Bernie on new benchmarking set-up - Waiting for Ryan on permission * https://bugs.linaro.org/show_bug.cgi?id=412 (4/10) - Created a reduced test-case and filed upstream bug - looked at GCSE code and ifcvt co

[ACTIVITY] 12-16 January 2015

== Progress == * TCWG-554 (1/10) - Analysing coremark with widen type pass * TCWG-547 (6/10) - Posted patches for vrp based extension elimination for review * Connect Slides (3/10) - Started working == Plan == * Finish connect slides * TCWG-554 ___

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