[CI-NOTIFY]: TCWG Bisect tcwg_gcc_bootstrap/master-arm-bootstrap_debug - Build # 1 - Successful!

Successfully identified regression in *gcc* in CI configuration tcwg_gcc_bootstrap/master-arm-bootstrap_debug. So far, this commit has regressed CI configurations: - tcwg_gcc_bootstrap/master-arm-bootstrap_debug Culprit: commit d881460deb1f0bdfc3e8fa2d391a03a9763cbff4 Author: Harald Anlauf D

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/llvm-release-arm-spec2k6-O3 - Build # 10 - Successful!

Successfully identified regression in *llvm* in CI configuration tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-O3. So far, this commit has regressed CI configurations: - tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-O3 Culprit: commit a838a4f69f500fc8e39fb4c9a1476f162ccf8423 Author: David Green Da

[ACTIVITY] report week ending 20 Aug

Progress: * UM-2 [QEMU upstream maintainership] + We needed an rc4 (as usual) + Tried to work through some of my code review patchlog, notably some big alignment-related series from RTH + Sent patchseries for some small things: + implement last few bits of HSTR trap-to-hypervisor fun

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/llvm-release-arm-spec2k6-O3_LTO - Build # 7 - Successful!

Successfully identified regression in *llvm* in CI configuration tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-O3_LTO. So far, this commit has regressed CI configurations: - tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-O3_LTO Culprit: commit f343a730596b6b02039a91d71dc16c113d09cfe6 Author: Vitaly