RE: [CI-NOTIFY]: TCWG Bisect tcwg_cross/gnu-master-aarch64-build_cross - Build # 35 - Successful!

2021-07-12 Thread Liu, Hongtao
>-Original Message- >From: ci_not...@linaro.org >Sent: Sunday, July 11, 2021 9:59 PM >To: tcwg-validat...@linaro.org; Liu, Hongtao ; linaro- >toolch...@lists.linaro.org >Subject: [CI-NOTIFY]: TCWG Bisect tcwg_cross/gnu-master-aarch64- >build_cross - Build # 35 - Successful! > >Successful

Re: [CI-NOTIFY]: TCWG Bisect tcwg_cross/gnu-master-aarch64-build_cross - Build # 21 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
Hi Florian, This was due to a bug in our bisection scripts. I've disabled notifications to patch authors and linaro-toolchain@ while I'm testing the fix. Sorry for the noise. -- Maxim Kuvyrkov https://www.linaro.org > On Jul 12, 2021, at 9:05 AM, Florian Weimer wrote: > > * ci notify: >

Re: [CI-NOTIFY]: TCWG Bisect tcwg_cross/gnu-master-aarch64-build_cross - Build # 35 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
Hi Hongtao, This was due to a bug in our bisection scripts. I've disabled notifications to patch authors and linaro-toolchain@ while I'm testing the fix. Sorry for the noise. -- Maxim Kuvyrkov https://www.linaro.org > On Jul 12, 2021, at 10:25 AM, Liu, Hongtao wrote: > > > >> -Orig

Re: [CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/gnu-release-arm-spec2k6-O3_LTO - Build # 27 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
Hi Wilco, This report was sent out accidentally, it's for an old patch. Still, it appears that your patch regresses code-speed of several SPEC2k6 benchmarks by up to 16% on 436.cactusADM when compiled with "-marm -O3 -flto". May be worth to look for low-hanging fruit and get some of the perfor

Re: [CI-NOTIFY]: TCWG Bisect tcwg_bmk_tx1/gnu-release-aarch64-spec2k6-O2 - Build # 15 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
Hi Richard, This report was sent out accidentally, due to a mistake in email preferences in our bisection scripts. It appears that your patch regresses code-speed of a single function -- 447.dealII,[.] _ZNK12SparseMatrixIdE5vmultI6VectorIdES3_EEvRT -- by 12%. I don't there is anything worth i

Re: [CI-NOTIFY]: TCWG Bisect tcwg_cross/gnu-master-aarch64-build_cross - Build # 37 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
Hi Joseph, This was due to a bug in our bisection scripts. I've disabled notifications to patch authors and linaro-toolchain@ while I'm testing the fix. Sorry for the noise. -- Maxim Kuvyrkov https://www.linaro.org > On Jul 11, 2021, at 7:36 PM, ci_not...@linaro.org wrote: > > Successfull

Re: [CI-NOTIFY]: TCWG Bisect tcwg_cross/gnu-master-aarch64-build_cross - Build # 33 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
Hi Siddhesh, This was due to a bug in our bisection scripts. I've disabled notifications to patch authors and linaro-toolchain@ while I'm testing the fix. Sorry for the noise. -- Maxim Kuvyrkov https://www.linaro.org > On Jul 11, 2021, at 1:56 PM, ci_not...@linaro.org wrote: > > Successfu

Re: [CI-NOTIFY]: TCWG Bisect tcwg_gnu/gnu-master-arm-bootstrap_debug - Build # 13 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
Hi Martin, [Looks like Linaro TCWG's CI finally works!] It appears that bootstrap_debug on 32-bit ARM (or, likely, any 32-bit architecture) exposes a potential problem in gcc/tree.h. Could you take a look at that? Let us know if it appears specific to 32-bit ARM and we'll investigate on our

Re: [CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/gnu-release-arm-spec2k6-O3_LTO - Build # 27 - Successful!

2021-07-12 Thread Wilco Dijkstra
Hi Maxim, That sounds rather strange, huge differences due to scheduling are very rare. Which micro architecture was this run on? I can try running it on trunk and see what difference it makes with those options. Cheers, Wilco IMPORTANT NOTICE: The contents of this email and any attachments are

Re: [CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/gnu-release-arm-spec2k6-O3_LTO - Build # 27 - Successful!

2021-07-12 Thread Maxim Kuvyrkov
[CC: Richard S.] Hi Wilco, We use Nvidia TK1s (Cortex-A15) for benchmarking on 32-bit ARM. LTO tends to increase functions due to additional inlining, which increases scheduling regions, which increases opportunities for the 1st scheduler for inter-block instruction moves, which increases regi