Hello mister Hope,
this is already solved.
There was -fpie option which cause that problem.
Pardon, i didn't inform you in time.
On 11/22/2012 04:58 AM, Michael Hope wrote:
> On 15 November 2012 01:58, 남관우 wrote:
>> Hi,
>>
>>
>>
>> As your guide, i tried to build again.
>>
>>
>>
>> without :
Hi,
I think I have identified some issues with the atomic builtins, but I want
your advises.
For instance :
A: __atomic_store_n (addr, val, __ATOMIC_SEQ_CST);
gives the armv7 code:
DMB sy
STR r1, [r0]
DMB sy
but if I have well understood, the DMBs instructions only provide the
pro
On 23 November 2012 02:43, Andrey Senkevich wrote:
> Hello mister Hope,
>
> this is already solved.
>
> There was -fpie option which cause that problem.
>
> Pardon, i didn't inform you in time.
Good to hear you have a solution,
-- Michael
___
linaro-t
On 22 November 2012 20:53, Zhenqiang Chen wrote:
> On 21 November 2012 09:20, Zhenqiang Chen wrote:
>> On 21 November 2012 03:26, Michael Hope wrote:
>>> On 20 November 2012 22:10, Zhenqiang Chen wrote:
Hi,
I try ARM, MIPS, PowerPC and X86 on povray benchmark. No one can
shr
Hi Yvan,
There is no issue in the first case. You are correct that the dmb's there are
to ensure the sequential consistency as you'd want to see with __ATOMIC_SEQ_CST
in the call to the builtin. However what you must remember is that STRs are
guaranteed to be single-copy atomic by the architect
On 22 November 2012 20:31, Ramana Radhakrishnan
wrote:
> On systems with LPAE enabled, ldrd and strd are also guaranteed to be atomic
> copies from 64 bit aligned addresses
Not quite (though this is splitting a rather fine hair). ldrd/strd are 64 bit
single-copy atomic for 64 bit aligned addresse
On 23 November 2012 04:25, Michael Hope wrote:
> On 22 November 2012 20:53, Zhenqiang Chen wrote:
>> On 21 November 2012 09:20, Zhenqiang Chen wrote:
>>> On 21 November 2012 03:26, Michael Hope wrote:
On 20 November 2012 22:10, Zhenqiang Chen
wrote:
> Hi,
>
> I try ARM,
