On Fri, 1 Nov 2019 at 13:52, Richard Henderson
wrote:
> The case I'm trying to debug, guest EL1 timer, TGE == 0 && IMO == 1. Which,
> according to D1-10 routes to EL2, and according to D1-13 is not masked by
> PSTATE.
>
> I really don't understand how this is supposed to work.
>
> The only thing
On 10/31/19 2:30 PM, Peter Maydell wrote:
> HCR_EL2.{VI,VF} aren't set by the CPU, they're set by software
> (ie the hypervisor running in QEMU). They're for the situation where
> the hypervisor wants to cause a VIRQ or VFIQ to occur directly
> (ie not because the hypervisor has programmed the GIC
On Thu, 31 Oct 2019 at 13:15, Richard Henderson
wrote:
> As soon as the guest kernel enables interrupts,
>
> arch_timer_starting_cpu
> enable_percpu_irq
> irq_percpu_enable
> gic_unmask_irq
> -- Incorrect exception delivery.
>
> the GTIMER_PHYS interrupt is delivered
