On 4 August 2012 00:53, Richard Earnshaw wrote:
> On 03/08/12 13:49, Mans Rullgard wrote:
>> I have noticed gcc has a preference for generating UXTB instructions
>> when an AND with #255 would do the same thing. This is bad, because
>> on A9 UXTB has two cycles latency compared to one cycle for A
On Fri, Aug 3, 2012 at 3:53 PM, Richard Earnshaw wrote:
> On 03/08/12 13:49, Mans Rullgard wrote:
>> I have noticed gcc has a preference for generating UXTB instructions
>> when an AND with #255 would do the same thing. This is bad, because
>> on A9 UXTB has two cycles latency compared to one cyc
On 3 August 2012 13:53, Richard Earnshaw wrote:
> On 03/08/12 13:49, Mans Rullgard wrote:
>> I have noticed gcc has a preference for generating UXTB instructions
>> when an AND with #255 would do the same thing. This is bad, because
>> on A9 UXTB has two cycles latency compared to one cycle for A
On 03/08/12 13:49, Mans Rullgard wrote:
> I have noticed gcc has a preference for generating UXTB instructions
> when an AND with #255 would do the same thing. This is bad, because
> on A9 UXTB has two cycles latency compared to one cycle for AND. On
> A8 both instructions have one cycle latency.
