On 22/02/13 09:54, Yvan Roux wrote:
Hi Richard,
thanks for the reminding, my previous example was just an attempt to
find the good asm statement constraints to generate a correct ldxp
instruction. My real objective is to implement 128-bit single-copy
atomic load/store and to do this I use ldxp w
Hi Richard,
thanks for the reminding, my previous example was just an attempt to
find the good asm statement constraints to generate a correct ldxp
instruction. My real objective is to implement 128-bit single-copy
atomic load/store and to do this I use ldxp without any matching stxp
for the atomi
On 21/02/13 15:54, Yvan Roux wrote:
Hi,
in the example below I want to explicitly generate a "store exclusive
pair" instruction with an asm statement:
typedef struct {
long unsigned int v1;
long unsigned int v2;
} mtype;
int main () {
mtype val[2] ;
val[0].v1 = 1234;
val[0]
> So stxp %w0, %2, %3, %1 in your inline asm or look out for how this is
> printed in the equivalent sync pattern. I'd look in iterators.md for some of
> the attributes to confirm this.
Hey, thanks Ramana that's it :)
just one more thing, there is a special internal constraint "Ump" on
memory a
> -Original Message-
> From: linaro-toolchain-boun...@lists.linaro.org [mailto:linaro-
> toolchain-boun...@lists.linaro.org] On Behalf Of Yvan Roux
> Sent: 21 February 2013 15:54
> To: linaro-toolchain@lists.linaro.org
> Subject: AArch64 asm statement question
>
> Hi,
>
> in the example b
