[ACTIVITY] 25 February - 1 March 2019

* PR88838 - I have a patch which solves this. * adds iv in Pmode but compare_type in 32bit - It exposes a latent bug in fwprop in regression testing - Looking into it == Plan == * Complete above PRs * Look at GDB BZ #21221 - gdb hangs while stepping an empty loop __

[ACTIVITY] 18-22 February 2019

== Progress == * PR88836 - I have a patch (for backend and CSE) which now passes bootstrap and regression except for one testcase failure (which looks like a pattern issue). Looking into it. * Look at GDB BZ #21221 - gdb hangs while stepping an empty loop - Not convinced that it is a gcc issue.

[ACTIVITY] 11-15 February 2019

== Progress == * PR88834: * Have a patch for ivopt and backend that generates the required addressing mode and code. Still need cleanup and some improvements. * PR88836 Made the required changes to the backend. CSE is still not happening. Looked at CSE in detail and made few changes but still nee

[ACTIVITY] 28 January-1 February 2019

== Progress == * Short week - Annual Leave 2 days - Public Holiday 1 day (Australia day) *SVE ACLE - Revised remaining ACLE patches - svbic revised and reviewed * Auto Vectorizer - Looking at auto vectorisation SVE == Plan == * SVE ACLE * Look at PR88834 ___

Re: [BUG REPORT] The bare-metal toolchains for aarch64 cannot link objects successfully

> return 0; > } > > aarch64-elf-gcc -o test test.c Are you missing -specs=rdimon.specs or similar? Thanks, Kugan > .../gcc-linaro-7.3.1-2018.05-x86_64_aarch64-elf/bin/../aarch64-elf/libc/usr/lib/crt0.o: > In function `_start': > /home/tcwg-buildslave/worksp

[ACTIVITY] 21 - 25 January 2019

== Progress == * SVE ACLE - Revised and reviewed svbic main briant svbic_z for bool * Fixing uninit warning suppression from tree-ch pass - Implemented a patch to handle this and regression test is fine. Will post for review once stage 1 opens * tree-reassoc improvements - Looking at poss

[ACTIVITY] 14-18 January 2019

== Progress == * SVE ACLE - Committed patches for * svabs, svneg, svnot and svsqrt series * svdiv series * svmulh series * svand, svorr, and sveor series * svdot series - Working on svbic and svbic_b variants * Others - Looking into tree-reassoc improvements for

[ACTIVITY] 7 January - 11 January 2019

== Progress == * SVE ACLE - Revised svmla, svmls, svmad and svmsb and committed after getting ACK - Revised again posted for review * svabs, svneg, svnot and svsqrt series * svdiv series * svmulh series * svand, svorr, and sveor series * svdot series == Plan == *

Python test error

i.c'], +'AARCH64' : ['src/aarch64/ffi.c', 'src/aarch64/sysv.S'], } ffi_sources += ffi_platforms['@TARGET@'] ./configure Also tried ./configure --enable-pydebug and --disable-optimization Also tried changing to -O0 manually in the m

[ACTIVITY] 23-27 April 2018

* Short week - a public holiday * Return jump function - Writing up issues with test cases for upstream discussion based on the ipa-cp implementation * LLVM astar regression - Trying to reproduce with trunk LLVM vs trunk gcc - Clang build fails in tx1 (likely due to not enough memory ?) -

[ACTIVITY] 16-20 April 2018

* GCC Benchmarking - Tried Jenkins jobs for trunk benchmarking and posted a patch to fix -std=legacy needed for gfortran - Going over the job definitions to add support for SPEC2017 * LLVM - Looking at spec2006 difference compared to gcc in astar due to speculative devirtualization not happ

Re: LTO support

Hi David, LTO support is present in the toolchain for some time now. GCC support was added in GCC 4.6 and it was continuously improved. Necessary LD support also was added in GNU LD 2.21. Therefore any recent toolchain should be fine. Did you run into any issues using LTO? Thanks, Kugan On 11

Re: [hpc-sig-devel] GCC extensions for `hcqc'

Hi, On 29 August 2017 at 04:54, Masaki Arai wrote: > Hi, > > Thank you very much for your quick check and reply. > > Kugan Vivekanandarajah writes: >> > I looked into the structure, adding this field is not going to make the > s= >> tructure bigger for either IL

Re: [hpc-sig-devel] GCC extensions for `hcqc'

the mem_attrs structure. This does have at least a byte left unlike some other tightly packed structures (gimple and some tree structures in gcc). Thanks, Kugan >> Alternatively, we maybe able to get this info from dwarf info when we >> compile with -g ? > > I doubt you can

Re: [hpc-sig-devel] GCC extensions for `hcqc'

field. This could have implications for memory usage of the compiler. Alternatively, we maybe able to get this info from dwarf info when we compile with -g ? Jim may have some input here (cc ing him). Thanks, Kugan >> >> The extended GCC's output using the option ` -fverbose-asm&

[ACTIVITY] 3 to 6 January 2017

== Activity == - [PR64946] abs vectorization fails for char/short types * Trying to tackle this with ABSU_EXPR * Experimented with implemented in FE vs in gimplification * Hope to get a working prototype this week - Misc * gcc-patches/bug list * Plan for 2017 == Plans for next w

[ACTIVITY] 21-25 November 2016

== Progress == - Posted a revised patch for PR78365 - Fixed ICE and Spec2006 benchmarked type promotion pass * There are couple of mis-compares that needs fixing - Setup perf in r1-a12 and analyzing for type promotion and lto - Documented tasks within reassoc == Plan == - Perf analysis of LTO

[ACTIVITY] 17- 21 October 2016

== Progress == LTO/IPA - Committed propagation of nonnull attribute and optimizations - Committed patch to infer noonull from ADDR_EXPR - Working on a patch to improve ipa-cp unary expressions pass through jump-function * LTO bootstrap is failing in streaming but normal bootst

[ACTIVITY] 10 - 14 October 2016

== Progress == LTO/IPA - Committed ipa-vrp and early-vrp improvements - Patches for propagation of nonnull and optimization are accepted; Will commit after testing (once again) - Noticed some improvements but full benchmarking not yet done - Setting up the benchmarking infrastructure

[ACTIVITY] 12 - 16 Sep 2016

== Progress == - Connect slides - Return jump function - working on prototype - Revised and posted early-vrp - Revised and posted patch for PR72835 == Next == - Work on IPA/LTO improvements - Wrap-up connect slides - Follow up on pending patches _

[ACTIVITY] 5-9 Sept 2016

== Progress == - Connect slides - Analyzed IPA-VRP performance for slides - Started working on return jump function - Reading C++ ABI and other documents referred in Honza's blog to understand the C++ related issues in IPA/LTO = Next == - Work on IPA/LTO improvements - Benchmarking - Fol

[ACTIVITY] 29 August-2 Sept 2016

== Progress == - IPA-VRP: Re-based ipa-cp/ipa-prop on top of Prathameshes commit (quite a few conflicts) and did full testing before posting to the list. Patch approved for commit. - Waiting for Early-VRP patch to commit rest of the patches in the series - All other patches are OK now. - Lookin

[ACTIVITY] 18-22 July 2016

== Progress == * IPA VRP and Early VRP - Posted patch series and revised based on review - Few patches are accepted; others are waiting for re-review * Tree VRP - Converted to use allocpool * Committed upstream tree-reassoc patch for missed optimization due to factoring out CONVERT_EXPR

[ACTIVITY] 30 May-3 June 2016

== Progress == 1 day public holidays IPA VRP - Implemented a version of early VRP. - Verified with simple test cases. - Some test cases are failing in regression testing, looking into it. - Some design decisions need to be firmed up with the upstream discussions. == Plan == - Follow upon

[ACTIVITY] 30 May - 3 June 2016

== Progress == Fixed Bugs and posted patches for review - PR71281 and PR71408 PR66726 - Convert expr - Found way to handle this well and posted a patch. IPA VRP - Started with a simple implementation for intra-procedural early VRP by refactoring tree-vrp. - Still need to handle range domin

[ACTIVITY] 23-27 May 2016

== Progress == PR71252 - ICE in rewrite_expr_tree - Tried various options to fix this and settled on an implementation - Patches sent for upstream review - tested with cpu2006 too - One patch approved PR66726 - Convert expr - Newlib test case is failing due to mi compiled lib - Trying to reduce

[ACTIVITY] 16 - 20 May 2016

== Progress == PR40921 -missed optimization: x + (-y * z * z) => x - y * z * z - Patch committed PR63586 - x+x+x+x -> 4*x in gimple - Patch committed - There were couple of fallouts PR71179 - ICE fold_convert_loc, at fold-const.c:2360 - Patch committed PR71170 - ICE in rewrite_expr_tree, at tre

Re: Issues with accessing TLS of shared object

erence pointers or some steps I might have missed. >> Ian has written a nice blog post about this at: http://www.airs.com/blog/archives/44 Thanks, Kugan ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain

[ACTIVITY] 18 - 22 April 2016

== Progress == * GCC Stage-1 (5/10) - Posted patches and revised based on review - PR40921 and PR63586 - Getting ready post type promotion pass again * Linaro bug (2/10) - BUG 2195 and BIG 1979 - Investigation with trunk and educed test case shows Missing commit * Misc (1/10) - GCC Lis

[ACTIVITY] 4 - 8 April 2016

== Progress == * Type promotion pass (2/10) - Benchmarking * LTO (7/10) - Refactoring tree-vrp to share common parts - Looking at open enhancement bugzilla and working on them * Misc (1/10) - GCC Lists == Plan == * LTO and VRP ___ linaro-tool

[ACTIVITY] 27 March to 1 April 2016

== Progress == * Type promotion pass (4/10) - Tested many different architectures - Branch created - Getting ready to benchmark * LTO (2/10) - Read VRP algorithms - new - Discussing algorithm implementation * Bugs (1/10) - PR70359 * Misc (1/10) - GCC Lists - Jenkins benchmarking

[ACTIVITY] 21 - 25 March 2016

== Progress == * Type promotion pass (6/10) - Fixed major false positive uninit warnings = Changed tree-ssa-uinit to handle SEXT_EXPR = preserving TREE_NO_WARNING set by SRA = Somemore fixes to preserve debug loc - There are still some more but this is mainly due to how tree-s

[ACTIVITY] 14-18 March 2016

== Progress == * LTO (3/10) - Read VRP algorithms * Type promotion pass (2/10) - Rebased and testing - Looking at fixing uninitilazed warning false positives * Misc (1/10) - GCC Lists - Extended validation * Public holiday (2/10) * Connect travel/recovery (2/10) == Plan == * Type pr

Re: gcc 5.2 code quality

disjoint_words (from_4(D), to_6(D), count_2(D)); [tail call] : return; } Thanks, Kugan ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain

[ACTIVITY] 22nd - 26th February

== Progress == - BUGS (6/10) * Posted patches for the bugs https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01974.html https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01927.html https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01905.html * Addressed review comments - Connect

Re: setting loop buffer size in the gcc (aarch64)

(or in general) which uses the > loop buffer size in loop unrolling decision? If yes, could you please > mention the relevant files or code section? Look at this patch for x86: https://gcc.gnu.org/ml/gcc-patches/2013-11/msg02567.html This is implemented using TARGET_LOOP_UNROLL_ADJUST as you have f

[ACTIVITY] 08 - 12 February

== Progress == BUGS (8/10) - PR69708: * Posted a patch to fix. - PR69589: * Posted a patch to fix. - PR66726: * Omitted the patch bu that triggered a bootstrap failure for ppc64. Reverted the patch and looking into it. - Misc (2/10) * gcc/bug list * Undefined behaviors slides for connec

[ACTIVITY] 01 - 05 Feb 2016

== Progress == - LTO and TCWG480 (5/10) * Started testing with the prototype patch * Still trying to figure out what is the best way to set_range_info based on IPA * i.e., how to find the SSA_NAME initialized with PARM_DECL - Misc (5/10) * gcc/bug list * Undefined behaviors slides for c

[ACTIVITY] 25-29 January 2016

== Progress == - Public Holiday (2/10) - LTO and TCWG480 (4/10) * Started with a prototype for VRP * Experimenting with simple test cases - Misc (4/10) * gcc/bug list * LTO and Undefined behaviors slides for connect * Meetings == Plan == * LTO * bugs _

[ACTIVITY] 18-22 January 2016

== Progress == - LTO and TCWG480 (7/10) * Read and experimented with GCC's LTO codebase. * LTO benchmarking for a15 on chromebook * Analyzed regressions with perf - Misc (3/10) * gcc/bug list * Slides for connect presentation * Backpors * Meetings == Plan == * LTO * bugs _

[ACTIVITY] 11th - 15th January

== Progress == - LTO and TCWG480 (6/10) * Read and experimented with GCC's LTO codebase. * Setup archlinux on chromebook and ran coremark with perf * Read referenced publications - PR66726 (2/10) * Rebased the patch * Regression tested on x86_64 and using Chritsope's setup * getting re

[ACTIVITY] 4 - 8 Jan 2016

== Progress == - TCWG480 – IPA-VRP (4/10) * Continue to read/experiment with lto infrastructure * Getting ready to start discussion upstream - PR69194 and PR67714 (5/10) * Posted patch for PR69194 * Revising and testing patch for PR67714 - Misc (1/10) * gcc/bug list * Meetings == Pl

Re: gcc-linaro-5.1 vs gcc-linaro-4.8

Hi Ron, > > Following part of assembly code for fcp function: > > Gcc-5.1: > 40110c: 3dc00c6cldr q12, [x3,#48] > 401110: 3dc0106bldr q11, [x3,#64] > 401114: 3dc0146aldr q10, [x3,#80] > 401118: 3dc01869ldr q9, [x3,#96

[ACTIVITY] 7 Nov - 11 Nov 2015

== Progress == - LTO (8/10) * Looked at ipa-cp * Read LTO papers * Started with ipa-vrp experiment * Reproduced spec2006 issues - Misc (2/10) * gcc/bug list * LuaJIT == Plan == * LTO ___ linaro-toolchain mailing list linaro-toolchain@lists.

[ACTIVITY] Nov 30 - Dec 4, 2015

== Progress == - PR66726 (2/10) * Testing a patch - PR63586 (2/10) * Posted a patch * Revised the patch based on testing - LuaJIT (2/10) * Setup nginx * Still haven't figured out how to use mongodb with nginx (config required). - Misc (2/10) * gcc/bug list * LTO - sick (2/10) ==

[ACTIVITY] 23 - 27 November 2015

== Progress == - tree re-assoc regression (2/10) - Found a test-case to reproduce it. - working on a patch - LuaJIT issue (6/10) * Setup luajit on aarch64 and tried it * tried to reproduce nginx issue with various configs without success - LTO (1/10) * aarch64 bootstrap * ran into an

[ACTIVITY] 16-20 November 2015

== Progress == - Linaro bug 1900 (4/10) * Committed fix to trunk * Will propose back-port to branches after a week - Widening pass (TCWG-547) - 4/10 * Address latest review comments * Posted updated patch to the list - Misc (2/10) * Looked at LuaJIT issue * gcc/bug list == Plan == *

[ACTIVITY] 9-13 November 2015

== Progress == - Widening pass (TCWG-547) - 6/10 * Bootstrapped latest patch on ppc64-linux-gnu, aarch64-linux-gnu and x64-64-linux-gnu. * Regression testing on ppc64-linux-gnu, aarch64-linux-gnu arm64-linux-gnu and x64-64-linux-gnu. * Fixed all of the execution issues * Posted updated patc

[ACTIVITY] 2-6 November 2015

== Progress == - Leave (2/10) - Widening pass (TCWG-547) - 5/10 * Made the latest changes requested in the review * Fixed bootstrap and bootstrap mis-compare for ppc64-linux-gnu * Making uninitialized variable as anonymous ssa (as asked in review) results in few ICEs. * Posted updated patc

[ACTIVITY] 12th - 16th October

== Progress == - Run spec2006 with DS5/Streamline Performance Analyzer (3/10) - Setup DS5 - Setting up client for chromebook which requires kernel rebuild - Widening pass (TCWG-547) - 5/10 * iterated based on review comments * re-wrote GIMPLE_DEBUG handling - Misc (2/10) * gcc/bug list

[ACTIVITY] 5 - 9 October 2015

== Progress == - 1 day off public holiday (2/10) - Upstream patch follow-ups (2/10) * https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html Trying to reproduce 1.cc failure found with Christophe's testing * https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html Committed it and ve

[ACTIVITY] 28 September-2 October 2015​

== Progress == - 1 day off recovering from travel and 1 public holiday (4/10) - https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html (1/10) * Approved patch * re-based and retesting before committing - https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html (1/10) * Found a latent issu

[ACTIVITY] 31th Aug - 04th Sep

== Progress == * Widening pass (TCWG-547) – 6/10 - Looked at “Error: unaligned opcodes detected in executable segment” * Spent lot of time trying to understand the root cause. * Got some suggestions from Jim and looking into it. - Posted some of the important patches for review. * https://

[ACTIVITY] 24th - 28th August

== Progress == * Annual Leave (2/10) * Widening pass (TCWG-547) - 6/10 - Fixed all execution test failure. - bootstrap failure due to “Drop copy-rename” is still not resolved. Found a workaround. - Sorted debug_stmt handling * TACT 1/10 - Started looking to cross execution set-up * Misc - 1

[ACTIVITY] 17th - 21st August

== Progress == * Widening pass (TCWG-547) - 8/10 - Fixed all but one execution test failure. - aarch64 and x86 are clean - arm has one but this looks like a latent issue (in expand); looking into it - Latest trunk with aarch64 miscompiles stage2 fwprop (-fno-forwprop works). This happens with

[ACTIVITY] 10-14 August 2015

== Progress == * Short week due to GNU Cauldron Travel * Widening pass (TCWG-547) - 3/10 - Looked at the false positive warning for uninitialized variable - Have a reduced test-case and looking at ways to fix this - Split the patch for easy review - Fixed test-cases and going through all the t

[ACTIVITY] 27th - 31th July

== Progress == * Widening pass (TCWG-547) - 8/10 - Handled review comments. - Improved CONVERT_EXPR handling. - Re based and retested - found some failures. - This was due to VRP reusing the range info computed in VRP1 after type promotion is applied. Invalidating the range info when type is

[ACTIVITY] 20th - 24th July

== Progress == * Factor conversion out of COND_EXPR - TCWG-849 (5/10) - Iterated through the review and more testing * Looked at widening pass and the test-case from Wilco (1/10) * Misc (2/10) - Connect slides. - gcc-patches, gcc-bugs list - Meetings * Sick (2/10) == Plan == - GCC Bugs - Wi

[ACTIVITY] 13-17 July 2015

== Progress == * Add REG_EQUAL note for arm_emit_movpair (1/10) - Patch2 ok to commit. - Ran complete validation. - Found an issue and posted a patch to fix * Factor conversion out of COND_EXPR - TCWG-849 (6/10) - Found a performance regression in tree-ssa-reasoc - Looked at the tree-ssa-reas

[ACTIVITY] 6-10 July 2015

== Progress == * Add REG_EQUAL note for arm_emit_movpair (1/10) - committed patch1 after testing again * Factor conversion out of COND_EXPR - TCWG-849 (5/10) - Gone through couple of iterations and committed the patch - There are still some improvements need as follow up patches * TACT -TCWG-8

[ACTIVITY] 29 June - 3 July 2015

== Progress == * Add REG_EQUAL note for arm_emit_movpair (1/10) - Updated and reposted - https://gcc.gnu.org/ml/gcc-patches/2015-07/msg00295.html - https://gcc.gnu.org/ml/gcc-patches/2015-06/msg02066.html * Factor conversion out of COND_EXPR - TCWG-849 (3/10) - https://gcc.gnu.org/ml/gcc-patch

[ACTIVITY] 22-26 June 2015

== Progress == * TCWG-849 (1/10) - Committed improvement for VRP https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=225108 * Add REG_EQUAL for arm_emit_movpair (4/10) - Posted patches for review * TACT -TCWG-851 (3/10) - Started with the small examples. - Ran into an error while tuni

[ACTIVITY] 15-19 June

== Progress == * Upstream GCC Bugs(5/10) - PR66554 - PR64130 - PR60001 * Misc (3/10) - Started experimenting with TACT - gcc-patches, gcc-bugs list - Meetings * Sprint recovery (2/10) == Plan == - GCC Bugs - TACT driven optimization exploration for gcc __

Re: Tool for checking coding style in Linaro Toolchain

pts. For gcc, in the contrib directory there is a script called check_GNU_style.sh which can help to some extend. Thanks, Kugan ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain

[ACTIVITY] 25 - 29 May 2015

== Progress == * Upstream GCC (8/10) - TCWG-486 - Optimize Constant Uses in Loops. - Jeff reviewed it and asked for some minor changes - Rebased and redid full testing and posted it - TCWG-555 - Complete re-write of widening pass based on review comments - Getting ready to post for revie

[ACTIVITY] 18-22 May 2015

== Progress == * Upstream GCC (8/10) - vector cost (TCWG-779) - benchmarking complete and analysed - Committed after full testing (bootstrap and regression testing) - Started working on widening pass based on review comments (TCWG-555) - Completed re-factoring with the new ideas - ran

[Weekly] 11-15 MAY 2015

== Progress == * Upstream GCC (5/10) - committed delaying constant splitting in arm after full testing (TCWG-486) - Spec benchmarking is still an issue (TCWG-779) - Bernie agreed to kindly help benchmark it - taking time due to long lava queue - Started working on widening pass based on re

Re: [ACTIVITY] 04 May -- 08 May

On 11/05/15 15:54, Pinski, Andrew wrote: > It would be best to file a bug in glibc then and fix it there. I agree. Let me see if it is present in the trunk as well and file a bug-report. Thanks, Kugan > > From: Kugan > Sent: Sunday, May 10

Re: [ACTIVITY] 04 May -- 08 May

is showing this. I ran into this when I built the cross toolchain for aarch64. I am sure that we are going to have this in tones of places. Thanks, Kugan ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain

[ACTIVITY] 04 May -- 08 May

== Progress == * Upstream GCC (4/10) - TCWG-779 Vector rtx costs for AArch64 ACKed to commit. - Asked to do fresh regression and benchmarking - re-based to latest trunk - Trunk is broken and narrowed down the failure to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66066 - Fixed and regression

27 April -- 01 May 2015

- Public holiday (2/10) == Progress == * Upstream GCC (3/10) - TCWG-796 Zero/sign extension elimination with vrp. - TCWG-555 posted patch for compiler pass to widen computation to back-end promoted mode * IRA (4/10) - Looked at https://bugs.linaro.org/show_bug.cgi?id=540 (TCWG-773 Median of th

[ACTIVITY] 20th - 24th April

== Progress == * Upstream GCC (9/10) - TCWG-780 - Improve register allocation for aarch64_*_sisd_or_int3 patterns. - TCWG-486 - Optimize Constant Uses in Loops. Posted the arm part of the patch that addresses review comments after full testing. Waiting for the cprop review. - TCWG-796 Zero/sign

[ACTIVITY] 13th - 17th April

== Progress == * Upstream GCC (7/10) - Rebased and posted/prepared patches for gcc stage1 for the following - TCWG-780 - Improve register allocation for aarch64_*_sisd_or_int3 patterns - TCWG-779 - Improve codegen for vld2q_f32 and vst2q_f32 - TCWG-486 - Optimize Constant Uses in Loops - Zero

[ACTIVITY] 6 - 10 April 2015

== Progress == * Public holiday (2/10) * Sick (2/10) * TCWG-620 (4/10) - regression tested a version of patch - few regressions lead to reworked it - have a version that passes regression * TCWG-753 and Bug 1373 (1/10) - Al the Back-ports committed - closing the card * Misc (1/10) - gcc

[ACTIVITY] 30 March - 3 April 2015

== Progress == * Public holiday (2/10) * zero/sign extension - TCWG-521 (2/10) - Looked at profile results - Starting aarch64 benchmarking * TCWG-620 (2/10) - Ran into missing pattern issue - Discussed it with Maxim and Jim * TCWG-753 (2/10) - orted few issues with my backporting set-up

[ACTIVITY] 23-27 March 2015

== Progress == * Type promotion pass (zero/sign extension elimination) - TCWG-547 (2/10) - Ran more benchmarks and gathered more data (will post the results) - Need to run perf to analyse regressions * Bug 1373 (1/10) - Set-up back-porting infrastructure - Ran into some issues * TCWG-48

[ACTIVITY] 16-20 March, 2015

== Progress == * type promotion pass (zero/sign extension elimination) - TCWG-547 (6/10) - Fixed LTO testcase failure - Native testing on arm chromebook found three more failures - Fixed all of them - Setup spec2006 on chromebook - spec2006 with -O3 -mfpu=neon -march=armv7-a -fno-common s

[ACTIVITY] 9-13 March 2015

== Progress == * Linaro bugs (2/10) #1325 * type promotion pass (zero/sign extension elimination) - TCWG-547 (5/10) - tried to improve some of the aspects and made it more aggressive - improved handling of CASE_CONVERT - tried it on CoreMark and it reduces the number of instructions in pe

[ACTIVITY] 3rd - 6th March

== Progress == * Linaro bugs (6/10) #1291 #1293, #1314 * Home PC crashed and required hardware upgrade and software re-installation (2/10) * Improve register allocation for AArch64 (TCWG-620) - (1/10) - preparations for benchmarking of proposed changes * Misc (1/10) - gcc-patchs and gcc-bu

[ACTIVITY] 23 - 27 Feb 2015

== Progress == * compiler-pass to widen computation (TCWG-547) - (7/10) - ran into -std=gnu90 issue in compiling spec2k/2006 with the trunk using the new infrastructure - ran benchmarking but the results are not much different - tried with -save-temps but the intermediates are gone. Not sure i

Re: Problems porting Boost.Context to aarch64 gcc

ave to be conservative and save it? Isn’t this problem may occur in other targets like x86 as well? At least x86 defines TARGET_SPILL_CLASS hooks so that integer registers can be spilled to SSE_REGS instead of memory by the register allocator. Shouldn’t this have the same issue? Thanks,

[ACTIVITY] 16th - 20th February

== Progress == * compiler-pass to widen computation (TCWG-547) - (5/10) - Analysed core-mark code size regression - fixed constant handling - Added VRP support for ZEXT_EXPR * Improve register allocation for AArch64 (TCWG-620) - (1/10) - Looked at the relevant patches * Misc (4/10) - Settin

[ACTIVITY] 26 - 30 January 2015

== Progress == * TCWG-554 (2/10) - Looking at subsequent optimisation passes * public holiday (2/10) * Leave (4/10) * Misc (2/10) - Connect preparation - Bugs/gcc-patches list - Looked at IRA == Plan == * Connect preparation * TCWG-554 ___ linaro-t

[ACTIVITY] 19 - 23 January 2015

== Progress == * TCWG-554 (2/10) - Analysing coremark with widen type pass - Looking at subsequent optimization passes * Connect Slides (6/10) - completed * Misc (2/10) - Bugs/gcc-patches list - Looked at IRA == Plan == * TCWG-554 * Public Holiday/Leave (28th to 30th)

[ACTIVITY] 12-16 January 2015

== Progress == * TCWG-554 (1/10) - Analysing coremark with widen type pass * TCWG-547 (6/10) - Posted patches for vrp based extension elimination for review * Connect Slides (3/10) - Started working == Plan == * Finish connect slides * TCWG-554 ___

[ACTIVITY] 5 - 9 January 2015

== Progress == * TCWG-486 (4/10) - Ready to start benchmarking - Discussed with Bernie on new benchmarking set-up - Waiting for Ryan on permission * https://bugs.linaro.org/show_bug.cgi?id=412 (4/10) - Created a reduced test-case and filed upstream bug - looked at GCSE code and ifcvt co

[ACTIVITY] 29 December 2014 - 2 January 2015

== Progress == * Back from holiday * Public holiday Thursday (2/10) * TCWG-486 (4/10) - Simplified existing patch - Discussed with Zhenqiang * TCWG-555 (4/10) - propagate wrap/overflow information to ssa == Plan == TCWG-486 and TCWG-555 ___ linar

[ACTIVITY] 8 - 12 December 2014

== Progress == * Compiler-pass to widen computation to back-end promoted mode (2/10) - Looking at generated code with benchmarks - some benchmark analysis with coremark * https://cards.linaro.org/browse/TCWG-486 (3/10) - Reviewed Zhenqiang's and Dmitry's patches and experimented - I have a

[ACTIVITY] 1-5 December 2014

== Progress == * Compiler-pass to widen computation to back-end promoted mode (6/10) - Addressed most of the comments. testing it. - Re-based the patch to latest type-safe changes - changed the design to remove CONVERT_EXPRs as much as possible and generated AND_EXPR and SEXT_EXPR - Looking

[ACTIVITY] 24-28 November 2014

== Progress == * Zero/sign extension elimination with widening types (1/10) - Addressing comments from the review * BUG #398 #412 (5/10) - built kernel revision with provided config and toolchain binary release to reproduce gcc segafult. Couldn’t reproduce it. Since there is no more d

[ACTIVITY] 17 - 21 November 2014

== Progress == * Zero/sign extension elimination with widening types (2/10) - Addressing comments from the review * Improve block memory operations by GCC (TCWG-142 - 3/10) -Looked at ARM vs AArch64 * BUG #880 (3/10) - Analysed tree dumps. - Updated bug report with the findings. *

[ACTIVITY] 10 - 14 November 2014

== Progress == * Zero/sign extension elimination with widening types (5/10) - Addressing comments from the review * Improve block memory operations by GCC (TCWG-142 - 5/10) - Looked at gcc/glibc implementations - Experimented with x86_64 vs ARM and found different implementation decis

[ACTIVITY] 3-7 November 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 9/10) - benchmarked Spec2k and the improvements are very small - Coremark fared worse. Looked into the cases and relaxed some of the constraints. - Subsequent passes are also not optimizing some of the expected case

[ACTIVITY] 27-31 October 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 10/10) - Fixed regression failures - Fixed bootstrapping issues for ARM and AArch64 - Re-factored and added some comments - x86-64 Bootstrapped and regression tested for all languages with forced promotion. There i

[ACTIVITY] 20 - 24 October 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 10/10) - Re-wrote the pass from the results of experiments so far - Fixed most of the regression failures - 5 tests are still failing from C/C++/Fortran regression suite. == Plan == * Continue with Zero/

[ACTIVITY] 13 - 17 October 2014

== Progress == * Zero/sign extension elimination with widening types (TCWG-546 - 9/10) - Fixed ICEs and now can build the cross compiler and do the regression testing with qemu - some test-cases are failing due to condition that rely on overflow; this need fixing. - Bootstrapping on AArch64 sti

[ACTIVITY] 6-10 October 2014

== Holiday == * Public Holiday (2/10) * Leave (4/10) == Progress == * Zero/sign extension elimination with widening types (4/10) - Started experimented with a pass for widening type. - Verified for one simple test-case. - Bootstrapping is failing and looking into it. == Plan == * Continue wit

[ACTIVITY] 29 September - 3 October 2014

== Progress == * LR register not used in leaf functions (TCWG-539) (1/10) Reviewed Jiong's changes. * bug #412 (2/10) - Seems to have been fixed but since there is not specific test-case except that it happens with spec2k gcc, need more work to be entirely sure. * AArch64 Spec2006 int regression

[ACTIVITY] 22-26 Sept 2014

== Progress == * LR register not used in leaf functions (TCWG-539) (2/10) Posted the patch after regression testing https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01833.html * AArch64 Spec2006 int regression (3/10) - After struggling to boot Juno, found the combination that works - Ran spec2006 i

[ACTIVITY] 1 - 5 September 2014

== Progress == * Regression on alphaev68-linux-gnu due to uxt/sxt commit (6/10) - posted patch for promoted type based VRP after fixing issues found in bootstrapping and regression testing. But had to drop this as this might have performance implications. https://gcc.gnu.org/ml/gcc-patches/2014-09

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