SVE Support ([VIRT-198])
- spin next version of CNT{VCT|FRQ}_EL0 from user-space Message-Id:
<20180518114424.18054-1-alex.ben...@linaro.org> with ID regs :todo
- the HPC guys hit this in their test setups
[VIRT-198] https://projects.linaro.org/browse/VIRT-198
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ lots of code review (including patchsets supporting up to
512 CPUs and lots of PCI devices for KVM virt)
+ put together another target-arm pullreq
* VIRT-164 [improve Cortex-M emulation]
+ Got small-MPU-regions working for read/write;
[TCWG-1424] Profile guided information code size investigation.
- Wrote up initial findings in Jira
- Have written a pass that works with both the new and old pass
manager that I can use to selectively add size optimisation attributes
to functions.
- Spent way too much time trying to work out where
=== Work done during this week ===
* stack-protector failure on GCC ARM: more testing needed
+ rework to introduce new standard pattern including guard's address
computation and make pattern opaque until after register allocation
+ fill in form for new CVE ID and ask feedback on CVE descriptio
