== Progress ==
* Ongoing refactoring of malloc to improve performance
* Preparation for Connect
== Issues ==
* None
== Plan ==
* Linaro Connect US
--
Will Newton
Toolchain Working Group, Linaro
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== Progress ==
* Getting ready for Connect & LLVM US
* Stride Vectorization
- Added some logic to detect read/write reduction, possibly not the best
solution
- Consolidating all discussion into a single document for easy referral
- Creating several bugs (PR17673,PR17677,PR17678,PR17679,PR17680
== Issue ==
* Can not attend LCU'13 due to slow US Visa process.
== Progress ==
* Investigate lp:1243022:
- Root cause: REG_INC note is lost in subreg2 pass, so ira gets
wrong result in function validate_equiv_mem.
- Work out a patch for community review.
* Send conditional compare (CCMP) pa
