Hi,
I tried to generate a binary containing only ARM 32-bit ISA.
The toolchain I used is
gcc-linaro-arm-linux-gnueabihf-4.7-2013.01-20130125_linux.
The compilation options are -O3 -mcpu=Cortex-A15 -marm -static.
I could get 32-bit ARM ISA for my own C code, but not the C lib functions,
such as
st
Some days sick, reduced output...
== Progress ==
* Vectorization
- Global Structures now vectorizing (some access)
- http://llvm.org/viewvc/llvm-project?view=revision&revision=175818
- http://llvm.org/viewvc/llvm-project?view=revision&revision=175898
- Working on remaining cases
* Buildbots
== Progress ==
* smin-umin: waiting for benchmark results with 'coalesce-vars' patch
reverted on trunk.
* libsanitizer: its backtrace printing facility relies on unwinding
info not present by default in binaries. Adding -funwind-tables
improves the results in GCC testsuite.
There is still an inter
Progress:
* updated various Virtualization category cards in cards.linaro.org
with my comments and clarifications
* rebased qemu-linaro on upstream 1.4.0
* upstream code review: pl330 and others
* prompted by LP:1129571 into another look at the linux-user threading
issues. I dusted off an
Hi Richard,
thanks for the reminding, my previous example was just an attempt to
find the good asm statement constraints to generate a correct ldxp
instruction. My real objective is to implement 128-bit single-copy
atomic load/store and to do this I use ldxp without any matching stxp
for the atomi
