On 11/24/2011 03:27 PM, Peter Maydell wrote:
> If it doesn't make sense to hand off cp15 accesses that's fine,
> though -- I want to do this refactoring for the A15 system mode
> implementation in qemu anyway, because I really don't think we
> should try to shoehorn in yet another cpu implementatio
On 24 November 2011 15:32, Ira Rosen wrote:
> * Disabling peeling for low loop bounds also helps with one of EEMBC
> benchmarks, for which vectorization with double-words is more
> beneficial than with quad-words. It turns out that we are able to
> force the alignment for double-words (and, theref
Addressing the comments received from Richard and Ayal regarding the
patch to estimate register pressure.
Testing the patch on eembc and libav micro benchmarks.
Looking at the regressions seen with SMS.
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RAG:
Red:
Amber:
Green: KVM/QEMU work blueprints set up
Current Milestones:
|| || Planned|| Estimate || Actual ||
||upstream-omap3-cleanup|| 2011-11-10 || 2011-12-15 ||||
||cp15-rework || 2012-01-06 ||||||
||i
== GDB ==
* Ongoing work on support for cross-platform core file generation.
Posted a new design proposal to the mailing list to include not
only "info proc mappings", but *all* "info proc" commands. This
would involve a remote protocol command to read arbitrary proc
files, instead
Worked on adding support for 64-bit NEON integer shifts. I have this
working now, although I'm still not very happy about how the register
allocator chooses which mode to use - it prefers core-registers if the
values start or end in core-regs, even though moving to values to NEON
registers migh
