On Wednesday, November 24, 2010 8:29:35 pm Peter Maydell wrote:
> This wiki page came up during the toolchain call:
> https://wiki.linaro.org/Internal/People/KenWerner/AtomicMemoryOperations/
>
> It gives the code generated for __sync_val_compare_and_swap
> as including a push {r4} / pop {r4} pair
== Linaro GCC ==
* Finished testing patch for lp675347 (QT inline-asm atomics), and
send upstream for comments (no response yet). Suggested reverting a
patch (which enabled -fstrict-volatile-bitfields by default on ARM)
locally for Ubuntu in the bug log.
* Continued working on NEON quad-word ve
Andrew Stubbs wrote:
> * Instruction set coverage.
> - Are there any ARM/Thumb2 instructions that we are not taking
> advantage of? [2]
> - Do we test that we use the instructions we do have? [3]
There is no general frame work to test instruction set coverage. The only
way to find out, r
On 29 November 2010 00:18, Michael Hope wrote:
>
> To add to the mix:
>
> Some ideas that are logged as blueprints:
> Using ARMv5 saturated instructions
> (https://blueprints.launchpad.net/gcc-linaro/+spec/armv5-saturated-ops)
> Using ARMv6 SIMD instructions
> (https://blueprints.launchpad.net/
> On the issue of the doloop_end pattern for ARM/Thumb-2 in the context of
> enabling SMS, I actually have tried it in the past. IIRC, I used a
> "subs+bne" assembly sequence then.
Thanks, I'll try it also then.
Revital
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In the ARM architecture: Under ARM mode, the PC(r15) register value is
"address of current insn + 8", while in Thumb mode (including Thumb-2),
it is "address of current insn + 4"
With the way the cbz/cbnz immediate is defined, which is 0--126 (even),
the branch range is then: +4 to +130 :)
OK, thanks for your answer.
Is there other instruction for backward jumps that can be used
to replace cmp to zero+bne?
btw, in the following link of thumb-2 instructions set I understood that
the label can appear before the branch so it was confusing...
CB{N}Z Rn, If Rn {== or !=} 0 then PC := la
Christian Robottom Reis writes:
> On Fri, Nov 26, 2010 at 05:57:57PM +, Richard Sandiford wrote:
>> * More ARM testing of binutils support for STT_GNU_IFUNC.
>>
>> * Implemented the GLIBC support for STT_GNU_IFUNC. Simple ARM testcases
>> seem to run correctly.
>
> Coincidentally I was rea
Unfortunately, cbnz/cbz has a 6-bit:'0' (7-bit aligned to 2) immediate
offset that is *zero extended*, i.e. it is only for forward branches.
Chung-Lin
On 2010/11/29 下午 04:14, Revital1 Eres wrote:
Hello,
I have a question about cbnz/cbz thumb-2 instruction implementation in
thumb2.md file:
I
Hello,
I have a question about cbnz/cbz thumb-2 instruction implementation in
thumb2.md file:
I have an example where we jump to a label which appears before the branch;
for example:
L4
...
cmp r3, 0
bne .L4
It seems that cbnz instruction should be appli
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