Re: [PATCH 18/19] perf: Introduce positive capability for raw events

vent_init = cpumf_pmu_event_init, > > Tangential, but use of perf_sw_context here looks bogus. > It might look strange, but it was done on purpose. For details see commit 9254e70c4ef1 ("s390/cpum_cf: use perf software context for hardware counters") Background was a WARN_ON()

Re: [PATCH 18/19] perf: Introduce positive capability for raw events

type == PERF_TYPE_RAW || >> +   pmu->capabilities & PERF_PMU_CAP_RAW_EVENTS; >> +} >> + >>   static int perf_try_init_event(struct pmu *pmu, struct perf_event *event) >>   { >>   struct perf_event_context *ctx = NULL; >>   int ret; >

[Intel-gfx] Intel-gfx related suspend-to-ram issues on IBM R31

Hi Daniel, hi Ville, thanks for integrating my patches of the DVO chip of my old IBM R31. With this patch in place, dithering on the laptop works now. However, I recently upgraded to Debian Stretch, and since then, I'm having either issues with 3D acceleration or with suspend-to-RAM. Details are

Re: [Intel-gfx] Intel-gfx related suspend-to-ram issues on IBM R31

Hi Ville, Thanks for the pointers. However, which branch of mesa does this drm-tip + https://patchwork.freedesktop.org/patch/176870/ patch apply to? I assume it is the intel-drm-nightly? Tried that, without success. While the 4.9.xx reaches at least S1, this one gets stuck earlier, with or

[Intel-gfx] [PATCH] Fix resume from suspend on IBM X30

make use of the same intel iVCH DVO. Please let me know whether this patch is acceptable. Thanks and have a nice weekend, Thomas >From 457d52863d4dfb9d68091fca5716560dd4eb4441 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Sat, 30 May 2015 20:25:53 +0200 Subject: [PATCH 1/1] Fix resume f

[Intel-gfx] [PATCH] Fix suspend from resume for IBM x30

homas >From 457d52863d4dfb9d68091fca5716560dd4eb4441 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Sat, 30 May 2015 20:25:53 +0200 Subject: [PATCH 1/1] Fix resume from suspend on IBM X30 This patch fixes the resume from suspend-to-ram on the IBM X30 laptop. The problem is caused by the Bios mi

[Intel-gfx] [BUG] Again panning problems on i830 chipsets

Hi folks, when playing with the 4.1.0-rc5 kernel coming from the latest intel-drm-nightly branch yesterday, I noted that this branch again introduces problems with panning on i830 based machines. This panning bug seems to be unrelated to the long-ago resolved mis-configuration of the watermark reg

[Intel-gfx] [PATCH] Fix resume from suspend to RAM on IBM X30 (take two)

making use of the IVCH DVO chip. Greetings, Thomas >From 457d52863d4dfb9d68091fca5716560dd4eb4441 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Sat, 30 May 2015 20:25:53 +0200 Subject: [PATCH 1/1] Fix resume from suspend on IBM X30 This patch fixes the resume from suspend-to-ram

[Intel-gfx] [PATCH] Fix resume from suspend to RAM on IBM X30

been tested by Stefan Monnier, see https://bugs.freedesktop.org/show_bug.cgi?id=49838 for details. Thanks, Thomas >From 8ea307cc203d217cb6513ace045678d06c23ad61 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Fri, 22 May 2015 20:55:54 +0200 Subject: [PATCH 1/1] Fixes for IBM

[Intel-gfx] [PATCH] Enable dithering on the S6010 notebook and others

include this patch in the kernel. Greetings, Thomas >From 3353aee162b45b8a03fa13e470858b5157263831 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Fri, 22 May 2015 19:56:28 +0200 Subject: [PATCH 1/1] Added the dithering enable for the ns2501. This patch enables dithering for notebo

[Intel-gfx] Intel IVCH, Bug 49838

Hi Daniel, hi Ville, as promised, I was recently able to borrow an X30 that - similar to the R31 - features the intel DVO VCH. As Ville mentioned, this notebook suffers from bug #49838, namely the screen is blank after a resume from suspend. With some debugging, I was able to resolve this pr

[Intel-gfx] [PATCH] Enable dithering on NatSemi DVO2501 for Fujitsu S6010

undocumented. Tested on the S6010. Greetings, Thomas Signed-off-by: Thomas Richter This patch enables the (unfortunately undocumented) scaler of the NatSemi 2501 DVO found in the Fujitsu-Siemens S6010 laptop and other machines of the same series and age. Parts of the DVO scaler logic have

[Intel-gfx] [PATCH] Enable dithering for NS 2501 DVO

Hi Daniel, hi Ville, did you get this? Greetings, Thomas Signed-off-by: Thomas Richter This patch enables the (unfortunately undocumented) scaler of the NatSemi 2501 DVO found in the Fujitsu-Siemens S6010 laptop and other machines of the same series and age. Parts of the DVO scaler

[Intel-gfx] [PATCH] Enable dithering for ns2501 DVO (2)

side, the image quality improved notably due to dithering. Greetings, Thomas Signed-off-by: Thomas Richter This patch enables the (unfortunately undocumented) scaler of the NatSemi 2501 DVO found in the Fujitsu-Siemens S6010 laptop and other machines of the same series and age. Parts of the

[Intel-gfx] [PATCH] Enable dithering for ns2501 DVO

to understand the rest of the registers. Greetings, Thomas Signed-off-by: Thomas Richter --- --- dvo_ns2501.c-org2015-04-14 15:34:34.0 +0200 +++ dvo_ns2501.c2015-04-14 23:46:16.0 +0200 @@ -60,6 +60,130 @@ #define NS2501_REGC 0x0c +/* + * The following

[Intel-gfx] ns2501 DVO - success at last

Hi Daniel, hi Ville, some success at last. I couldn't stop myself playing with the NatSemi 2501 DVO in my Fujitsu S6010 and I believe I finally got a hang on this chip. I believe I understand now most of the undocumented registers. There are also a couple of additional features that are, appa

Re: [Intel-gfx] R31 dithering

Am 30.03.2015 um 15:59 schrieb Ville Syrjälä: > On Mon, Mar 30, 2015 at 03:54:29PM +0200, Thomas Richter wrote: >> Am 30.03.2015 um 13:55 schrieb Ville Syrjälä: >>> On Fri, Mar 27, 2015 at 07:57:52PM +0100, Thomas Richter wrote: >> >>>> Thanks and have a nice w

Re: [Intel-gfx] R31 dithering

Am 30.03.2015 um 13:55 schrieb Ville Syrjälä: > On Fri, Mar 27, 2015 at 07:57:52PM +0100, Thomas Richter wrote: >> Thanks and have a nice weekend, > > BTW I think this bug is about failure to restore the ivch to proper > state after suspend (on X30): > https://bugs.freedes

[Intel-gfx] [PATCH] Enable dithering for intel VCH DVO

Hi Daniel, hi Ville, did you get the attached patch? This enables dithering for the iVCH DVO chip and improves image quality for 24 pipes on 18bpp displays greatly. Thanks for reviewing and considering this patch. Thomas Richter >From 3d0b1a15302aa704c7cf4ebbf7c2b8a1566b9beb Mon Sep 17 00

[Intel-gfx] Addressing the intel VCH on the i2c bus / R31 dithering

Hi folks, hi Daniel, hi Ville, thanks again for getting my old Laptops (the R31 and the S6010) back to life. It's been quite a way, but everything looks fine now. There is one interesting observation I made, though, on my IBM R31 laptop: The i830GM graphics supports 24bpp pipes, thought the panel

[Intel-gfx] [PATCH] Enable dithering on intel VCH DVO chips on 18bpp panels

off. There are no ill side effects. Please let me know whether this patch is acceptable. Thanks and greetings, Thomas Signed-off-by: Thomas Richter --- drivers/gpu/drm/i915/dvo_ivch.c | 21 ++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers

[Intel-gfx] R31 dithering

Hi Daniel, hi Ville, thanks for your help. I used now the debug output to research how to enable dithering on the intel VCH. Apparently, it is bit #4 in register VR01 that enables dithering. This is cross-checked by enabling in the dvo_ivch.c file, which greatly improves image quality for 24bpp

Re: [Intel-gfx] [PATCH] drm/i915: Fix SRC_COPY width on 830/845g

instruction. Reported-by: Thomas Richter Signed-off-by: Chris Wilson Cc: Thomas Richter Cc: Jani Nikula Cc: sta...@vger.kernel.org --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu

Re: [Intel-gfx] GPU-hang on i830

Am 10.09.2014 16:00, schrieb Ville Syrjälä: The w/a batch is corrupted. 0x400-0x1000 somehow got turned into zeroes. Both are page boundaries, so I guess trying out Chris's TLB fix would be worth a shot. According to "patch", it is already applied, which is no miracle since I pulled yesterday.

[Intel-gfx] GPU-hang on i830

Hi Daniel, hi Ville, just tried the new 3.17.0+rc4 kernel, though with old userspace (i.e. xserver-xorg-video-intel is *old*, libdrm is old, mesa is old). If I do, I get a "GPU hung" from xorg.conf. The same userspace works fine on 3.15.0 with patches from Ville. Is this expected behavior or

Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

Am 08.09.2014 09:39, schrieb Daniel Vetter: On Fri, Sep 05, 2014 at 09:54:13PM +0300, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä 830 is very unhappy of the watermark value is too low (indicating a very high watermark in fact, ie. memory fetch will occur with an almost full FIFO).

Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

On 06.09.2014 19:33, Ville Syrjälä wrote: The DVO 2x clock fix was missing. I posted a new version. But I think that should only affect the DVO output and not the VGA output. Anyway on my 830 nightly with those two patches is pretty damn good. I'm going to assume this is the first time in histor

Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

On 05.09.2014 20:54, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä 830 is very unhappy of the watermark value is too low (indicating a very high watermark in fact, ie. memory fetch will occur with an almost full FIFO). Limit the watermark value to at least 8 cache lines. That also m

[Intel-gfx] Ping: Status of the i830 code?

Hi Ville, hi Daniel, this is again a "ping" on the status of the i830 code. I reviewed the code I received, at least the code I could review (I do not know enough about the internal wirings of the intel_display source, only on the ns2501 dvo source), but I haven't heart anything back. Is there

Re: [Intel-gfx] S6010 - brightness adjustment not available

Hi Ville just testing your alm_fixes11 branch. So far, everything works fine, including suspend2ram, for the first time! Yippiee! However, there is one thing that bothers me, namely that the brightness adjustment is no longer working. Specifically, fujitsu_laptop fails with: Fujitsu laptop FUJ

Re: [Intel-gfx] [PATCH 16/16] drm/i915: Preserve VGACNTR bits from the BIOS

esn't interfere with the S3 resume fortunately. Signed-off-by: Ville Syrjälä Works on the S6010 as advertized, though cannot test on the R31 since it does not resume from S3 - it does not even reach the real-mode entry hook of the kernel. Tested-by: Thomas Richter --- drivers/gpu

Re: [Intel-gfx] [PATCH v2 15/16] drm/i915: Add pipe B force quirk for 830M

order wrt. double wide handling changes Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 39 +--- 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/dr

Re: [Intel-gfx] [PATCH 14/16] Revert "drm/i915: Nuke pipe A quirk on i830M"

nless both pipes are running. Also it's documented that the DPLL must be enabled on both pipes whenever it's needed. This reverts commit ac6696d3236bd61503f89a1a99680fd7894d5d53. Signed-off-by: Ville Syrjälä Works on both the R31 and the S6010. Reviewed-by: Thomas Richter ---

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Fix DVO 2x clock enable on 830M

1” in both the DPLL A Control Register (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." The pipe A and B force quirks take care of DPLL_VCO_ENABLE, so we just need a bit of special care to handle DPLL_DVO_2X_MODE. Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- d

Re: [Intel-gfx] [PATCH 12/16] drm/i915: Check pixel clock in ns2501 mode_valid hook

et up the 56Hz mode we can't get the magic values for the orther mode. So when checking whether a mode is valid also check the pixel clock so that we filter out the 56Hz variant. Signed-off-by: Ville Syrjälä Reviewed-by: Thomas Richter --- drivers/gpu/drm/i915/dvo_ns2501.c | 6 +++--

Re: [Intel-gfx] [PATCH 11/16] drm/i915: Init important ns2501 registers

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Looks like IEGD does a one time init of these three registers. We don&#

Re: [Intel-gfx] [PATCH 10/16] drm/i915: Rewrite ns2501 driver a bit

le Syrjälä Reviewed-by: Thomas Richter --- drivers/gpu/drm/i915/dvo_ns2501.c | 529 +++--- 1 file changed, 325 insertions(+), 204 deletions(-) diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c index 85030d4..b278571 100644 --- a/d

Re: [Intel-gfx] [PATCH 09/16] drm/i915: Kill useless ns2501_dump_regs

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Signed-off-by: Ville Syrjälä Reviewed-by: Thomas Richter --- drivers/gpu/drm/i915/dvo_ns2501.c | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b

Re: [Intel-gfx] [PATCH 07/16] drm/i915: Enable DVO between mode_set and dpms hooks

-by: Thomas Richter --- drivers/gpu/drm/i915/intel_dvo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index d5ea393..4f115c1 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH 08/16] drm/i915: Don't call DVO mode_set hook on DPMS changes

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Calling the mode_set hook on DPMS changes doesn't seem to be necessary for ns2501. Just drop it. Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- drivers/gpu/drm/i915/intel_dvo.c | 4 1

Re: [Intel-gfx] [PATCH 06/16] drm/i915: ns2501 is on DVOB

On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead of DVOC. FIXME: Maybe need to dig out the correct DVO port from VBT Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- drivers

Re: [Intel-gfx] [PATCH v3 05/16] drm/i915: Disable double wide even when leaving the pipe on

o far. v2: Disable double wide also when turning the pipe off v3: Reorder wrt. force pipe B quirk Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- drivers/gpu/drm/i915/intel_display.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drive

Re: [Intel-gfx] [PATCH 04/16] drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()

On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Just pass the intel_crtc around instead of dev_priv+pipe. Also make intel_wait_for_pipe_off() static since it's only used in intel_display.c. Signed-off-by: Ville Syrjälä Tested-by: Thomas Ri

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Fix gen2 planes B and C max watermark value

value. Tested-by: Thomas Richter Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 24 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 12f4e14..f696b7f 100644 --- a

Re: [Intel-gfx] [PATCH 12/16] drm/i915: Check pixel clock in ns2501 mode_valid hook

. Signed-off-by: Thomas Richter Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/dvo_ns2501.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c index 345235b..4416304 100644 --- a/drivers/gp

Re: [Intel-gfx] [PATCH 11/16] drm/i915: Init important ns2501 registers

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Looks like IEGD does a one time init of these three registers. We don&#

Re: [Intel-gfx] [PATCH 10/16] drm/i915: Rewrite ns2501 driver a bit

o say what these values actually mean, I tried to find some reasonable algorithm to derive them, but had little success. The current set of values is working for the S6010, though probably not for other devices using the same DVO but having a different display size. Signed-off-by: Thomas Richter

Re: [Intel-gfx] [PATCH 09/16] drm/i915: Kill useless ns2501_dump_regs

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Looks perfectly fine to me. Signed-off-by: Thomas Richter Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/dvo_ns2501.c | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/gpu

Re: [Intel-gfx] No boot console/Plane B assertion value on 945GM hardware [FIXED!]

Hi Daniel, hi others, Can you please boot with drm.debug=0xe and grab a new dmesg with the backtrace? Ok, thanks for looking into this, and sorry for taking so long. I'm back now and had now finally some availability to check this issue again with the latest kernel. Seems to be fixed, bo

Re: [Intel-gfx] No boot console/Plane B assertion value on 945GM hardware

On 07.07.2014 17:04, Daniel Vetter wrote: On Sat, Jun 21, 2014 at 01:57:32PM +0200, Thomas Richter wrote: Hi Daniel, dear intel experts, this a bug report for the intel i945GM integrated graphics chipset (*NOT* the 830GM this time). Since at least 3.12.0, but also with the latest intel-drm

Re: [Intel-gfx] 3.16, i915: less colors in X?

Hi Martin, I'm trying to figure out how to ask X what color depth it is using...? I think: martin@merkaba:~> xdpyinfo | grep -i "depth of root" depth of root window:24 planes but am not completely sure. This is thinkpad x60 with Debian 6.0.9. AFAIK the 830GM chipset does not offer

[Intel-gfx] i830GM on IBM R31 works with alm_fixes5 repository

Hi Ville, thanks again for your alm_fixes5 branch. Just installed it on the old R31 - this seems to work fine. The external monitor works (unlike with intel_drm_nightly, which is broken), and watermarks are also setup correctly. Booting works correctly, boot console is setup correctly. Suspen

Re: [Intel-gfx] VGA1 output no longer detected on IBM R31/i830

Am 16.06.2014 19:59, schrieb Daniel Vetter: On Sun, Jun 15, 2014 at 09:38:49PM +0200, Thomas Richter wrote: Thanks for keeping the repository, but that's not a solution, at least not for most of the remaining users of old hardware. Repositories with patches are normal procedures until

Re: [Intel-gfx] VGA1 output no longer detected on IBM R31/i830

Am 15.06.2014 14:26, schrieb Ville Syrjälä: We all know nightly is rather broken with 830. Nothing new here. I suggest just trying my alm_fixes5 branch. Excuse my ignorance, but there is something I do not get. There are patches that are tested and working. Having them in an off-side reposit

Re: [Intel-gfx] [PATCH] drm/i915: Init important ns2501 registers

Hi Ville, Either pipe can drive DVO just fine. Looks like it's using pipe A in your register dump, and all the registers look fine to me. Well, DPLL B VCO enable is off since we don't currently have a mechanism to kick pipe B into action during resume/load. In theory that would need to be enable

Re: [Intel-gfx] [PATCH] drm/i915: Init important ns2501 registers

Hi Ville, thanks for the latest patch. As said, the screen did not come back quite correctly. I checked the register values again, and I am sorry to say that I was wrong - register values do differ. Apparently, the code configures now the wrong pipe to generate output to the DVO and thus the DV

Re: [Intel-gfx] [PATCH] drm/i915: Init important ns2501 registers

Am 09.06.2014 21:46, schrieb ville.syrj...@linux.intel.com: From: Ville Syrjälä In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Thanks, this *almost* works, much better than before. Now I only ne

Re: [Intel-gfx] Partial success - Fixing resume from s2ram on S6010

Hi Ville, dear Intel experts, more on the partial resume from suspend for the S6010. It seems that the culprit is really the lack of a proper initialization of the DVO. The minimum sequence to restore the display does not require to modify the 830 registers directly, but rather needs to setup

Re: [Intel-gfx] Partial success - Fixing resume from s2ram on S6010

Am 09.06.2014 13:31, schrieb Ville Syrjälä: So now you're using acpi_sleep=s3_bios, or nothing? Ok, tried now with acpi_sleep=s3. Unfortunately, this hangs the machine completely during resume, I cannot even ping it. Then, I tried the same trick again, namely unloading the i915 module bef

Re: [Intel-gfx] Partial success - Fixing resume from s2ram on S6010

Am 09.06.2014 13:08, schrieb Ville Syrjälä No, we do restore the mode you were using before suspend. Are you still using vbetool? That would explain why things go bad since vbetool will clobber whatever i915 already did. No, vbetool is out of the equation (see the script attached to the previ

[Intel-gfx] Partial success - Fixing resume from s2ram on S6010

Hi Ville, dear intel experts, without the deadlock in i915, I had at least a partial success in restoring the video on the Fujitsu S6010. Apparently, the bios does not re-initialize the 830MG registers, nor the registers of the ns2501 DVO. Instead, the 830MG is configured in a 640x480 mode (no

[Intel-gfx] Deadlock in intel_enable_pipe_a()

Hi Ville, hi Daniel, dear intel experts, just went through the problem I send around, and I guess I understand now what happens here. The reason *why* resume fails is that there is a deadlock situation in intel_display.c: *) loading the module calls intel_modeset_init() *) intel_modeset_init(

[Intel-gfx] [PATCH] Check for a min level when computing the watermark.

Dear intel experts, the attached patch is a minimally invasive modification of the watermark computation for the 830GM chipset graphics. It adds a minimum watermark level to test against. The minimum value is zero for all other families of the intel chipset graphics, thus causing no change the

[Intel-gfx] Broken suspend/resume on i830 (with debug information)

Dear intel experts, just tried to debug the i830 resume on the S6010. With netconsole and netcat, I found that the kernel locks up when trying to load the i915 module on suspend. Here is the output of the kernel: [ 1772.867519] hid-generic 0003:046D:C05F.002B: input,hidraw0: USB HID v1.11 Mo

[Intel-gfx] [Patch] Add minimum watermark level for I830

Dear Daniel, dear intel experts, please find a minimally-invasive patch to add a minimum watermark level to the current watermark logic. This fixes the flickering and video overlay crashes on 830M(G) chipsets. Note that this patch does not alter the watermark algorithm on any other family of t

Re: [Intel-gfx] [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M

Am 07.06.2014 00:23, schrieb Daniel Vetter: On Fri, Jun 6, 2014 at 11:15 PM, Bob Paauwe wrote: + /* Fujitsu-Siemens Lifebook S6010 VBT lies */ + if (IS_I830(dev)) + return true; My old D945GNT board with a 945G and really old BIOS also has a VBT that lies about this. I gue

Re: [Intel-gfx] Bug reports on 830MG patches (thanks, but more trouble)

Am 06.06.2014 22:08, schrieb Ville Syrjälä: Yup, I flashed the bios last week with version 1.07, the latest I could find on the Fujitsu pages. It was 1.06 before, though I did not observe any difference between 1.06 and 1.07 with respect to the broken resume operation. 1.07 is what have as wel

Re: [Intel-gfx] Bug reports on 830MG patches (thanks, but more trouble)

Hi Ville, hi others, As Ville already said, resume from "suspend-to-ram" is broken. No surprise, old broken bios. However, there is a big difference between the kernel with the pipe-A quirk disabled, and the one with pipe-a and pipe-b quirks enabled: If resumed without the quirk, the display is

[Intel-gfx] Bug reports on 830MG patches (thanks, but more trouble)

Update on the 830MG Updates: As Ville already said, resume from "suspend-to-ram" is broken. No surprise, old broken bios. However, there is a big difference between the kernel with the pipe-A quirk disabled, and the one with pipe-a and pipe-b quirks enabled: If resumed without the quirk, the d

Re: [Intel-gfx] [PATCH 01/15] drm/i915: Use named initializers for gmch wm params

Am 05.06.2014 22:43, schrieb Chris Wilson: On Thu, Jun 05, 2014 at 07:15:50PM +0300, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Using names initializers when filling out the watermark structs saves you from having go look up the struct definition every single time. Signed-off-by:

[Intel-gfx] Bug: Pipe A underrun on resolution switching on 830MG

Hi folks, when switching resolutions with xrandr (or otherwise) on the 830MG chipset, I usually get a "Pipe A underrun" error, sometimes resulting in a completely black screen. To my understanding, the internal screen is connected to pipe B on this laptop, thus I wonder why I get the error. Thu

Re: [Intel-gfx] Breaking suspend/resume by the Pipe A quirk

Am 03.06.2014 17:26, schrieb Chris Wilson: I should have said VGA. Thinking about it, it is likely a shared DDC line so that only a single EDID can be read. Actually, it gets the EDID from the VGA panel just fine, also shows me the modes it supports. DVI1 has no edit, though it gets its allo

Re: [Intel-gfx] Breaking suspend/resume by the Pipe A quirk

Am 03.06.2014 17:14, schrieb Chris Wilson: On Tue, Jun 03, 2014 at 05:04:52PM +0200, Thomas Richter wrote: Am 03.06.2014 16:45, schrieb Daniel Vetter: Yeah, both connectors use CRTC 0. Have you tried what happens if you: - disable DVI1 first (--off) - then enable it on crtc 1? Same

Re: [Intel-gfx] Breaking suspend/resume by the Pipe A quirk

Am 03.06.2014 16:45, schrieb Daniel Vetter: Yeah, both connectors use CRTC 0. Have you tried what happens if you: - disable DVI1 first (--off) - then enable it on crtc 1? Same difference, internal screen goes blank with --off, and stays blank after moving it to crtc 1 if I try to re-enable i

Re: [Intel-gfx] Breaking suspend/resume by the Pipe A quirk

Hi Daniel, dear intel experts, We've put a crtc restriction on VGA (it needs to be crtc 0) to work around some issues. DVI/LVDS should work on crtc 1. You can set this with the --crtc knob for xrandr. Unfortunately, I cannot. Whenever I put DVI1 (which is connected to the internal screen) on c

Re: [Intel-gfx] [Patch] Disabling the pipe A quirk for the Fujitsu S6010

Am 02.06.2014 19:39, schrieb Daniel Vetter: nack = not acknowledged, i.e. rejected. Comes from tcp. I've applied the patch instead to just remove the quirk on all i830M. Ok, thanks, I'm fine with that. Greetings, Thomas ___ Intel-gfx mailin

Re: [Intel-gfx] [Patch] Disabling the pipe A quirk for the Fujitsu S6010

Hi Daniel, From 2006abcd850f8c0995153ffb491efd590103f17f Mon Sep 17 00:00:00 2001 From: thor Date: Mon, 2 Jun 2014 17:32:55 +0200 Subject: [PATCH 2/2] Disabling the pipe A quirk for the Fujitsu S6010. Signed-off-by: thor Like I've explained, this is nacked. I'll merge the patch I've wanted

[Intel-gfx] [Patch] Disabling the pipe A quirk for the Fujitsu S6010

Hi Daniel, hi others, please find a patch attached that disables the pipe A quirk for the Fujitsu S6010. I will probably add a line for the R31 later, I only need to add the model number. How is the watermark-alignment patch for the 830 doing, btw? Greetings, Thomas >From 2006abcd850

Re: [Intel-gfx] Breaking suspend/resume by the Pipe A quirk

Am 02.06.2014 10:27, schrieb Daniel Vetter: Can you go right ahead and please submit this as a patch? Certainly, but I would prefer to get more information on this. Even though the R31 *also* works without the pipe A quirk, I am not sure it does work on all other hardware configurations.

[Intel-gfx] [PATCH] Align i830 watermark to cache lines

Hi folks, as by discussion, the problem with the i830 watermark problems is likely that the 830 requires the number of entries in the buffer to be a multiple of the cache line size. I provide hereby a small patch against intel_pm.c that performs the alignment for GEN2 chips. Tested on the Fuj

[Intel-gfx] Breaking suspend/resume by the Pipe A quirk

Hi Daniel, hi folks, according to my knowledge, the pipe A quirk is unconditionally enabled on the 830 to allow resume to work properly. Unfortunately, it does quite the opposite on the S6010, it breaks resume completely. If the pipe A quirk is disabled, then the boot console works correctly.

[Intel-gfx] 830GM still woes

Hi Daniel, hi folks, still a couple of observations from my side on this. The 1024x786x24 mode here uses a clock of 65MHz (65000kHz), if that is inserted into the watermark computation, it computes from that a prefetch of 40 entries, and thus a watermark level of four, which is much much too hi

Re: [Intel-gfx] 830GM still woes

Am 16.05.2014 18:50, schrieb Daniel Vetter: On Fri, May 16, 2014 at 07:04:54PM +0300, Ville Syrjälä wrote: On Fri, May 16, 2014 at 05:09:53PM +0200, Daniel Vetter wrote: On Fri, May 16, 2014 at 03:41:05PM +0100, Chris Wilson wrote: On Fri, May 16, 2014 at 04:02:48PM +0200, Thomas Richter

[Intel-gfx] 830GM still woes

Hi Daniel, dear list, just tried the latest nightly build of 3.15.0+, and I'm sorry to say that the watermark configuration of the 830GM is still off. This is what I get from the kernel: (not to be taken too serious, but humor is the only thing that keeps me from getting seriously anoyed afte

Re: [Intel-gfx] Fujitsu S6010 still woes (partially)

On 08.04.2014 18:10, Daniel Vetter wrote: On Tue, Apr 8, 2014 at 2:05 PM, Thomas Richter Also, from the linux suspend mechanism, /usr/lib/pm-utils/sleep.d/99video is just useless or breaks more than it helps. I just removed it. It tries some weird workarounds that are not beneficial, and the

Re: [Intel-gfx] Fujitsu S6010 still woes (partially)

Am 08.04.2014 13:37, schrieb Ville Syrjälä: On Tue, Apr 08, 2014 at 11:48:14AM +0200, Thomas Richter wrote: I saw the watermark issue on my S6010 too. I have no good explanation for it since low value in the register means the watermark is actually high. I know )-: So it's a myster

Re: [Intel-gfx] Fujitsu S6010 still woes (partially)

Am 08.04.2014 13:52, schrieb Daniel Vetter: On Tue, Apr 8, 2014 at 11:48 AM, Thomas Richter Hm, my X30 also locks up here on resume. What hack do you apply to make the ns2501 driver get through resume? I don't care about black screen, but I just wonder whether my X30 has the same issue - a

[Intel-gfx] Fujitsu S6010 still woes (partially)

Hi Daniel, dear intel-experts, again I had the chance to test the latest intel-drm-nightly of the 3.14.0 kernel on the Siemens S6010 with its dreadful nso2501 DVO. Unfortunately, there are still a couple of issues here, and I also want to report on some progress and some workarounds. 1) Panning

[Intel-gfx] Fujitsu S6010 still woes (partially)

Hi Daniel, dear intel-experts, again I had the chance to test the latest intel-drm-nightly of the 3.14.0 kernel on the Siemens S6010 with its dreadful nso2501 DVO. Unfortunately, there are still a couple of issues here, and I also want to report on some progress and some workarounds. 1) Pan

Re: [Intel-gfx] Performance drop on XDrawRectangles()

On 01/08/2014 06:10 PM, Chris Wilson wrote: On Wed, Jan 08, 2014 at 04:57:52PM +0100, Thomas Richter wrote: Hi folks, during the changes from 3.12rc7 to 3.13rc4, the performance of XDrawRectangles() dropped considerably. Interestingly, it is not the raw rectangles drawing operations that are

[Intel-gfx] Performance drop on XDrawRectangles()

Hi folks, during the changes from 3.12rc7 to 3.13rc4, the performance of XDrawRectangles() dropped considerably. Interestingly, it is not the raw rectangles drawing operations that are slow, but it seems that the "per-call" overhead has increased by one magnitude. In specific, if you use the

Re: [Intel-gfx] [PATCH 0/2] drm/i915: 830M regression fixes

On 01/07/2014 03:15 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Looks like I managed to break 830M in a few different ways recently. But I recently found one for myself so hopefully that'll not happen again. I have a few other things lined up for 830M, but these are the quick f

[Intel-gfx] Bug/Patch : resolved i830 black screen

Dear intel-experts, a while ago I reported that the latest kernel from intel-drm-nightly broke operations on i830 completely. In the meantime, I found the reason. The trouble is in intel_crtcl_init(): static void intel_crtc_init(struct drm_device *dev, int pipe) { /* * On g

Re: [Intel-gfx] intel-drm-nightly 3.13rc3 broke i830 - more debug

Hi Daniel, Quick shot in the dark: Can you please try the below diff? If that doesn't work please remove the locking in that function completely (i.e. remove the calls to drm_modset_lock|unlock_all). If that doesn't help please compile a pristine -nightly with lockdep (CONFIG_PROVE_LOCKING) re

[Intel-gfx] intel-drm-nightly 3.13rc3 broke i830 - more debug

Hi Daniel, hi folks, here is more debug output from the blank screen/hang on the i830 based laptop: Dec 19 15:48:19 tyleet kernel: [ 10.919155] [drm:drm_pci_init], Dec 19 15:48:19 tyleet kernel: [ 11.317545] lib80211_crypt: registered algorithm 'NULL' Dec 19 15:48:19 tyleet kernel: [ 1

[Intel-gfx] intel-drm-nightly: hang and black screen on i830

Hi Daniel, hi folks, back from a couple of business trips, so finally some time to look into the i830 support on this old laptop. Sorry to say that the current drm-nightly does not work at all. It just generates a hang, resulting in a black screen and nothing else. All you can do there is to

Re: [Intel-gfx] [PATCH 6/6] drm/i915: i830M has watermarks like i855

On 12/02/2013 02:26 PM, Rodrigo Vivi wrote: From: Daniel Vetter So shuffle the checks around a bit. Also give all the structs and functions proper prefixes: i830_ for the dual-pipe mobile platforms and i845_ for the two single-pipe desktop platforms. Note that the max fifo value isn't actually

Re: [Intel-gfx] i830 watermark problems - status?

Hi Daniel, just a short notice that I tried the same patch - namely adjusting the minimum watermark value (thus the maximual watermark setting) now on the i830 based Fujitsu, and it does work here as well as it did on the R31. Thus, this seems to be the real culprit. This is the laptop with

Re: [Intel-gfx] i830 watermark problems - status?

Am 25.11.2013 16:23, schrieb Daniel Vetter: On Mon, Nov 25, 2013 at 04:14:12PM +0100, Thomas Richter wrote: Hi Daniel, hi group, just being curious - what is the status of the i830 watermark problems, i.e. the state of affairs concerning that the i830 does not allow the maximum watermark value

[Intel-gfx] i830 watermark problems - status?

Hi Daniel, hi group, just being curious - what is the status of the i830 watermark problems, i.e. the state of affairs concerning that the i830 does not allow the maximum watermark value, but requires a "headroom" of eight entries to avoid flickering. I provided a patch for this a while ago,

  1   2   >