The current reading of engine utilization has same races. This should
fix most of them while also drastically reducing the update rate needed
on "normal apps".
I left tests/xe_drm_fdinfo running on 2 systems and saw no failures
after 100 iterations.
Lucas De Marchi (3):
drm/xe: Add trace to lrc
Help debugging when LRC timestamp is updated for a exec queue.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_lrc.c | 3 ++
drivers/gpu/drm/xe/xe_trace_lrc.c | 9 ++
drivers/gpu/drm/xe/xe_trace_lrc.h | 52 +++
The exec queue timestamp is only really useful when it's being queried
through the fdinfo. There's no need to update it so often, on every
job_free. Tracing a simple app like vkcube running shows an update
rate of ~ 120Hz.
The update on job_free() is used to cover a gap: if exec
queue is created a
When the exec queue is destroyed, there's a race between a query to the
fdinfo and the exec queue value being updated: after the destroy ioctl,
if the fdinfo is queried before a call to guc_exec_queue_free_job(),
the wrong utilization is reported: it's not accumulated on the query
since the queue w
From: Dnyaneshwar Bhadane
The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD.
Bspec: 69853,69878
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Shekhar Chauhan
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 +++
Quoting Patchwork (2024-10-25 14:44:09-03:00)
>== Series Details ==
>
>Series: drm/i915/xe3lpd: Load DMC
>URL : https://patchwork.freedesktop.org/series/140321/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_15579_full -> Patchwork_140321v1_full
>===
From: Dnyaneshwar Bhadane
When deciding the type of the phy, add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylo
From: Suraj Kandpal
Read PICA register to see if edp over type C is possible and then
add the appropriate tables for it.
--v2
-remove bool from intel_encoder have it in runtime_info [Jani]
-initialize the bool in runtime_info init [Jani]
-dont abbreviate the bool [Jani]
--v3
-Remove useless dis
On Fri, Oct 25, 2024 at 01:47:34PM -0700, Clint Taylor wrote:
> From: Suraj Kandpal
>
> We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI
> encoder. Also remove the Wa comment tag as this follows the bspec and
> does not implement the wa.
>
> v2: add additional definition i
== Series Details ==
Series: drm/i915/xe3lpd: ptl display patches (rev5)
URL : https://patchwork.freedesktop.org/series/140196/
State : warning
== Summary ==
Error: dim checkpatch failed
a6718297a14a drm/i915/xe3lpd: Update pmdemand programming
-:145: CHECK:PARENTHESIS_ALIGNMENT: Alignment sho
== Series Details ==
Series: drm/i915/xe3lpd: ptl display patches (rev5)
URL : https://patchwork.freedesktop.org/series/140196/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Fri, Oct 25, 2024 at 12:45:26PM +0200, Thomas Hellström wrote:
> On Fri, 2024-10-25 at 12:34 +0300, Jani Nikula wrote:
> > On Fri, 25 Oct 2024, Thomas Hellström
> > wrote:
> > > On Thu, 2024-10-24 at 19:22 +, Matthew Brost wrote:
> > > > On Thu, Oct 24, 2024 at 07:52:11PM +0200, Thomas Hell
On Fri, Oct 25, 2024 at 11:31:34AM +0530, Suraj Kandpal wrote:
> Increase the psr max_h limit to 4096.
Commit message doesn't match code (this should probably say max_v
instead of max_h).
Since PSR2 size is supported up to the maximum pipe size now (for both
Xe2 and Xe3) would it be simpler to ju
From: Suraj Kandpal
We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI
encoder. Also remove the Wa comment tag as this follows the bspec and
does not implement the wa.
v2: add additional definition instead of function, commit message typo
fix and update.
v3: restore lost con
== Series Details ==
Series: drm/i915/xe3lpd: ptl display patches (rev5)
URL : https://patchwork.freedesktop.org/series/140196/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15601 -> Patchwork_140196v5
Summary
---
**
From: Mika Kahola
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when
From: Haridhar Kalvala
Signed-off-by: Haridhar Kalvala
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/xe/xe_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 4085bb3b6550..6f73a243c24c 100644
--- a/drivers
From: "Heikkila, Juha-pekka"
Xe3 has no more support for x-tile on display.
v2: Include up to display 29 for X-tiled support. (Gustavo)
Signed-off-by: Heikkila, Juha-pekka
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/int
From: Dnyaneshwar Bhadane
Common display code requires IS_PANTHERLAKE macro.
Define the macro and set 0 as PTL is no longer support for i915.
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h
From: Ravi Kumar Vodapalli
>From platforms xe3 Underrun recovery does not exist
v2: improve DISPLAY_VER checking
BSpec: 68849
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Sai Teja Pottumuttu
---
drivers/gpu/drm/i915/display/intel_d
C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
transaction. Starting with xe3lpd this is bus reset not necessary
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
This series builds on the previous v4, Review Comments have addressed
for the first 2 patches in a series. 1 more VRR related patch dropped.
PTL display enabling patch added.
Clint Taylor (1):
drm/i915/cx0: Remove bus reset after every c10 transaction
Dnyaneshwar Bhadane (3):
drm/i915/ptl: D
From: Matt Roper
There are some minor changes to pmdemand handling on Xe3:
- Active scalers are no longer tracked. We can simply skip the readout
and programming of this field.
- Active dbuf slices are no longer tracked. We should skip the readout
and programming of this field and also
Quoting Taylor, Clinton A (2024-10-22 14:43:52-03:00)
>Reviewed-by: Clint Taylor
Pushed to drm-intel-next. Thanks for the review!
--
Gustavo Sousa
>
>-Clint
>
>On Tue, 2024-10-22 at 12:50 -0300, Gustavo Sousa wrote:
>> Load the DMC for Xe3LPD.
>>
>> Signed-off-by: Gustavo Sousa
>> ---
>> dri
Quoting Patchwork (2024-10-16 18:30:51-03:00)
>== Series Details ==
>
>Series: Miscelaneous fixes for display tracepoints (rev4)
>URL : https://patchwork.freedesktop.org/series/137978/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_15541_full -> Patchwork_137978v4_full
>===
On Thu, Oct 24, 2024 at 02:52:14AM +, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Wednesday, October 23, 2024 11:22 PM
> > To: Atwood, Matthew S
> > Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > Kandpal,
> > Suraj
On Thu, 24 Oct 2024, Clint Taylor wrote:
> From: Suraj Kandpal
>
> Read PICA register to see if edp over type C is possible and then
> add the appropriate tables for it.
>
> --v2
> -remove bool from intel_encoder have it in runtime_info [Jani]
> -initialize the bool in runtime_info init [Jani]
>
== Series Details ==
Series: drm/xe/hdcp: Add check to remove hdcp2 compatibilty (rev3)
URL : https://patchwork.freedesktop.org/series/140291/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15598 -> Patchwork_140291v3
Summar
== Series Details ==
Series: drm/i915: Write source OUI for non-eDP sinks (rev4)
URL : https://patchwork.freedesktop.org/series/140061/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15598 -> Patchwork_140061v4
Summary
-
== Series Details ==
Series: drm/i915: Write source OUI for non-eDP sinks (rev4)
URL : https://patchwork.freedesktop.org/series/140061/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm
On Fri, Oct 25, 2024 at 09:38:35PM +0530, Suraj Kandpal wrote:
> Fix the condition for gsc structure validity in
> gsc_cs_status_check(). It needs to be an OR and not an AND
> condition
>
> Fixes: b4224f6bae38 ("drm/xe/hdcp: Check GSC structure validity")
> Signed-off-by: Suraj Kandpal
Reviewed-
Fix the condition for gsc structure validity in
gsc_cs_status_check(). It needs to be an OR and not an AND
condition
Fixes: b4224f6bae38 ("drm/xe/hdcp: Check GSC structure validity")
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 2 +-
1 file changed, 1 insertion(+),
On 25/10/2024 12:21, Andi Shyti wrote:
On Fri, Oct 25, 2024 at 09:02:16AM +0100, Tvrtko Ursulin wrote:
On 24/10/2024 19:58, Matt Roper wrote:
On Thu, Oct 24, 2024 at 04:09:17PM +0530, Nitin Gote wrote:
There is ENGINE_TRACE() macro which introduce engine name
with GEM tracing in i915. So, i
Make sure that a DP connector detection doesn't happen in parallel
with an ongoing modeset on the connector. The reasons for this are:
- Besides reading the capabilities, EDID etc. the detection may change
the state of the sink (via the AUX bus), for instance by setting the
LTTPR mode or the s
If the source OUI DPCD register value matches the expected Intel OUI
value, the write timestamp doesn't get updated leaving it at the 0
initial value if the OUI wasn't written before. This can lead to an
incorrect wait duration in intel_dp_wait_source_oui(), since jiffies is
not inited to 0 in gene
The eDP sink's capabilities, like DSC, may depend on the source OUI
written to the sink, so ensure the OUI is written before reading out the
capabilities.
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6 inserti
At least the i-tec USB-C Nano 2x Display Docking Station (containing a
Synaptics MST branch device) requires the driver to update the source
OUI DPCD registers to expose its DSC capability. Accordingly update the
OUI for all sink types (besides eDP where this has been done already).
v2: Rebased on
The DP sink's capabilities, like DSC, may depend on the source OUI
written to the sink. On eDP this OUI value could have been reset before
the detection started if the panel power on it got disabled. Make sure
the OUI is re-written at the beginning of detection in this case, before
the sink capabil
While updating the source OUI on the sink the driver should avoid
writing the OUI if it's already up-to-date to prevent the sink from
resetting itself in response to the update. On eDP - the only output
type where the OUI was updated so far - the driver ensured this by
comparing the current source
Reuse intel_dp_detect_dsc_caps() which already checks for the source's
DSC cap and retrieves the DPCD version from the DPRX caps.
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 -
1 file changed, 18 insertions(+), 20
The sink's capabilities, like the DSC caps, depend on the source OUI
written to the sink's DPCD registers and so this OUI value should be
valid for the whole duration of the detection. An eDP sink will reset
this OUI value when the panel power is disabled, so prevent the
disabling - happening by de
This is v5 of [1], with Ville's and Jani's review comments addressed
(patch 1, 2) and Reviewed-bys added (patch 1-7).
Cc: Jani Nikula
Cc: Ville Syrjälä
[1] https://lore.kernel.org/all/20241016132405.2231744-1-imre.d...@intel.com
Imre Deak (8):
drm/i915/dp: Flush modeset commits during connec
> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: Friday, October 25, 2024 8:35 PM
> To: Kandpal, Suraj ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Ghimiray, Himal Prasad
>
> Subject: Re: [PATCH] drm/xe/hdcp: Add check to remo
On 10/24/2024 6:21 PM, Kandpal, Suraj wrote:
-Original Message-
From: Ceraolo Spurio, Daniele
Sent: Thursday, October 24, 2024 9:03 PM
To: Kandpal, Suraj ; intel...@lists.freedesktop.org;
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K ; Ghimiray, Himal Prasad
Subject: Re: [
On Fri, Oct 25, 2024 at 11:49:34AM +0300, Jani Nikula wrote:
> On Fri, 25 Oct 2024, Ville Syrjälä wrote:
> > On Thu, Oct 24, 2024 at 08:11:04PM +0300, Jani Nikula wrote:
> >> Use x100, or ver * 100 + rel, versions for full IP version checks,
> >
> > Have the hardware folks promised to never use mi
On Fri, Oct 25, 2024 at 12:08:50PM +0300, Jani Nikula wrote:
> On Fri, 25 Oct 2024, Raag Jadav wrote:
...
> > +/*
> > + * Available recovery methods for wedged device. To be sent along with
> > device
> > + * wedged uevent.
> > + */
> > +static const char *const drm_wedge_recovery_opts[] = {
>
On Fri, 25 Oct 2024, Gustavo Sousa wrote:
> Quoting Clint Taylor (2024-10-24 19:31:04-03:00)
>>@@ -460,7 +479,8 @@ void intel_pmdemand_program_dbuf(struct drm_i915_private
>>*i915,
>> }
>>
>> static void
>>-intel_pmdemand_update_params(const struct intel_pmdemand_state *new,
>>+intel_pmdemand_up
Quoting Clint Taylor (2024-10-24 19:31:14-03:00)
>From: Mika Kahola
>
>There is a HW issue that arises when there are race conditions
>between TCSS entering/exiting TC7 or TC10 states while the
>driver is asserting/deasserting TCSS power request. As a
>workaround, Display driver will implement a m
Quoting Clint Taylor (2024-10-24 19:31:09-03:00)
>C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
>transaction. Starting with xe3lpd this is bus reset not necessary
>
Yeah. Resetting the bus on every transaction was never part of the Bspec
and it was added as a workaround for issues
== Series Details ==
Series: drm/i915/xe3lpd: Load DMC
URL : https://patchwork.freedesktop.org/series/140321/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15579 -> Patchwork_140321v1
Summary
---
**SUCCESS**
No re
Quoting Clint Taylor (2024-10-24 19:31:04-03:00)
>From: Matt Roper
>
>There are some minor changes to pmdemand handling on Xe3:
> - Active scalers are no longer tracked. We can simply skip the readout
> and programming of this field.
> - Active dbuf slices are no longer tracked. We should skip
== Series Details ==
Series: drm/i915: add GEM_WARN_ON to remap_io_sg
URL : https://patchwork.freedesktop.org/series/140486/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15595 -> Patchwork_140486v1
Summary
---
**SUC
On Fri, Oct 25, 2024 at 09:02:16AM +0100, Tvrtko Ursulin wrote:
>
> On 24/10/2024 19:58, Matt Roper wrote:
> > On Thu, Oct 24, 2024 at 04:09:17PM +0530, Nitin Gote wrote:
> > > There is ENGINE_TRACE() macro which introduce engine name
> > > with GEM tracing in i915. So, it will be good to use ENGI
Since we already have that warning inside `remap_sg` we can also catch
this condition inside `remap_io_sg`.
Signed-off-by: Krzysztof Karas
---
drivers/gpu/drm/i915/i915_mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/
On Fri, 2024-10-25 at 12:34 +0300, Jani Nikula wrote:
> On Fri, 25 Oct 2024, Thomas Hellström
> wrote:
> > On Thu, 2024-10-24 at 19:22 +, Matthew Brost wrote:
> > > On Thu, Oct 24, 2024 at 07:52:11PM +0200, Thomas Hellstrom wrote:
> > > > Hi, Dave & Simona,
> > > >
> > > > This week's drm-xe-
== Series Details ==
Series: Introduce DRM device wedged event (rev6)
URL : https://patchwork.freedesktop.org/series/138069/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15595 -> Patchwork_138069v6
Summary
---
**SUC
On Fri, Oct 25, 2024 at 12:57:50PM +0300, Jani Nikula wrote:
> On Thu, 03 Oct 2024, Ville Syrjälä wrote:
> > On Wed, Oct 02, 2024 at 09:21:59PM +0300, Ville Syrjala wrote:
> >> From: Ville Syrjälä
> >>
> >> Hide the plane->fb/etc. footguns better by stashing them inside
> >> a "legacy" sub struc
Hello @Taylor, Clinton A
This patch can be dropped from here, We are handling this scenario with Ankit's
VRR default timing generator patch series.
https://patchwork.freedesktop.org/series/134383/
-Mitul
> -Original Message-
> From: Intel-gfx On Behalf Of
> Golani, Mitulkumar Ajitkum
== Series Details ==
Series: Introduce DRM device wedged event (rev6)
URL : https://patchwork.freedesktop.org/series/138069/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce DRM device wedged event (rev6)
URL : https://patchwork.freedesktop.org/series/138069/
State : warning
== Summary ==
Error: dim checkpatch failed
da83e6333b1b drm: Introduce device wedged event
-:128: CHECK:LINE_SPACING: Please use a blank line after
func
On Fri, 25 Oct 2024 at 10:46, Ville Syrjälä
wrote:
>
> On Wed, Oct 02, 2024 at 09:21:58PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > An attempt to hide the drm_plane/crtc legacy state better.
> >
> > This also highlights the fact that a lot of supposedly
> > atomic drivers are po
On Fri, 25 Oct 2024, Ville Syrjälä wrote:
> On Wed, Oct 02, 2024 at 09:21:58PM +0300, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> An attempt to hide the drm_plane/crtc legacy state better.
>>
>> This also highlights the fact that a lot of supposedly
>> atomic drivers are poking around in
On Thu, 03 Oct 2024, Ville Syrjälä wrote:
> On Wed, Oct 02, 2024 at 09:21:59PM +0300, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Hide the plane->fb/etc. footguns better by stashing them inside
>> a "legacy" sub struct.
>>
>> Eventually maybe we could turn 'legacy' into a pointer
>> that
== Series Details ==
Series: drm/i915/gsc: test new GSC 102.1.15.1926 for MTL (rev4)
URL : https://patchwork.freedesktop.org/series/140338/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15595 -> Patchwork_140338v4
Summary
-
On 10/24/2024 3:16, Clint Taylor wrote:
From: Dnyaneshwar Bhadane
The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD.
Can we have an empty line here to consider BSpec as part of the git
trailer.
Other than this,
Reviewed-by: Shekhar Chauhan
Bspec: 69853,69878
Signed-off-by: Dny
On Fri, 25 Oct 2024, Thomas Hellström wrote:
> On Thu, 2024-10-24 at 19:22 +, Matthew Brost wrote:
>> On Thu, Oct 24, 2024 at 07:52:11PM +0200, Thomas Hellstrom wrote:
>> > Hi, Dave & Simona,
>> >
>> > This week's drm-xe-next PR
>> >
>> > Thanks,
>> > Thomas
>> >
>> >
>> > drm-xe-next-2024
Hi Dave, Simona,
A bit late, but here it is!
drm-misc-next-2024-10-25:
drm-misc-next for v6.13:
UAPI Changes:
Cross-subsystem Changes:
- Add DT bindings for Sharp Memory LCD.
- Update DT bindings for tc358768.
Core Changes:
- Make the fbdev emulations a drm-client.
- Add a drm-client lib modul
Use x100, or ver * 100 + rel, versions for full IP version checks,
similar to what xe driver does:
- Replace IP_VER(14, 1) inline with 1401, etc.
- Convert DISPLAY_VER_FULL() to DISPLAY_VERx100()
- Convert IS_DISPLAY_VER_FULL() to IS_DISPLAY_VERx100()
- Convert IS_DISPLAY_VER_STEP() to IS_DISPL
== Series Details ==
Series: drm/i915: ensure segment offset never exceeds allowed max (rev3)
URL : https://patchwork.freedesktop.org/series/140374/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15594 -> Patchwork_140374v3
On Fri, 25 Oct 2024, Raag Jadav wrote:
> Introduce device wedged event, which will notify userspace of wedged
> (hanged/unusable) state of the DRM device through a uevent. This is
> useful especially in cases where the device is no longer operating as
> expected even after a reset and has become u
Hi Krzysztof,
> - while (offset >= sg_dma_len(r.sgt.sgp) >> PAGE_SHIFT) {
> - offset -= sg_dma_len(r.sgt.sgp) >> PAGE_SHIFT;
> - r.sgt = __sgt_iter(__sg_next(r.sgt.sgp), use_dma(iobase));
> - if (!r.sgt.sgp)
> - return -EINVAL;
> + if
On Fri, 25 Oct 2024, Ville Syrjälä wrote:
> On Thu, Oct 24, 2024 at 08:11:04PM +0300, Jani Nikula wrote:
>> Use x100, or ver * 100 + rel, versions for full IP version checks,
>
> Have the hardware folks promised to never use minor >= 100?
I guess that's a fair point. Xe uses this extensively, and
Now that we have device wedged event provided by DRM core, make use
of it and support both driver rebind and bus-reset based recovery.
With this in place, userspace will be notified of wedged device on
gt reset failure.
Signed-off-by: Raag Jadav
---
drivers/gpu/drm/i915/gt/intel_reset.c | 3 +++
Add documentation for device wedged event in a new 'Device wedging'
chapter. The describes basic definitions and consumer expectations
along with an example.
v8: Improve documentation (Christian, Rodrigo)
Signed-off-by: Raag Jadav
---
Documentation/gpu/drm-uapi.rst | 75
This was previously attempted as xe specific reset uevent but dropped
in commit 77a0d4d1cea2 ("drm/xe/uapi: Remove reset uevent for now")
as part of refactoring.
Now that we have device wedged event provided by DRM core, make use
of it and support both driver rebind and bus-reset based recovery.
W
Introduce device wedged event, which will notify userspace of wedged
(hanged/unusable) state of the DRM device through a uevent. This is
useful especially in cases where the device is no longer operating as
expected even after a reset and has become unrecoverable from driver
context. Purpose of thi
This series introduces device wedged event in DRM subsystem and uses
it in xe and i915 drivers. Detailed description in commit message.
This was earlier attempted as xe specific uevent in v1 and v2.
https://patchwork.freedesktop.org/series/136909/
Similar work by André Almeida.
https://lore.kerne
== Series Details ==
Series: drm/i915/display: use x100 version for full version and release (rev2)
URL : https://patchwork.freedesktop.org/series/140454/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15594 -> Patchwork_140454v2
On Wed, 23 Oct 2024, Gustavo Sousa wrote:
> The variable crtc_state already contains everything that
> intel_c20_compute_hdmi_tmds_pll() needs. Simplify the function's
> signature by passing that struct instead of separate variables.
>
> Suggested-by: Jani Nikula
> Signed-off-by: Gustavo Sousa
Quoting Matt Atwood (2024-10-18 17:49:41-03:00)
>From: Mika Kahola
>
>There is a HW issue that arises when there are race conditions
>between TCSS entering/exiting TC7 or TC10 states while the
>driver is asserting/deasserting TCSS power request. As a
>workaround, Display driver will implement a ma
From: Dnyaneshwar Bhadane
When deciding the type of the phy, add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylo
From: Ville Syrjälä
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the color management
code to use it (as much as possible at this stage).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c| 636 +-
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch vlv_wait_port_ready() over to
it. The main motivation to do just one function is to stop passing i915
to intel_de_wait(), so its generic wrapper can be removed.
Reviewed-by: Rodrigo Vivi
On Thu, Oct 24, 2024 at 08:11:04PM +0300, Jani Nikula wrote:
> Use x100, or ver * 100 + rel, versions for full IP version checks,
Have the hardware folks promised to never use minor >= 100?
> similar to what xe driver does:
>
> - Replace IP_VER(14, 1) inline with 1401, etc.
>
> - Convert DISPLA
== Series Details ==
Series: drm/i915/display: convert I915_STATE_WARN() to struct intel_display
URL : https://patchwork.freedesktop.org/series/140444/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15588 -> Patchwork_140444v1
===
== Series Details ==
Series: drm/i915/display: use x100 version for full version and release (rev2)
URL : https://patchwork.freedesktop.org/series/140454/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/display: use x100 version for full version and release (rev2)
URL : https://patchwork.freedesktop.org/series/140454/
State : warning
== Summary ==
Error: dim checkpatch failed
2a11c9d84f96 drm/i915/display: use x100 version for full version and release
-:1
> -Original Message-
> From: Intel-gfx On Behalf Of Clint
> Taylor
> Sent: 25 October 2024 04:01
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH v4 10/11] drm/i915/xe3lpd: Skip disabling VRR during
> modeset disable
>
> From: Ravi Kumar Vodapalli
On Fri, Oct 25, 2024 at 12:54:45PM +0530, Nautiyal, Ankit K wrote:
>
> On 10/25/2024 11:51 AM, Ville Syrjälä wrote:
> > On Fri, Oct 25, 2024 at 11:31:32AM +0530, Suraj Kandpal wrote:
> >> Fix the plane max height and width limits taking into account the
> >> joined pipe limits too.
> >>
> >> Bspec
On 24/10/2024 19:58, Matt Roper wrote:
On Thu, Oct 24, 2024 at 04:09:17PM +0530, Nitin Gote wrote:
There is ENGINE_TRACE() macro which introduce engine name
with GEM tracing in i915. So, it will be good to use ENGINE_TRACE()
over drm_err() drm_device based logging for engine debug log.
Doesn
The display platform enums are not really needed for anything. Remove.
Without the enum, PLATFORM_UNINITIALIZED is also no longer needed for
keeping the first enum 0. Also need to switch from sp->subplatform to
sp->pciidlist as the check for array end.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ja
This series builds on the previous v2, further enabling new features
for the platform. 1 patch drop at the request of the author.
Clint Taylor (1):
drm/i915/cx0: Remove bus reset after every c10 transaction
Dnyaneshwar Bhadane (3):
drm/i915/ptl: Define IS_PANTHERLAKE macro
drm/i915/cx0: Ex
On 10/25/2024 1:18 AM, Matt Roper wrote:
On Thu, Oct 24, 2024 at 05:16:51PM +0530, Nautiyal, Ankit K wrote:
On 10/24/2024 9:25 AM, Suraj Kandpal wrote:
DISPLAY_VER >= 30 onwards CRTC can now support 6k resolution.
Increase pipe and plane max width and height to reflect this
Only max width is
On Wed, Oct 02, 2024 at 09:21:58PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> An attempt to hide the drm_plane/crtc legacy state better.
>
> This also highlights the fact that a lot of supposedly
> atomic drivers are poking around in the legacy crtc state,
> which is rather questionab
From: Mika Kahola
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when
On Thu, 2024-10-24 at 19:22 +, Matthew Brost wrote:
> On Thu, Oct 24, 2024 at 07:52:11PM +0200, Thomas Hellstrom wrote:
> > Hi, Dave & Simona,
> >
> > This week's drm-xe-next PR
> >
> > Thanks,
> > Thomas
> >
> >
> > drm-xe-next-2024-10-24:
> > UAPI Changes:
> > - Define and parse OA sync p
DISPLAY_VER >= 30 onwards CRTC can now support 6k resolution.
Increase pipe and plane max width and height to reflect this
increase in resolution.
--v2
-Take care of the subsampling scenario sooner rather than later [Matt]
--v3
-Take care of the joined pipe limits too [Ankit/Matt]
Signed-off-by:
Make the subplatform initialization less cramped, and follow the coding
style more closely. Initialize .pciidlist using designated initializers.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 116 +-
1 file changed, 88 in
Rebase and split patch 2 from, otherwise the same.
BR,
Jani.
[1] https://lore.kernel.org/r/cover.1729612605.git.jani.nik...@intel.com
Jani Nikula (12):
drm/i915/gmbus: convert to struct intel_display
drm/i915/cx0: remove unnecessary includes
drm/i915/cx0: convert to struct intel_display
== Series Details ==
Series: Add 6k resolution support for a single CRTC (rev3)
URL : https://patchwork.freedesktop.org/series/139978/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15593 -> Patchwork_139978v3
Summary
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