On Tue, Nov 04, 2014 at 04:51:38AM -0800, Rodrigo Vivi wrote:
>
> This is another drm-intel-collector updated notice:
> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
>
> Here goes the update list in order for better reviewers assignment:
>
> Patch drm/i915: Check
On Thu, Nov 06, 2014 at 09:26:39AM +0200, Ander Conselvan de Oliveira wrote:
> @@ -9424,73 +9424,24 @@ static void intel_do_mmio_flip(struct intel_crtc
> *intel_crtc)
>
> if (atomic_update)
> intel_pipe_update_end(intel_crtc, start_vbl_count);
> -
> - spin_lock_irq(&dev_p
On Wed, Nov 05, 2014 at 02:42:00PM -0800, Volkin, Bradley D wrote:
> For this part, I've got an implementation that works ok but one difference is
> that if we stop submitting batches, and therefore stop calling batch_pool_get,
> we stop moving buffers to the batch pool's inactive list. This means
So that it can be used by the flip code to wait for rendering without
holding any locks.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_gem.c | 20 +++-
2 files changed, 16 insertions(+), 9 deletions(-)
diff
This simplifies the code quite a bit compared to iterating over all
rings during the ring interrupt.
Also, it allows us to drop the mmio_flip spinlock, since the mmio_flip
struct is only accessed in two places. The first is when the flip is
queued and the other when the mmio writes are done. Since
On 06.11.2014 01:48, Rodrigo Vivi wrote:
> Using dispatch mask cause hangs waiting PS Done on some cases like bug #83207,
> with larger screen or when scaling it.
>
> Also mesa uses VMask instead of Dmask for 3DSTATE_PS because in some cases
> they were getting incorrect derivatives for subspans.
From: Tom O'Rourke
Based on sandybridge_pcode_write, haswell_pcode_write has an
additional field for address control.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_pm.c |9 +++--
3 files ch
From: Tom O'Rourke
These patches update the turbo minimum frequency to
match the values used for Windows and Android. The
refactoring in Imre's recent series
"[Intel-gfx] [PATCH 0/8] sanitize RPS interrupt enabling/disabling"
conflicts with these changes. Those conflicts should
not be diff
From: Tom O'Rourke
Set the min_freq_softlimit to max(RPe, 450MHz).
Setting a floor can ensure a minimum experience
level. The 450MHz value came from a power and
performance study of various types of workloads
(3D, Media, GPGPU, idle, etc).
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915
From: Tom O'Rourke
Updated gen6|8_enable_rps() for Haswell and Broadwell
to use the efficient frequency read from pcode.
Added hsw_use_efficient_freq() to read efficient
frequency (aka RPe) from pcode. The efficiency is
based on the frequency/power ratio (MHz/W); this is
considering GT power an
Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
MOCS can still be used though. But if userspace is trusting PTE for
cache selection the safest thing to do is to let caches disabled.
BSpec: "For GGT
Just a warning that this round collector had many differences on PRTS:
HSw:
Testing: http://tinderbox.sh.intel.com/PRTS_UI/prtsresult.php?task_id=3869
Collector: http://tinderbox.sh.intel.com/PRTS_UI/prtsresult.php?task_id=3874
Comparison:
http://tinderbox.sh.intel.com/PRTS_UI/prtscompareresult.p
Using dispatch mask cause hangs waiting PS Done on some cases like bug #83207,
with larger screen or when scaling it.
Also mesa uses VMask instead of Dmask for 3DSTATE_PS because in some cases
they were getting incorrect derivatives for subspans.
Reference: https://bugs.freedesktop.org/show_bug.c
[snip]
On Wed, Nov 05, 2014 at 01:50:24AM -0800, Daniel Vetter wrote:
> On Tue, Nov 04, 2014 at 08:35:00AM -0800, Volkin, Bradley D wrote:
> > On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
> > > On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com
> > > wrote:
> >
This should allow us to avoid mode sets for some panel fitter config
changes.
v2:
- fixup pfit comment (Ander)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 61 +---
1 file changed, 50 insertions(+), 11 deletions(-)
diff --git a/driver
This allows us to calculate the full pipe config before we do any mode
setting work.
v2:
- clarify comments about global vs. per-crtc mode set (Ander)
- clean up unnecessary pipe_config = NULL setting (Ander)
v3:
- fix pipe_config handling (alloc in compute_config, free in set_mode) (Jesse)
This only affects the fastboot path as-is. In that case, we simply need
to make sure that we update the pipe size at the first mode set. Rather
than putting it off until we decide to flip (if indeed we do end up
flipping), update the pipe size as appropriate a bit earlier in the
set_config call.
This will allow us to consult more info before deciding whether to flip
or do a full mode set.
v2:
- don't use uninitialized or incorrect pipe masks in set_config
failure path (Ander)
v3:
- fixup for pipe_config changes in compute_config (Jesse)
Signed-off-by: Jesse Barnes
---
drivers/g
If these change (e.g. after a modeset following a fastboot), we need to
do a full mode set.
v2:
- put under pipe_config check so we don't deref a null state (Jesse)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 12 +++-
1 file changed, 11 insertions(+), 1 dele
This is useful for checking things later.
v2:
- fix hsw infoframe enabled check (Ander)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_drv.h | 4 +++
drivers/gpu/drm/i915/intel_hdmi.c | 62 +++
2 files changed, 66 insertions(+)
diff --git a/d
On Wed, Nov 05, 2014 at 02:48:48PM -0500, Sean Paul wrote:
> > + if (!crtc && crtc != set->crtc)
>
> I think this should be an ||
Hm. My idea idea was actually something along the lines of
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 4f80885de3f6..
I've applied all the other nits, replies to the more interesting bits
below.
On Wed, Nov 05, 2014 at 01:53:48PM -0500, Sean Paul wrote:
> On Sun, Nov 02, 2014 at 02:19:23PM +0100, Daniel Vetter wrote:
> > + if (new_encoder != connector_state->best_encoder) {
>
> nit: If you just returned early wh
On Wed, May 08, 2013 at 06:11:19PM +0200, Daniel Vetter wrote:
> On Wed, May 08, 2013 at 04:33:09PM +0100, Chris Wilson wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59771
> > Signed-off-by: Chris Wilson
>
> I guess we've walked past a "please stop and return" sign here a bit.
On Wed, Nov 05, 2014 at 02:46:10PM +0100, Daniel Vetter wrote:
> Well, except page_flip since that requires async commit, which isn't
> there yet.
>
> For the functions which changes planes there's a bit of trickery
> involved to keep the fb refcounting working. But otherwise fairly
> straight-forw
On Sun, Nov 02, 2014 at 02:19:23PM +0100, Daniel Vetter wrote:
> So this is finally the integration of the crtc and plane helper
> interfaces into the atomic helper functions.
>
> In the check function we now have a few steps:
>
> - First we update the output routing and figure out which crtcs need
After the previous patch RPS disabling doesn't depend any more on the
first level interrupts being disabled, so we can move it everywhere
earlier. Doing so let's us think about the uninitialization steps
afterwards independently of any asynchronous RPS events that can happen
atm. It also makes the
Atm we first enable the RPS interrupts then we clear any pending ones.
By this we could lose an interrupt arriving after we unmasked it. This
may not be a problem as the caller should handle such a race, but logic
still calls for the opposite order. Also we can delay enabling the
interrupts until a
After the previous patch the GEN8 RPS handler became very similar to the
GEN6 version, so unify the two functions.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_irq.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/g
When disabling the RPS interrupts there is a tricky dependency between
the thread disabling the interrupts, the RPS interrupt handler and the
corresponding RPS work. The RPS work can reenable the interrupts, so
there is no straightforward order in the disabling thread to (1) make
sure that any RPS
We disable the RPS interrupts for all platforms at the same spot, so
move it one level up in the callstack to simplify things.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/
The logical place for these functions is in i915_irq.c next to the rest of
PM interrupt handling functions.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_irq.c | 43
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/dr
The GEN6 and GEN8 versions differ only in the PM IIR and IER register
addresses and that on GEN8 we need to keep the
GEN8_PMINTR_REDIRECT_TO_NON_DISP PM interrupt unmasked. Abstract away
these 3 things in the GEN6 versions of the helpers and use them
everywhere.
No functional change.
Signed-off-b
The helpers to enable/disable PM IRQs for GEN6 and GEN8 are the same
except for the PM interrupt mask register, so abstract away this
register in the GEN6 versions and use these everywhere.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_irq.c | 59 +++-
While fixing [1] I noticed that we can simplify a couple of things in
the RPS enabling/disabling code. So I did that and also fixed one WARN
that we can hit with some of the pm_rpm subtests. Hopefully these
changes also makes it clearer how we avoid the race during RPS interrupt
disabling and makes
This also ensures that "make dist" works even if SWIG is not available.
BUILT_SOURCES is not required because the files are already explicit
dependencies of other rules.
v2: make sure SWIG is not invoked with the incorrect output filename
Signed-off-by: Thomas Wood
---
tools/quick_dump/Makefil
On Sun, Nov 02, 2014 at 02:19:22PM +0100, Daniel Vetter wrote:
> These two functions allow drivers to reuse their atomic plane helpers
> functions for the primary plane to implement the interfaces required
> by the crtc helpers for the legacy ->set_config callback.
>
> This is purely transitional a
On Wed, Nov 05, 2014 at 06:04:59PM +0100, Daniel Vetter wrote:
> On Wed, Nov 5, 2014 at 5:26 PM, Thierry Reding
> wrote:
> >> +struct drm_plane_state {
> >> + struct drm_crtc *crtc;
> >> + struct drm_framebuffer *fb;
> >> +
> >> + /* Signed dest location allows it to be partially off
On Wed, Nov 5, 2014 at 5:26 PM, Thierry Reding wrote:
>> +struct drm_plane_state {
>> + struct drm_crtc *crtc;
>> + struct drm_framebuffer *fb;
>> +
>> + /* Signed dest location allows it to be partially off screen */
>> + int32_t crtc_x, crtc_y;
>> + uint32_t crtc_w, crtc_h;
>
Some differences compared to Rob's patches again:
- Dropped the committed and checked booleans. Checking will be
internally enforced by always calling ->atomic_check before
->atomic_commit. And async handling needs to be solved differently
because the current scheme completely side-steps ww m
Converting a driver to the atomic interface can be a daunting
undertaking. One of the prerequisites is to have full universal planes
support.
To make that transition a bit easier this patch provides plane helpers
which use the new atomic helper callbacks just only for the plane
changes. This way t
On Wed, Nov 5, 2014 at 5:45 PM, Sean Paul wrote:
>> + /* There's no other way to figure out whether the crtc is running. */
>> + ret = drm_crtc_vblank_get(crtc[i]);
>> + if (ret == 0) {
>> + drm_crtc_wait_one_vblank(crtc[i]);
>> + drm_crtc_vblank_put(crtc[i]);
>> + }
>
> This will be good motivati
On Tue, Nov 04, 2014 at 11:00:46AM -0800, Rodrigo Vivi wrote:
> just a warn/heads-up: I had listed this one for -collector but got a
> conflict because skl latency retrieval didn't get merged yet.
I carry those in my SKL branch and will resend them as part of stage1
upstreaming, I think you can dr
On Sun, Nov 02, 2014 at 02:19:21PM +0100, Daniel Vetter wrote:
> Converting a driver to the atomic interface can be a daunting
> undertaking. One of the prerequisites is to have full universal planes
> support.
>
> To make that transition a bit easier this pathc provides plane helpers
s/pathc/patc
On Sun, Nov 02, 2014 at 02:19:18PM +0100, Daniel Vetter wrote:
[...]
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index a68e02be7e37..9847009ad451 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -224,6 +224,25 @@ struct drm_encoder;
> struct drm_pendin
On Sun, Nov 02, 2014 at 02:19:17PM +0100, Daniel Vetter wrote:
> I've forgotten to do this in:
>
> commit cb597bb3a2fbfc871cc1c703fb330d247bd21394
> Author: Daniel Vetter
> Date: Sun Jul 27 19:09:33 2014 +0200
>
> drm: trylock modest locking for fbdev panics
>
> Oops, fix this asap.
>
>
This also ensures that "make dist" works even if SWIG is not available.
BUILT_SOURCES is not required because the files are already explicit
dependencies of other rules.
Signed-off-by: Thomas Wood
---
tools/quick_dump/Makefile.am | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
dif
On Wed, Nov 05, 2014 at 02:46:31PM +0200, Jani Nikula wrote:
> Never trust (your interpretation of) the VBT. Regression from
>
> commit 6dda730e55f412a6dfb181cae6784822ba463847
> Author: Jani Nikula
> Date: Tue Jun 24 18:27:40 2014 +0300
>
> drm/i915: respect the VBT minimum backlight brig
Reviewed-by: Rodrigo Vivi
On Tue, Oct 28, 2014 at 7:20 AM, Jani Nikula wrote:
> The Baseline_ELD_Len field does not include ELD Header Block size.
>
> From High Definition Audio Specification, Revision 1.0a:
>
> The header block is a fixed size of 4 bytes. The baseline block
> is
This reverts commit 5cb13c07dae73380d8b3ddc792740487b8742938.
While the relevance for WaRsDontPollForAckOnClearingFWBits is under
investigation, revert this as regression.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684
Tested-by: Tested-by: lu hua
Cc: Chris Wilson
Cc: Ville Syrj
with
commit 5cb13c07dae73380d8b3ddc792740487b8742938
Author: Deepak S
Date: Thu Sep 18 18:51:50 2014 +0530
drm/i915/vlv: Remove check for Old Ack during forcewake
we didn't wait anymore for old ack bit clearing in basis
of workaround WaRsDontPollForAckOnClearingFWBits.
That WA says that d
From: Satheeshakrishna M
Adding new power doamins for AUX controllers
v2: Added new power domains in power_domain_str per Imre's comment
v3: Added AUX power domains to older platforms
v4: Rebase on top of POWER_DOMAIN_PLLS.
v5: Modified to address review comments from Imre
Reviewed-by: Imre
Some differences compared to Rob's patches again:
- Dropped the committed and checked booleans. Checking will be
internally enforced by always calling ->atomic_check before
->atomic_commit. And async handling needs to be solved differently
because the current scheme completely side-steps ww m
Currently there is no way to implement async flips using atomic, that
essentially requires us to be able to cancel pending requests
mid-flight.
To be able to do that (and I guess we want this since vblank synced
updates whic opportunistically cancel still pending updates seem to be
wanted) we'd ne
Well, except page_flip since that requires async commit, which isn't
there yet.
For the functions which changes planes there's a bit of trickery
involved to keep the fb refcounting working. But otherwise fairly
straight-forward atomic updates.
The property setting functions are still a bit incomp
Some differences compared to Rob's patches again:
- Dropped the committed and checked booleans. Checking will be
internally enforced by always calling ->atomic_check before
->atomic_commit. And async handling needs to be solved differently
because the current scheme completely side-steps ww m
On 11/05/2014 12:07 AM, Daniel Vetter wrote:
/**
+ * struct struct drm_atomic_state - the global state object for atomic updates
+ * @dev: parent DRM device
+ * @flags: state flags like async update
+ * @planes: pointer to array of plane pointers
+ * @plane_states: pointer to array of plane sta
Hi Dave,
Just various stuff all over from a bunch of people. Shortlog gives a beter
overview, it's really all misc drm patches.
Cheers, Daniel
The following changes since commit 1bcecfacde6269dc6cee9a098bc454222d441ff9:
drm/core: use helper to check driver features (2014-10-03 10:38:56 +0200
On Tue, Oct 14, 2014 at 01:47:36PM +0100, Chris Wilson wrote:
> Previously, this was restricted to only operate on bound objects - to
> make pointer access through the GTT to the object coherent with writes
> to and from the GPU. A second usecase is drm_intel_bo_wait_rendering()
> which at present
On Thu, Oct 23, 2014 at 05:55:47PM +0100, Chris Wilson wrote:
> From: Akash Goel
>
> This patch provides support to create write-combining virtual mappings of
> GEM object. It intends to provide the same funtionality of 'mmap_gtt'
> interface without the constraints and contention of a limited ap
On 11/5/2014 3:43 PM, Mika Kuoppala wrote:
Ville Syrjälä writes:
On Wed, Nov 05, 2014 at 10:18:46AM +0200, Mika Kuoppala wrote:
Don't rush into getting new fw until the clearing
of old one has been acked.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684
Tested-by: lu hua
Signed
Never trust (your interpretation of) the VBT. Regression from
commit 6dda730e55f412a6dfb181cae6784822ba463847
Author: Jani Nikula
Date: Tue Jun 24 18:27:40 2014 +0300
drm/i915: respect the VBT minimum backlight brightness
causing div by zero if VBT minimum brightness equals maximum bright
On Wed, Nov 05, 2014 at 12:13:40PM +0200, Mika Kuoppala wrote:
> Ville Syrjälä writes:
>
> > On Wed, Nov 05, 2014 at 10:18:46AM +0200, Mika Kuoppala wrote:
> >> Don't rush into getting new fw until the clearing
> >> of old one has been acked.
> >>
> >> Bugzilla: https://bugs.freedesktop.org/show
On Tue, Nov 04, 2014 at 02:20:28PM -0800, armin.c.re...@intel.com wrote:
> From: Armin Reese
>
> This commit synchronizes the intel_renderstate_genx.c files in
> the kernel source tree with those produced by the 'make states'
> command invoking null_state_gen. Replaced manually-added
> copyright
On Tue, Nov 04, 2014 at 02:00:43PM -0800, bradley.d.vol...@intel.com wrote:
> +static bool uses_cmd_parser(int fd, int gen)
> +{
> + int parser_version = 0;
> + drm_i915_getparam_t gp;
> + int rc;
> +
> + gp.param = I915_PARAM_CMD_PARSER_VERSION;
> + gp.value = &parser_version;
On Tue, Nov 04, 2014 at 09:19:36AM -0800, armin.c.re...@intel.com wrote:
> From: Armin Reese
>
> The new 'i915_context_dump' file generates a hex dump of the
> entire logical context DRM object. It is useful for
> validating the contents of the default context set up by
> the golden state batch
On Wed, Nov 05, 2014 at 12:41:32PM +0200, Jani Nikula wrote:
>
> Daniel, Rodrigo accidentally replied to just me with his r-b.
Ok, pulled in the remaining i915 patches, thanks. But I still lack the
review on the second drm core eld patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corpora
On Wed, Nov 05, 2014 at 02:23:07PM +0200, Ander Conselvan de Oliveira wrote:
> On 11/05/2014 01:23 PM, Chris Wilson wrote:
> >On Wed, Nov 05, 2014 at 01:03:00PM +0200, Ander Conselvan de Oliveira wrote:
> >>This simplifies the code quite a bit compared to iterating over all
> >>rings during the rin
On 11/05/2014 01:23 PM, Chris Wilson wrote:
On Wed, Nov 05, 2014 at 01:03:00PM +0200, Ander Conselvan de Oliveira wrote:
This simplifies the code quite a bit compared to iterating over all
rings during the ring interrupt.
Also, it allows us to drop the mmio_flip spinlock, since the mmio_flip
st
On 04/11/14 22:09, Daniel Vetter wrote:
> Currently there is no way to implement async flips using atomic, that
> essentially requires us to be able to cancel pending requests
> mid-flight.
>
> To be able to do that (and I guess we want this since vblank synced
> updates whic opportunistically can
On Tue, Nov 04, 2014 at 05:06:37PM +, Damien Lespiau wrote:
> We might as well try to push a few more patches while waiting for the next
> batch of reviews. Here's the WM code and 2 bonus patches around forcewake and
> rc6.
>
> The attentive reader will notice the lack of r-b tag for:
> "drm
On Wed, Nov 05, 2014 at 01:03:00PM +0200, Ander Conselvan de Oliveira wrote:
> This simplifies the code quite a bit compared to iterating over all
> rings during the ring interrupt.
>
> Also, it allows us to drop the mmio_flip spinlock, since the mmio_flip
> struct is only accessed in two places.
On Thu, Oct 30, 2014 at 5:18 PM, Rodrigo Vivi wrote:
> Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
> So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
>
> MOCS can still be used though. But if userspace is trusting PTE for
> cache selection the
This simplifies the code quite a bit compared to iterating over all
rings during the ring interrupt.
Also, it allows us to drop the mmio_flip spinlock, since the mmio_flip
struct is only accessed in two places. The first is when the flip is
queued and the other when the mmio writes are done. Since
Daniel, Rodrigo accidentally replied to just me with his r-b.
BR,
Jani.
On Wed, 05 Nov 2014, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi
>
> On Tue, Nov 4, 2014 at 12:31 AM, Jani Nikula wrote:
>> Similar to the hsw/bdw enable sequence rewrite.
>>
>> v3: replace vblank wait with a comment
On Tue, Nov 04, 2014 at 05:06:52PM +, Damien Lespiau wrote:
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ecba620..9ec1ab7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10509,6 +1050
On Wed, Nov 05, 2014 at 11:25:51AM +0100, Daniel Vetter wrote:
> On Tue, Nov 04, 2014 at 05:06:38PM +, Damien Lespiau wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 7a69eba..761c884 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > ++
On Tue, Nov 04, 2014 at 05:06:38PM +, Damien Lespiau wrote:
> From: Pradeep Bhat
>
> This patch reads the memory latency values for all the 8 levels for
> SKL. These values are needed for the Watermark computation.
>
> v2: Incorporated the review comments from Damien on register
> indent
On Wed, Nov 05, 2014 at 10:50:24AM +0100, Daniel Vetter wrote:
> On Tue, Nov 04, 2014 at 08:35:00AM -0800, Volkin, Bradley D wrote:
> > On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
> > > On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com
> > > wrote:
> > > > +
Ville Syrjälä writes:
> On Wed, Nov 05, 2014 at 10:18:46AM +0200, Mika Kuoppala wrote:
>> Don't rush into getting new fw until the clearing
>> of old one has been acked.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684
>> Tested-by: lu hua
>> Signed-off-by: Mika Kuoppala
>
>
On 11/04/2014 06:44 PM, Chris Wilson wrote:
On Tue, Nov 04, 2014 at 03:14:04PM +, Tvrtko Ursulin wrote:
On 11/04/2014 02:31 PM, Chris Wilson wrote:
Running __mmu_notifier_register() is surprisingly expensive, so let's
not do that unless we have to.
Affects some program startup or what?
On Wed, Nov 05, 2014 at 09:50:47AM +, Chris Wilson wrote:
> Hmm, for pageflips it is not that useful unless you give me a method to
> pre-bind it elsewhere. Currently, I force a pagefault on objects that
> are allocated for use as scanout so that we do not incur the stall when
> flipping. Even
On Wed, Nov 05, 2014 at 08:35:01AM +, Chris Wilson wrote:
> On Tue, Nov 04, 2014 at 03:52:22PM +0100, Daniel Vetter wrote:
> > There's quite a few bug reports with error states where the error
> > reasons makes just about no sense at all. Like dying on tlbs for a
> > display plane that's not ev
On 11/4/2014 7:23 PM, Rodrigo Vivi wrote:
These patches got listed to -collector but got a huge conflict. If it
is still relevant please rebase it.
Also my bikeshed is to findo better names to help on differentiate
them at least.
On Wed, Sep 24, 2014 at 5:02 AM, Michel Thierry
wrote:
Followin
On 04/11/2014 19:23, Rodrigo Vivi wrote:
These patches got listed to -collector but got a huge conflict. If it
is still relevant please rebase it.
This patch is currently not relevant, rebased version is already sent to
the list for review.
https://patchwork.kernel.org/patch/5178771/
regards
On Tue, Nov 04, 2014 at 08:46:16AM -0800, Volkin, Bradley D wrote:
> On Tue, Nov 04, 2014 at 02:30:14AM -0800, Daniel Vetter wrote:
> > On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
> > > + flags |= I915_DISPATCH_SECURE;
> >
> > I've forgotten one: You
On Wed, Nov 05, 2014 at 10:19:47AM +0100, Daniel Vetter wrote:
> On Tue, Nov 04, 2014 at 01:01:09PM +, Chris Wilson wrote:
> > On Tue, Nov 04, 2014 at 01:44:47PM +0100, Daniel Vetter wrote:
> > > On Wed, Oct 08, 2014 at 08:13:33AM +0100, Chris Wilson wrote:
> > > > On Tue, Oct 07, 2014 at 06:10
On Tue, Nov 04, 2014 at 08:35:00AM -0800, Volkin, Bradley D wrote:
> On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
> > On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
> > Hm, no in-line clflush and cached cpu mmaps. How slow is this on vlv?
>
> No syst
On Tue, Nov 04, 2014 at 06:42:16PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 04, 2014 at 01:40:05PM +0100, Daniel Vetter wrote:
> > On Tue, Nov 4, 2014 at 1:21 PM, Ville Syrjälä
> > wrote:
> > >> > drm/i915: Refactor vlv_display_irq_uninstall()
> > >>
> > >> Except this, I think consens is that
On 11/5/2014 2:23 PM, Ville Syrjälä wrote:
On Wed, Nov 05, 2014 at 10:18:46AM +0200, Mika Kuoppala wrote:
Don't rush into getting new fw until the clearing
of old one has been acked.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684
Tested-by: lu hua
Signed-off-by: Mika Kuoppala
Hi Rodrigo,
This one and
[PATCH 2/2] drm/edid: fix Baseline_ELD_Len field in drm_edid_to_eld()
still seem to be missing your r-b I think. Merged 2 more from this series.
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
On Tue, Nov 04, 2014 at 01:01:09PM +, Chris Wilson wrote:
> On Tue, Nov 04, 2014 at 01:44:47PM +0100, Daniel Vetter wrote:
> > On Wed, Oct 08, 2014 at 08:13:33AM +0100, Chris Wilson wrote:
> > > On Tue, Oct 07, 2014 at 06:10:56PM +0100, Michel Thierry wrote:
> > > > This is based on the first 5
On Tue, Nov 04, 2014 at 04:12:47PM +, Damien Lespiau wrote:
> On Mon, Sep 22, 2014 at 03:25:30PM -0300, Paulo Zanoni wrote:
> > Also, I guess that a patch with 3 signed-off-by stamps shouldn't
> > really need an additional reviewed-by stamp, right? So maybe this
> > should just be merged.
The
On Tue, Nov 04, 2014 at 10:50:55AM -0200, Paulo Zanoni wrote:
> 2014-11-03 8:29 GMT-02:00 Daniel Vetter :
> >> If we're also interested on DDI platforms, we need to check for
> >> INTEL_OUTPUT_UNKNOWN here too. I guess Daniel could add this while
> >> applying the patch...
> >
> > Adding UNKNOWN he
On Wed, Nov 05, 2014 at 10:18:46AM +0200, Mika Kuoppala wrote:
> Don't rush into getting new fw until the clearing
> of old one has been acked.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684
> Tested-by: lu hua
> Signed-off-by: Mika Kuoppala
This is just a revert of
commit 5
On Tue, Nov 04, 2014 at 03:52:22PM +0100, Daniel Vetter wrote:
> There's quite a few bug reports with error states where the error
> reasons makes just about no sense at all. Like dying on tlbs for a
> display plane that's not even there. Also users don't really report a
> lot of bad side effects g
On Wed, Nov 05, 2014 at 10:18:46AM +0200, Mika Kuoppala wrote:
> Don't rush into getting new fw until the clearing
> of old one has been acked.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684
> Tested-by: lu hua
> Signed-off-by: Mika Kuoppala
vlv is backwards wrt to our design
Don't rush into getting new fw until the clearing
of old one has been acked.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684
Tested-by: lu hua
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/g
97 matches
Mail list logo
