This exercises both the wc mmappings and the extended get_tiling ioctl.
Userspace cannot handle bit17 swizzling through wc mmaps (because bit17
requires swizzling based on the actual physical address of the page -
which is unknown to userspace) and so we need an extended get_tiling
ioctl to report
On Mon, Nov 03, 2014 at 12:41:37PM +0100, Daniel Vetter wrote:
> On Thu, Oct 30, 2014 at 10:40:53AM +, Chris Wilson wrote:
> > On Mon, Oct 27, 2014 at 10:08:29AM +0100, Daniel Vetter wrote:
> > > On Fri, Oct 24, 2014 at 04:16:14PM +0100, Chris Wilson wrote:
> > > > On Fri, Oct 24, 2014 at 04:39
On 11/03/2014 03:56 PM, Daniel Vetter wrote:
On Mon, Nov 03, 2014 at 02:51:27PM +0100, Daniel Vetter wrote:
On Wed, Oct 29, 2014 at 11:32:33AM +0200, Ander Conselvan de Oliveira wrote:
It is possible for a mode set to fail if there aren't shared DPLLS that
match the new configuration requiremen
On Monday 03 November 2014 01:58 PM, Daniel Vetter wrote:
On Mon, Nov 3, 2014 at 9:25 AM, Thierry Reding wrote:
The idea is that you'd grab the DPCD field anyway since it's needed all
over the place. We have a pile of helpers already that take exactly this
block and decode parts of it. So I th
On Sun, Nov 02, 2014 at 02:19:19PM +0100, Daniel Vetter wrote:
...
> +/**
> + * drm_atomic_get_plane_state - get plane state
> + * @state: global atomic state object
> + * @plane: plane to get state object for
> + *
> + * This functions returns the plane state for the given plane, allocating it
>
On Mon, Nov 03, 2014 at 11:19:40AM -0800, Volkin, Bradley D wrote:
> From: Brad Volkin
>
> This is v3 of the series I sent here:
> http://lists.freedesktop.org/archives/intel-gfx/2014-July/048705.html
>
> Most of the previous commentary still applies. We've fixed the secure
> dispatch regression
On Mon, Nov 03, 2014 at 05:54:16PM +0100, Daniel Vetter wrote:
> On Wed, Oct 29, 2014 at 09:52:52AM +, Thomas Daniel wrote:
> > From: Oscar Mateo
> >
> > Up until now, we have pinned every logical ring context backing object
> > during creation, and left it pinned until destruction. This made
On Mon, Nov 03, 2014 at 01:29:04PM +, Dave Gordon wrote:
> Fixes to both the LRC and the legacy ringbuffer code to correctly
> calculate and update the available space in a ring.
>
> The logical ring code was updating the software ring 'head' value
> by reading the hardware 'HEAD' register. In
On Mon, Nov 03, 2014 at 03:31:09PM +0100, Daniel Vetter wrote:
> On Fri, Oct 31, 2014 at 05:38:31PM +0200, Mika Kuoppala wrote:
> > to move the interface to the ppgtt era.
> >
> > Signed-off-by: Mika Kuoppala
> > ---
> > drivers/gpu/drm/i915/i915_gpu_error.c | 49
> > +++
On Mon, Nov 03, 2014 at 04:17:57PM +0100, Daniel Vetter wrote:
> Then we could just look at the vma's drm_mm node instead of jumping
> through the helpers here. Which gets us one inch closer to tracking
> mappable in the ggtt vma, without increasing the diff ;-)
>
> > + bool mappable, f
On Mon, Nov 03, 2014 at 04:20:58PM +0100, Daniel Vetter wrote:
> On Fri, Oct 31, 2014 at 01:53:53PM +, Chris Wilson wrote:
> > Always require PIN_GLOBAL when we want a mappable offset (PIN_MAPPABLE).
> > This causes the pin to fixup the global binding in cases were the vma
> > was already bound
On Mon, Nov 03, 2014 at 04:17:57PM +0100, Daniel Vetter wrote:
> On Fri, Oct 31, 2014 at 01:53:52PM +, Chris Wilson wrote:
> > @@ -4091,6 +4078,7 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
> > }
> > }
> >
> > + bound = vma ? vma->bound : 0;
> > if (vma == NU
On Mon, Nov 03, 2014 at 01:54:00PM +0100, Daniel Vetter wrote:
> On Fri, Oct 31, 2014 at 04:07:35PM +, Chris Wilson wrote:
> > On Fri, Oct 31, 2014 at 02:52:40PM +, Damien Lespiau wrote:
> > > On Fri, Oct 31, 2014 at 12:00:26PM +, john.c.harri...@intel.com wrote:
> > > > From: John Harr
On Mon, Nov 03, 2014 at 05:05:55PM +0100, Daniel Vetter wrote:
> On Thu, Oct 30, 2014 at 04:39:37PM +, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > It will be used by other call sites shortly.
> >
> > Signed-off-by: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/i915_dma.c
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=251/251->248/251
PNV: pass/total=328/328->325
From: Brad Volkin
The size of the batch buffer passed to the kernel is significantly
larger than the size of the batch buffer passed to the function. A
proposed optimization as part of the batch copy kernel series is to
use batch_len for the copy and parse operations, which leads to a
false "batc
From: Brad Volkin
The command parser's batch_len optimization causes the parser to
reject this batch as not having an MI_BATCH_BUFFER_END because
the length was not set correctly.
Signed-off-by: Brad Volkin
---
tests/gem_madvise.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/gem_m
On Mon, Nov 3, 2014 at 8:13 PM, Paulo Zanoni wrote:
> 2014-11-03 16:53 GMT-02:00 Daniel Vetter :
>> On Mon, Nov 3, 2014 at 7:37 PM, Paulo Zanoni wrote:
>>> Besides this, my only worry is what is going to happen if we disable
>>> the CRTC or plane (or even suspend - S3 or runtime - or something li
From: Brad Volkin
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser and dispatches the copied
(shadow) batch to the hardware.
After this patch, the parser is in 'enabling' mode.
Note that performance takes a hit from the copy in some cases
a
From: Brad Volkin
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future u
From: Brad Volkin
This is v3 of the series I sent here:
http://lists.freedesktop.org/archives/intel-gfx/2014-July/048705.html
Most of the previous commentary still applies. We've fixed the secure
dispatch regression though, so the series now puts the parser into
enabling mode in patch 2.
There
From: Brad Volkin
Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential hole.
With the parser now
From: Brad Volkin
It provides some useful information about the buffers in
the global command parser batch pool.
v2: rebase on global pool instead of per-ring pools
v3: rebase
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +
1 fil
From: Brad Volkin
To better account for the potentially large memory consumption
of the batch pool.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
2014-11-03 16:53 GMT-02:00 Daniel Vetter :
> On Mon, Nov 3, 2014 at 7:37 PM, Paulo Zanoni wrote:
>> Besides this, my only worry is what is going to happen if we disable
>> the CRTC or plane (or even suspend - S3 or runtime - or something like
>> that) after we schedule the work, but before the wor
On Mon, Nov 3, 2014 at 7:37 PM, Paulo Zanoni wrote:
> Besides this, my only worry is what is going to happen if we disable
> the CRTC or plane (or even suspend - S3 or runtime - or something like
> that) after we schedule the work, but before the work actually
> happens. Isn't it possible to end u
2014-10-28 11:10 GMT-02:00 Ander Conselvan de Oliveira
:
> Currently we program just DPSCNTR and DSPSTRIDE directly from the ring
> interrupt handler, which is fine since the hardware guarantees that
> those are update atomically. When we have atomic page flips we'll want
> to be able to update als
On Mon, Nov 03, 2014 at 03:26:36PM -0200, Paulo Zanoni wrote:
> 2014-11-03 10:33 GMT-02:00 Daniel Vetter :
> > On Tue, Oct 28, 2014 at 03:10:12PM +0200, Ander Conselvan de Oliveira wrote:
> >> Signed-off-by: Ander Conselvan de Oliveira
> >>
> >> ---
> >> drivers/gpu/drm/i915/intel_sprite.c | 25
From: Zhe Wang
For MMIO registers which are shadowed, force wake is not needed to
write to these registers.
v2: Rebase on top of nightly (Damien)
v3: Rebase on top of "Gen9 multiple-engine forcewake" changes
v4: (Mika, Bob, done by Damien)
- Reorder the shadowed registers by popularity
Signed
On Mon, Nov 3, 2014 at 6:20 PM, Tvrtko Ursulin
wrote:
>> I'm not a fan of preemptive generalization - it tends to be the wrong one
>> and hurt doubly in the future since you have to remove the wrong one first
>> before you can add the right stuff.
>
>
> In general :), as always it is the question
On Mon, Nov 3, 2014 at 6:20 PM, Tvrtko Ursulin
wrote:
> I did not like your idea, well I did not think it is feasible - as in easily
> doable, of stealing the DMA addresses since the SG tables between view don't
> have a 1:1 relationship in number of chunk/pages.
Ok, so sg table coalescing is get
2014-11-03 10:33 GMT-02:00 Daniel Vetter :
> On Tue, Oct 28, 2014 at 03:10:12PM +0200, Ander Conselvan de Oliveira wrote:
>> Signed-off-by: Ander Conselvan de Oliveira
>>
>> ---
>> drivers/gpu/drm/i915/intel_sprite.c | 25 +
>> 1 file changed, 25 insertions(+)
>>
>> diff
>From: Daniel Vetter
>
>On Thu, Oct 30, 2014 at 05:35:55AM -0700, Rodrigo Vivi wrote:
>> It was identified that in some cases when moving cursor Hardware can do
>> mistake with idle_frame count. So Spec is being updated to use
>> 2 as minimum idle_frames.
>>
>> Reference:
>https://hsdhsw.intel.com
On 31/10/14 14:52, Damien Lespiau wrote:
> On Fri, Oct 31, 2014 at 12:00:26PM +, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> If a ring failed to initialise for any reason then the error path would try
>> to
>> clean up all rings including those that had not yet been allocate
On Mon, Nov 03, 2014 at 05:00:35PM +, Daniel, Thomas wrote:
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Monday, November 03, 2014 4:54 PM
> > To: Daniel, Thomas
> > Cc: intel-gfx@lists.freedesktop.org; shuang...
From: Zhe Wang
Enable multi-engine forcewake for Gen9.
v2: (Damien)
- Rebase on top of nightly
- Move the register range definitions to intel_uncore.c
- Whitespace fixes
v3: (Addressing Mika's comment, done by Damien)
- Use REG_RANGE() (introduced after the patch was written)
- Add a SKL_NEEDS_
On Thu, Oct 30, 2014 at 06:55:36PM +, John Harrison wrote:
> Oops, forgot to update the text for the zero patch. This is no longer 'work
> in progress' and is now intended for proper review! The description should
> read as follows:
>
> There is a general feeling that it is better to move away
On Thu, Oct 30, 2014 at 06:40:53PM +, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> An earlier commit (c8725f3dc0911d4354315a65150aecd8b7d0d74a: Do not call
> retire_requests from wait_for_rendering) removed the use of the ring parameter
> within wait_rendering__tail() but did no
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Monday, November 03, 2014 4:54 PM
> To: Daniel, Thomas
> Cc: intel-gfx@lists.freedesktop.org; shuang...@linux.intel.com
> Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/bdw: Pin th
On Wed, Oct 29, 2014 at 09:52:52AM +, Thomas Daniel wrote:
> From: Oscar Mateo
>
> Up until now, we have pinned every logical ring context backing object
> during creation, and left it pinned until destruction. This made my life
> easier, but it's a harmful thing to do, because we cause fragm
On Mon, Nov 03, 2014 at 04:18:30PM +, Tvrtko Ursulin wrote:
>
> On 11/03/2014 04:02 PM, Daniel Vetter wrote:
> >On Thu, Oct 30, 2014 at 04:39:37PM +, Tvrtko Ursulin wrote:
> >
> >Just a sideline comment here for now ;-)
> >
> >>+/* intel_dma.c */
> >>+int i915_st_set_pages(struct sg_table
On Mon, Nov 03, 2014 at 04:34:29PM +, Tvrtko Ursulin wrote:
>
> On 11/03/2014 03:58 PM, Daniel Vetter wrote:
> >On Thu, Oct 30, 2014 at 04:39:36PM +, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>Things like reliable GGTT mappings and mirrored 3d display will need to be
> >>to m
On Mon, Nov 03, 2014 at 03:42:06PM +, Thomas Wood wrote:
> On 3 November 2014 15:02, Daniel Vetter wrote:
> > On Mon, Nov 03, 2014 at 11:31:02AM +, Thomas Wood wrote:
> >> Signed-off-by: Thomas Wood
> >> ---
> >> lib/tests/igt_command_line.sh | 8
> >> 1 file changed, 4 insertio
On Thu, Oct 30, 2014 at 10:36:23PM +0200, Imre Deak wrote:
> On Thu, 2014-10-30 at 15:59 -0200, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > With this patch, the RPS sequence for runtime suspend/resume is
> > exactly like the sequence for S3 suspend/resume:
> > - flush_delayed_work(&dev_pr
On Thu, Oct 30, 2014 at 03:52:45PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Fix the message, not the fault :)
>
> This is what I see:
> [ 282.108597] [drm:i915_check_and_clear_faults] Unexpected fault
> [ 282.108597]Addr: 0x\n Address space: PPGTT
> [ 282.10859
On Thu, Oct 30, 2014 at 07:42:49PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> After enabling the pipe-a power well on CHV I noticed that hpd and interrupts
> didn't work too well anymore. The reason is the same as on VLV; the power well
> kills that stuff. So we need to
On Thu, Oct 30, 2014 at 06:41:11PM -0200, Paulo Zanoni wrote:
> 2014-10-30 15:43 GMT-02:00 :
> >
> > gen8_gt_irq_postinstall(dev_priv);
> >
> > @@ -3620,7 +3594,6 @@ static void valleyview_irq_uninstall(struct
> > drm_device *dev)
> > static void cherryview_irq_uninstall(struct drm_devic
On 11/03/2014 03:58 PM, Daniel Vetter wrote:
On Thu, Oct 30, 2014 at 04:39:36PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Things like reliable GGTT mappings and mirrored 3d display will need to be
to map the same object twice into the GGTT.
Add a ggtt_view field per VMA and select th
On Fri, Oct 31, 2014 at 11:40:36AM +0200, Ville Syrjälä wrote:
> On Thu, Oct 30, 2014 at 06:12:51PM -0200, Paulo Zanoni wrote:
> > While trying to check for the correctness of the lines above, I
> > noticed that in __i915_enable_pipestat(), if the enable mask is
> > already what we want, we won't c
On Fri, Oct 31, 2014 at 11:48:01AM +0200, Ville Syrjälä wrote:
> On Fri, Oct 31, 2014 at 11:35:52AM +0200, Ville Syrjälä wrote:
> > On Thu, Oct 30, 2014 at 05:51:49PM -0200, Paulo Zanoni wrote:
> > > 2014-10-30 15:42 GMT-02:00 :
> > > > From: Ville Syrjälä
> > > >
> > > > Looks like we forgot to
On 11/03/2014 04:02 PM, Daniel Vetter wrote:
On Thu, Oct 30, 2014 at 04:39:37PM +, Tvrtko Ursulin wrote:
Just a sideline comment here for now ;-)
+/* intel_dma.c */
+int i915_st_set_pages(struct sg_table **st, struct page **pvec, int num_pages);
Comments all over should tell you that i9
Motivated by the per-plane locking I've gone through all the get*
ioctls and reduced the locking to the bare minimum required.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_crtc.c | 43 +--
1 file changed, 17 insertions(+), 26 deletions(-)
diff --g
On Thu, Oct 30, 2014 at 04:39:38PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> It will help future code if this function knows something about of the context
> of the display setup object is being pinned for.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Daniel Vetter
Rebased and applie
On Mon, Nov 03, 2014 at 04:05:03PM +, Daniel, Thomas wrote:
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Monday, November 03, 2014 3:33 PM
> > To: Daniel, Thomas
> > Cc: intel-gfx@lists.freedesktop.org; shuang...
On 30/10/14 19:26, Ville Syrjälä wrote:
> On Thu, Oct 30, 2014 at 10:32:38AM -0700, Kenneth Graunke wrote:
>> On Thursday, October 30, 2014 01:01:30 PM Ville Syrjälä wrote:
>>> On Thu, Oct 30, 2014 at 02:32:40AM -0700, Kenneth Graunke wrote:
On Thursday, October 30, 2014 11:00:51 AM Ville Syrj
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Monday, November 03, 2014 3:33 PM
> To: Daniel, Thomas
> Cc: intel-gfx@lists.freedesktop.org; shuang...@linux.intel.com
> Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/bdw: Clean
On Thu, Oct 30, 2014 at 04:39:37PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> It will be used by other call sites shortly.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_dma.c | 38 +
> drivers/gpu/drm/i915/i915_gem_userptr.
On Thu, Oct 30, 2014 at 04:39:37PM +, Tvrtko Ursulin wrote:
Just a sideline comment here for now ;-)
> +/* intel_dma.c */
> +int i915_st_set_pages(struct sg_table **st, struct page **pvec, int
> num_pages);
Comments all over should tell you that i915_dma.c is super legacy
territory and real
On Thu, Oct 30, 2014 at 04:39:36PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Things like reliable GGTT mappings and mirrored 3d display will need to be
> to map the same object twice into the GGTT.
>
> Add a ggtt_view field per VMA and select the page view based on the type
> of th
On Wed, Oct 29, 2014 at 09:52:51AM +, Thomas Daniel wrote:
> Write HWS_PGA address even in execlists mode as the global hardware status
> page is still required. This address was previously uninitialized and
> HWSP writes would clobber whatever buffer happened to reside at GGTT
> address 0.
>
On 3 November 2014 15:02, Daniel Vetter wrote:
> On Mon, Nov 03, 2014 at 11:31:02AM +, Thomas Wood wrote:
>> Signed-off-by: Thomas Wood
>> ---
>> lib/tests/igt_command_line.sh | 8
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/lib/tests/igt_command_line.sh b/
On 3 November 2014 12:26, Daniel Vetter wrote:
> On Tue, Oct 28, 2014 at 03:10:25PM +, Damien Lespiau wrote:
>> On Tue, Oct 28, 2014 at 03:03:53PM +, Thomas Wood wrote:
>> > +extern const char* __igt_test_description __attribute__((weak));
>> > +#define IGT_TEST_DESCRIPTION(a) const char*
On Wed, Oct 29, 2014 at 09:52:50AM +, Thomas Daniel wrote:
> No longer create a work item to clean each execlist queue item.
> Instead, move retired execlist requests to a queue and clean up the
> items during retire_requests.
>
> v2: Fix legacy ring path broken during overzealous cleanup
>
>
On Sat, Nov 01, 2014 at 06:08:00PM +0100, Christian Kastner wrote:
> Hi,
>
> I have a Macbook Air (2013) (6,2) which until recently was working
> flawlessly with Debian unstable, which I use almost exclusively on that
> machine. I did keep the OSX installation, mainly because it's the only
> way t
On 03/11/14 14:53, Daniel Vetter wrote:
> On Mon, Nov 03, 2014 at 02:45:28PM +, Daniel Thompson wrote:
>>> index 70bd67cf86e3..bd38df3cbe55 100644
>>> --- a/drivers/gpu/drm/drm_atomic_helper.c
>>> +++ b/drivers/gpu/drm/drm_atomic_helper.c
>>> @@ -1429,7 +1429,7 @@ EXPORT_SYMBOL(drm_atomic_helpe
On 02/11/14 13:19, Daniel Vetter wrote:> The atomic users and helpers
assume that there is always a obj->state
> structure around. Which means drivers need to somehow create that at
> driver load time. Also it should obviously reset hardware state, so
> needs to be reset upon resume.
>
> Finally th
On Sat, Nov 01, 2014 at 05:05:57AM +, Damien Lespiau wrote:
> The function was removed in:
>
> commit 037bde19a43e299d30f0490bba9be32ab355975c
> Author: Chris Wilson
> Date: Thu Mar 27 08:24:19 2014 +
>
> Revert "drm/i915: Disable/Enable PM Intrrupts based on the current
>
To align with the ilk WM code and because it makes sense to test against
the upper bounds as soon as possible on variables that are bigger than
the number of bits in the register, let's move the maximum checks from
skl_compute_wm_results() to skl_compute_plane_wm().
v2: Leave the result values to
On Fri, Oct 31, 2014 at 01:53:53PM +, Chris Wilson wrote:
> Always require PIN_GLOBAL when we want a mappable offset (PIN_MAPPABLE).
> This causes the pin to fixup the global binding in cases were the vma
> was already bound (and due to the proceeding bug, we considered it to be
> already mappa
On Fri, Oct 31, 2014 at 01:53:52PM +, Chris Wilson wrote:
> @@ -4091,6 +4078,7 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
> }
> }
>
> + bound = vma ? vma->bound : 0;
> if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
> vma = i91
On Mon, Nov 03, 2014 at 03:06:07PM +, Daniel Thompson wrote:
> > kfree is a nop when the argument is NULL, which is a crucial property of
> > this - memset would oops on driver load.
>
> Oops. Missed that (I think I misread who as assuming there was always
> obj->state in the patch header).
>
On Wed, Oct 29, 2014 at 05:22:39PM +, Damien Lespiau wrote:
> Skylake changed a few things here and there in the plane registers and we
> weren't correctly reading out the primary plane state when trying to re-use
> the
> BIOS stolen allocated fb (especially the stride was all wrong). Of cours
On Mon, Nov 03, 2014 at 11:31:02AM +, Thomas Wood wrote:
> Signed-off-by: Thomas Wood
> ---
> lib/tests/igt_command_line.sh | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/lib/tests/igt_command_line.sh b/lib/tests/igt_command_line.sh
> index 7e6ca67..5cf2584
On Mon, Nov 03, 2014 at 02:45:28PM +, Daniel Thompson wrote:
> > index 70bd67cf86e3..bd38df3cbe55 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -1429,7 +1429,7 @@ EXPORT_SYMBOL(drm_atomic_helper_set_config);
> > /**
> > * drm_atomic
On Mon, Nov 03, 2014 at 03:49:32PM +0200, Jani Nikula wrote:
> On Mon, 03 Nov 2014, Daniel Vetter wrote:
> > Checking for lvds/edp is wrong (since we also support dsi panels now)
> > and not terribly useless. If we want to be more intelligent about all
>
> "wrong ... and not terribly useless"? us
On Tue, Nov 04, 2014 at 02:20:38PM +0530, Gagandeep S Arora wrote:
> +/*
> + * The macros and structures inside the conditional statement
> + * #if (ANDROID_HAS_CAIRO == 1) are defined in lib/igt_kms.c
> + * when the flag ANDROID_HAS_CAIRO is 1.
> + */
> +#if (ANDROID_HAS_CAIRO == 0)
> +struct type
Hi Dave,
drm-intel-next-2014-10-24:
- suspend/resume/freeze/thaw unification from Imre
- wa list improvements from Mika&Arun
- display pll precomputation from Ander Conselvan prep work
- more kerneldoc for the interrupt code
- 180 rotation for cursors (Ville&Sonika)
- ULT/ULX feature check macros
It's really part of the "push all new_* state into current state
pointers" done in that function. So let's move it there to make this
clear.
Also, with the conversion done the num_shared_dpll check the function
does in it's loop is enough, so we can drop the check for the dpll
compute callback, to
On Fri, Oct 31, 2014 at 05:38:31PM +0200, Mika Kuoppala wrote:
> to move the interface to the ppgtt era.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 49
> +++
> 1 file changed, 27 insertions(+), 22 deletions(-)
>
> diff --git
Ville suggested that we should use the same semantics as C arrays to
reduce the number of those pesky +1/-1 in the allocation code.
This patch leaves the debugfs file as is, showing the internal DDB
allocation structure, not the values written in the registers.
v2: Remove the test on ->end in skl
On Wed, Oct 29, 2014 at 03:20:47PM +, Thomas Wood wrote:
> @@ -380,6 +382,7 @@ void igt_exit(void) __attribute__((noreturn));
> */
> #define igt_require_f(expr, f...) do { \
> if (!(expr)) igt_skip_check(#expr , f); \
> + else igt_debug("Test requirement passed: "#expr"\n"); \
> }
On Wed, Oct 29, 2014 at 12:03:45PM +, Damien Lespiau wrote:
> Chris removed the code using it in:
>
> commit be2d599b5da3936ca92e0187ff50b34b6b8ff997
> Author: Chris Wilson
> Date: Wed Sep 10 19:52:18 2014 +0100
>
> drm/i915: Remove dead code, i915_gem_verify_gtt
>
> Signed-of
On Wed, Oct 29, 2014 at 01:48:15PM +0200, Jani Nikula wrote:
> On Wed, 29 Oct 2014, Damien Lespiau wrote:
> > As Paulo said when introducing the enum, having more types is really
> > good to document what should go where (int foo(int, int, bool, bool).
> >
> > Cc: Paulo Zanoni
> > Signed-off-by:
On Wed, Oct 29, 2014 at 11:32:29AM +0200, Ander Conselvan de Oliveira wrote:
> Version 2 of the series with the comments I got so far resolved.
>
> Ander Conselvan de Oliveira (9):
> drm/i915: Make *_crtc_mode_set work on new_config
> drm/i915: Convert shared dpll reference count to a crtc mas
On Mon, Nov 03, 2014 at 02:51:27PM +0100, Daniel Vetter wrote:
> On Wed, Oct 29, 2014 at 11:32:33AM +0200, Ander Conselvan de Oliveira wrote:
> > It is possible for a mode set to fail if there aren't shared DPLLS that
> > match the new configuration requirement or other errors in clock
> > computat
On Wed, Oct 29, 2014 at 11:32:33AM +0200, Ander Conselvan de Oliveira wrote:
> It is possible for a mode set to fail if there aren't shared DPLLS that
> match the new configuration requirement or other errors in clock
> computation. If that step is executed after disabling crtcs, in the
> failure c
On Mon, 03 Nov 2014, Daniel Vetter wrote:
> Checking for lvds/edp is wrong (since we also support dsi panels now)
> and not terribly useless. If we want to be more intelligent about all
"wrong ... and not terribly useless"? useful?
BR,
Jani.
> this then we need to look at the old state to figu
On Wed, Oct 29, 2014 at 11:32:30AM +0200, Ander Conselvan de Oliveira wrote:
> + if (num_encoders != 1)
> + WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
> + pipe_name(crtc->pipe));
I've folded the check into the WARN here.
-Daniel
--
Daniel Vetter
So
Checking for lvds/edp is wrong (since we also support dsi panels now)
and not terribly useless. If we want to be more intelligent about all
this then we need to look at the old state to figure out whether the
pfit adjustment is needed. This goes all the way back to the original
fastboot pfit patch:
More concise. Noticed while reviewing Ander's patch which touched a
lot of the pipe_has_type checks.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/
It seems that inclusion of intel_xvmc.h is usually protected by INTEL_XVMC.
The unprotected inclusion in src/uda/i965_video.c doesn't seem to be
necessary so rather than protect it, the following should be sufficient?
Cheers,
Patrick
diff --git a/src/uxa/i965_video.c b/src/uxa/i965_video.c
index
Fixes to both the LRC and the legacy ringbuffer code to correctly
calculate and update the available space in a ring.
The logical ring code was updating the software ring 'head' value
by reading the hardware 'HEAD' register. In LRC mode, this is not
valid as the hardware is not necessarily executi
On Thu, Oct 30, 2014 at 03:41:56PM +, Dave Gordon wrote:
> execlists_submit_context() always returns 0, which is redundant.
> And its name is inaccurate, since it actually submits (up to)
> TWO contextS. So we rename it, change it to "void", and remove
> the WARN_ON() testing its return value.
On Fri, Oct 31, 2014 at 04:07:35PM +, Chris Wilson wrote:
> On Fri, Oct 31, 2014 at 02:52:40PM +, Damien Lespiau wrote:
> > On Fri, Oct 31, 2014 at 12:00:26PM +, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > > If a ring failed to initialise for any reason then t
On Thu, Oct 30, 2014 at 05:35:55AM -0700, Rodrigo Vivi wrote:
> It was identified that in some cases when moving cursor Hardware can do
> mistake with idle_frame count. So Spec is being updated to use
> 2 as minimum idle_frames.
>
> Reference:
> https://hsdhsw.intel.com/hsd/haswell_platform/defau
On Fri, Oct 31, 2014 at 11:27:33AM +0200, Ville Syrjälä wrote:
> On Thu, Oct 30, 2014 at 12:57:04PM -0700, Kenneth Graunke wrote:
> > Before we get too much further...we should check if libva is actually
> > broken.
> > I don't know if this means the sampler palette completely doesn't work, or
>
On 11/03/2014 02:33 PM, Daniel Vetter wrote:
On Tue, Oct 28, 2014 at 03:10:12PM +0200, Ander Conselvan de Oliveira wrote:
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_sprite.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers
On Wed, Oct 29, 2014 at 05:30:52PM +, Thomas Wood wrote:
> The "check_" prefix ensures the test programs are not installed and are
> only built when "make check" is run.
>
> Signed-off-by: Thomas Wood
This was actually fairly intentional since when developing I always forget
to hit make chec
On Mon, Nov 03, 2014 at 01:15:24PM +0100, Daniel Vetter wrote:
> On Tue, Oct 28, 2014 at 04:30:41PM +0200, Ville Syrjälä wrote:
> > On Tue, Oct 28, 2014 at 11:26:51AM -0200, Paulo Zanoni wrote:
> > > >> + /*
> > > >> + * We can't change the DDI type if we already have a
>
On Tue, Oct 28, 2014 at 03:10:12PM +0200, Ander Conselvan de Oliveira wrote:
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/dr
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