[Intel-gfx] [QA 10/31 ww44] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platform: Baswell, Broadwell, Baytrail, Haswell, Ivybridge, SandyBridge In this circle, 2 new bugs are filed. Bug 85582 - [All Bisected]igt/testdisplay causes testdisplay.c:789: Failed assertion: ret Bug 85641

[Intel-gfx] [PATCH] drm/i915: Disable caches for Global GTT.

Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000; So the only way to avoid screen corruptions is setting PAT 0 to Uncached. MOCS can still be used though. But if userspace is trusting PTE for cache selection the safest thing to do is to let caches disabled. BSpec: "For GGT

[Intel-gfx] [PATCH] drm/i915: Add debugfs file to dump entire logical context

From: Armin Reese The new 'i915_context_dump' file generates a hex dump of the entire logical context DRM object. It is useful for validating the contents of the default context set up by the golden state batch buffer. Signed-off-by: Armin Reese --- drivers/gpu/drm/i915/i915_debugfs.c | 92 ++

Re: [Intel-gfx] i915.fastboot bug report - not working on coreboot

On Thu, 23 Oct 2014 16:44:26 -0400 Charles Devereaux wrote: > [0.529733] [drm:intel_set_config_compute_mode_changes], modes are > different, full mode set > [0.529736] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 54167 > 1024 1048 1184 1344 768 771 777 806 0x0 0xa > [0.529740]

Re: [Intel-gfx] [PATCH 2/4] drm/i915: preserve swizzle settings if necessary v4

On Tue, 21 Oct 2014 16:49:12 +0200 Daniel Vetter wrote: > On Thu, Oct 09, 2014 at 12:57:43PM -0700, Jesse Barnes wrote: > > Some machines (like MBAs) might use a tiled framebuffer but not > > enable display swizzling at boot time. We want to preserve that > > configuration if possible to prevent

Re: [Intel-gfx] [PATCH] drm/i915: don't try using training pattern 3 on pre-haswell

On Wed, 29 Oct 2014 11:07:32 +0200 Jani Nikula wrote: > On Wed, 29 Oct 2014, Ville Syrjälä wrote: > > On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote: > >> On Wed, 29 Oct 2014, Ville Syrjälä wrote: > >> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote: > >> >> From: Dav

Re: [Intel-gfx] [PATCH 13/14] drm/i915: Use vlv display irq setup code for chv

2014-10-30 15:43 GMT-02:00 : > From: Ville Syrjälä > > Throw away the hand rolled display irq setup code on chv, and instead > just call vlv_display_irq_postinstall() and vlv_display_irq_uninstall(). > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_irq.c | 37 ++---

Re: [Intel-gfx] [PATCH] drm/i915: fix RPS on runtime suspend

On Thu, 2014-10-30 at 15:59 -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > With this patch, the RPS sequence for runtime suspend/resume is > exactly like the sequence for S3 suspend/resume: > - flush_delayed_work(&dev_priv->rps.delayed_resume_work) > - intel_runtime_pm_disable_interrupts()

Re: [Intel-gfx] [PATCH 10/14] drm/i915: Refactor vlv_display_irq_uninstall()

2014-10-30 18:22 GMT-02:00 Paulo Zanoni : > 2014-10-30 15:42 GMT-02:00 : >> From: Ville Syrjälä >> >> Pull the vlv display irq uninstall code into a separate function, for >> eventual sharing with chv. >> >> Signed-off-by: Ville Syrjälä >> --- >> drivers/gpu/drm/i915/i915_irq.c | 25 +++

Re: [Intel-gfx] [PATCH 12/14] drm/i915: Drop useless VLV_IIR writes from vlv_display_irq_postinstall()

2014-10-30 15:43 GMT-02:00 : > From: Ville Syrjälä > > The extra VLV_IIR writes at the end of vlv_display_irq_postinstall() > serve no purpose. Remove them. > > The VLV_IMR/IER/IIR setup at the start of the function also seems a bit > pointless since it doesn't unmask/enable anything. But leave i

Re: [Intel-gfx] [PATCH 11/14] drm/i914: Refactor vlv_display_irq_postinstall()

2014-10-30 15:43 GMT-02:00 : > From: Ville Syrjälä > > Split the vlv display irq postinstall code to a separate function so > that we can share it with chv. Reviewed-by: Paulo Zanoni > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_irq.c | 11 --- > 1 file changed,

Re: [Intel-gfx] [PATCH 10/14] drm/i915: Refactor vlv_display_irq_uninstall()

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Pull the vlv display irq uninstall code into a separate function, for > eventual sharing with chv. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_irq.c | 25 +++-- > 1 file changed, 15 insertions(+),

Re: [Intel-gfx] [PATCH 09/14] drm/i915: Refactor vlv_display_irq_reset()

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Pull the vlv display irq reset code to a new functions. The aim is to > share the code with chv. Reviewed-by: Paulo Zanoni > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_irq.c | 40 +---

Re: [Intel-gfx] [PATCH 08/14] drm/i915: Make valleyview_display_irqs_(un)install() work for chv

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Genralize valleyview_display_irqs_install() and > valleyview_display_irqs_uninstall() enough so that they work on chv. > The only difference to vlv here being the third pipe that chv brings. > > Signed-off-by: Ville Syrjälä > --- > drivers/

Re: [Intel-gfx] [PATCH] drm/i915: Make sample_c messages go faster on Haswell.

On Thursday, October 30, 2014 09:26:01 PM Ville Syrjälä wrote: > On Thu, Oct 30, 2014 at 10:32:38AM -0700, Kenneth Graunke wrote: > > On Thursday, October 30, 2014 01:01:30 PM Ville Syrjälä wrote: > > > On Thu, Oct 30, 2014 at 02:32:40AM -0700, Kenneth Graunke wrote: > > > > On Thursday, October 30

Re: [Intel-gfx] [PATCH] drm/i915: Add support for CHV pipe B sprite CSC

On Thu, Oct 30, 2014 at 1:30 AM, Ville Syrjälä wrote: > On Wed, Oct 29, 2014 at 01:47:35PM -0700, Rodrigo Vivi wrote: >> First of all thanks for the spec >> >> On Mon, Oct 20, 2014 at 9:47 AM, wrote: >> > From: Ville Syrjälä >> > >> > CHV has a programmable CSC unit on the pipe B sprites. Progr

Re: [Intel-gfx] [PATCH 07/14] drm/i915: Call gen5_gt_irq_reset() from valleyview_irq_uninstall()

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Looks like we forgot to call gen5_gt_irq_reset() for vlv in the > uninstall phase. Do so. I also see that valleyview_irq_preinstall() contains 2 writes to GTIIR just before calling gen5_gt_irq_reset(), which should already clear GTIIR, and a

Re: [Intel-gfx] [PATCH 05/14] drm/i915: Use a consistent order between IIR, IER, IMR writes on vlv/chv

On Thu, Oct 30, 2014 at 05:24:05PM -0200, Paulo Zanoni wrote: > 2014-10-30 15:42 GMT-02:00 : > > From: Ville Syrjälä > > > > Follow the same ordering rules for the IIR,IER,IMR writes on vlv/chv > > that we do on other gen5+ platforms. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu

Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use GEN5_IRQ_RESET() on vlv/chv

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Replace the hand rolled IIR,IER,IMR disable sequences with > GEN5_IRQ_RESET(). Reviewed-by: Paulo Zanoni > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_irq.c | 25 + > 1 file changed, 5 inserti

[Intel-gfx] [PATCH] drm/i915: HSW/BDW PSR Set idle_frames=2 since sometimes it can be off by 1.

It was identified that in some cases when moving cursor Hardware can do mistake with idle_frame count. So Spec is being updated to use 2 as minimum idle_frames. Reference: https://hsdhsw.intel.com/hsd/haswell_platform/default.aspx#sighting/default.aspx?sighting_id=4394433 Cc: Arthur Runyan Cc: J

Re: [Intel-gfx] [PATCH] drm/i915: use the correct obj when preparing the sprite plane

2014-10-30 17:10 GMT-02:00 Ville Syrjälä : > On Thu, Oct 30, 2014 at 04:02:01PM -0200, Paulo Zanoni wrote: >> From: Paulo Zanoni >> >> Commit "drm/i915: create a prepare phase for sprite plane updates" >> changed the old_obj pointer we use when committing sprite planes, >> which caused a WARN() an

Re: [Intel-gfx] [PATCH] drm/i915: Make sample_c messages go faster on Haswell.

On Thu, Oct 30, 2014 at 10:32:38AM -0700, Kenneth Graunke wrote: > On Thursday, October 30, 2014 01:01:30 PM Ville Syrjälä wrote: > > On Thu, Oct 30, 2014 at 02:32:40AM -0700, Kenneth Graunke wrote: > > > On Thursday, October 30, 2014 11:00:51 AM Ville Syrjälä wrote: > > > > On Thu, Oct 30, 2014 at

Re: [Intel-gfx] [PATCH 05/14] drm/i915: Use a consistent order between IIR, IER, IMR writes on vlv/chv

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Follow the same ordering rules for the IIR,IER,IMR writes on vlv/chv > that we do on other gen5+ platforms. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_irq.c | 29 ++--- > 1 file changed, 18 in

Re: [Intel-gfx] [PATCH 03/14] drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall()

On Thu, Oct 30, 2014 at 04:49:21PM -0200, Paulo Zanoni wrote: > 2014-10-30 15:42 GMT-02:00 : > > From: Ville Syrjälä > > > > Replace the hand rolled macros with gen8_gt_irq_reset() and > > GEN5_IRQ_RESET() in cherryview_irq_uninstall(). > > > > I guess that was the result of a rebase? I origina

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Use DPINVGTT_STATUS_MASK

On Thu, Oct 30, 2014 at 04:41:36PM -0200, Paulo Zanoni wrote: > 2014-10-30 15:42 GMT-02:00 : > > From: Ville Syrjälä > > > > Some has given a name for the DPINVGTT status bitmask, so let's use it > > instead of the magic number. Looks more like the chv code now. > > Notice that valleyview_irq_po

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers

On Thu, Oct 30, 2014 at 1:33 AM, Ville Syrjälä wrote: > On Wed, Oct 29, 2014 at 02:18:49PM -0700, Rodrigo Vivi wrote: >> On Thu, Oct 16, 2014 at 10:52 AM, wrote: >> > From: Ville Syrjälä >> > >> > CHV adds a bunch of new registers for primary plane size/position and >> > pipe blender setup. Ini

Re: [Intel-gfx] [PATCH v2 15/18] drm/i915/audio: add audio codec disable on g4x

On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote: > This not based on any documentation... :( > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_audio.c | 20 > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_audio.c > b/driver

Re: [Intel-gfx] [PATCH] drm/i915: use the correct obj when preparing the sprite plane

On Thu, Oct 30, 2014 at 04:02:01PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > Commit "drm/i915: create a prepare phase for sprite plane updates" > changed the old_obj pointer we use when committing sprite planes, > which caused a WARN() and a BUG() to be triggered. This patch should > re

Re: [Intel-gfx] [PATCH v2 14/18] drm/i915: enable audio codec after port

Reviewed-by: Rodrigo Vivi On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote: > As per spec, and similar to DDI. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_dp.c | 13 - > drivers/gpu/drm/i915/intel_hdmi.c | 15 +++ > 2 files changed, 15 insertio

Re: [Intel-gfx] [PATCH v2 13/18] drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence

Looks good. Reviewed-by: Rodrigo Vivi On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote: > Add support for disabling the audio codec on vlv/chv/gen5-7, similar to > hsw/bdw. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_audio.c | 52 > +

Re: [Intel-gfx] [PATCH 00/29] Replace seqno values with request structures

Oops, forgot to update the text for the zero patch. This is no longer 'work in progress' and is now intended for proper review! The description should read as follows: There is a general feeling that it is better to move away from using a simple integer 'seqno' value to track batch buffer com

[Intel-gfx] [PATCH 1/6] drm/i915: factor out compute_config from __intel_set_mode v2

This allows us to calculate the full pipe config before we do any mode setting work. v2: - clarify comments about global vs. per-crtc mode set (Ander) - clean up unnecessary pipe_config = NULL setting (Ander) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 96

[Intel-gfx] [PATCH 4/6] drm/i915: check for audio and infoframe changes across mode sets

If these change (e.g. after a modeset following a fastboot), we need to do a full mode set. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_disp

[Intel-gfx] [PATCH 3/6] drm/i915/hdmi: fetch infoframe status in get_config v2

This is useful for checking things later. v2: - fix hsw infoframe enabled check (Ander) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_drv.h | 4 +++ drivers/gpu/drm/i915/intel_hdmi.c | 62 +++ 2 files changed, 66 insertions(+) diff --git a/d

[Intel-gfx] [PATCH 5/6] drm/i915: update pipe size at set_config time

This only affects the fastboot path as-is. In that case, we simply need to make sure that we update the pipe size at the first mode set. Rather than putting it off until we decide to flip (if indeed we do end up flipping), update the pipe size as appropriate a bit earlier in the set_config call.

[Intel-gfx] [PATCH 2/6] drm/i915: use compute_config in set_config v2

This will allow us to consult more info before deciding whether to flip or do a full mode set. v2: - don't use uninitialized or incorrect pipe masks in set_config failure path (Ander) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 30 ++

[Intel-gfx] [PATCH 6/6] drm/i915: calculate pfit changes in set_config v2

This should allow us to avoid mode sets for some panel fitter config changes. v2: - fixup pfit comment (Ander) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 61 +--- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/driver

Re: [Intel-gfx] [PATCH 04/14] drm/i915: Drop the extra GEN8_PCU_IIR posting read from cherryview_irq_preinstall()

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Looks like a leftover POSTING_READ(GEN8_PCU_IIR) in > cherryview_irq_preinstall() from some earlier age. GEN5_IRQ_RESET() > already does the posting read so this changes nothing, so kill it. Reviewed-by: Paulo Zanoni > > Signed-off-by: Vil

Re: [Intel-gfx] [PATCH 3/6] drm/i915/hdmi: fetch infoframe status in get_config

On Thu, 30 Oct 2014 15:20:43 +0200 Ander Conselvan de Oliveira wrote: > On 10/23/2014 09:50 PM, Jesse Barnes wrote: > > This is useful for checking things later. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_drv.h | 4 +++ > > drivers/gpu/drm/i915/intel_hdmi.c |

Re: [Intel-gfx] [PATCH 03/14] drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall()

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Replace the hand rolled macros with gen8_gt_irq_reset() and > GEN5_IRQ_RESET() in cherryview_irq_uninstall(). > I guess that was the result of a rebase? Reviewed-by: Paulo Zanoni > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i9

Re: [Intel-gfx] [PATCH 2/6] drm/i915: use compute_config in set_config

On Wed, 29 Oct 2014 16:31:56 +0200 Ander Conselvan de Oliveira wrote: > On 10/23/2014 09:50 PM, Jesse Barnes wrote: > > This will allow us to consult more info before deciding whether to > > flip or do a full mode set. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_

[Intel-gfx] [PATCH 19/29] drm/i915: Convert 'ring_idle()' to use requests not seqnos

From: John Harrison More seqno value to request structure conversions. Note, this change temporarily moves the 'get_seqno()' call inside ring_idle() but this will disappear again in a later patch when i915_seqno_passed() itself is converted. For: VIZ-4377 Signed-off-by: John Harrison --- drive

[Intel-gfx] [PATCH 29/29] WIP: Defer seqno allocation until actual hardware submission time

From: John Harrison *** Work in progress. Do not submit - currently broken! *** This patch is being included in the series simply to show the intention. The seqno value is now only used for the final test for completion of a request. It is no longer used to track the request through the software

[Intel-gfx] [PATCH 21/29] drm/i915: Convert 'i915_seqno_passed' calls into 'i915_gem_request_completed'

From: John Harrison Almost everywhere that caled i915_seqno_passed() was really asking 'has the given seqno popped out of the hardware yet?'. Thus it had to query the current hardware seqno and then do a signed delta comparison (which copes with wrapping around zero but not with seqno values more

[Intel-gfx] [PATCH 25/29] drm/i915: Spinlock protection for request list

From: John Harrison The completion status for all entries in the request list is updated on demand. This occurs whenever the code queries the completion status of a given request and a new seqno value has popped out of the hardware. Unfortuntately, not all such queries are done with the driver mu

[Intel-gfx] [PATCH 18/29] drm/i915: Convert 'trace_irq' to use requests rather than seqnos

From: John Harrison Updated the trace_irq code to use requests instead of seqnos. This includes reference counting the request object to ensure it sticks around when required. Note that getting access to the reference counting functions means moving the inline i915_trace_irq_get() function from i

[Intel-gfx] [PATCH 27/29] drm/i915: Interrupt driven request completion

From: John Harrison Added a hook to the ring noftification code to process request completion. This means that there is no longer a need to explicitly process request completions every time a request object is tested. Instead, the test code simply becomes 'return req->completed'. Obviously, this

[Intel-gfx] [PATCH 23/29] drm/i915: Cache request completion status

From: John Harrison Continuing the removal of seqno based operations - updated the request completion query to not simply chain on to i915_seqno_passed(). Instead, it now simply returns a pre-cached completion flag in the fast case. In the slow case it reads the hardware seqno and, only if it has

[Intel-gfx] [PATCH 26/29] drm/i915: Add uniq id to request structure for debugging

From: John Harrison For debugging purposes, it is useful to be able to uniquely identify a given request structure as it works its way through the system. This becomes especially tricky if the seqno value is late allocated as then the request has nothing but its pointer to identify it for much of

[Intel-gfx] [PATCH 28/29] drm/i915: Remove obsolete parameter to i915_gem_request_completed()

From: John Harrison The request completion test no longer chains on to the request completion processing code. Thus it no longer needs to pass a 'lazy coherency' flag through to the seqno query call. Hence that parameter can be removed. For: VIZ-4377 Signed-off-by: John Harrison --- drivers/gp

[Intel-gfx] [PATCH 13/29] drm/i915: Remove obsolete seqno parameter from 'i915_add_request'

From: John Harrison There is no longer any need to retreive a seqno value from an i915_add_request() call. The calling code already knows which request structure is being processed (it can only be ring->OLR). And as the request itself is now used in preference to the basic seqno value, the latter

[Intel-gfx] [PATCH 20/29] drm/i915: Connect requests to rings at creation not submission

From: John Harrison It makes a lot more sense (and makes future seqno -> request conversion patches simpler) to fill in the 'ring' field of the request structure at the point of creation rather than submission. Given that the request structure is assigned by ring specific code and thus is locked

[Intel-gfx] [PATCH 17/29] drm/i915: Convert trace functions from seqno to request

From: John Harrison All the code above is now using requests not seqnos so it is possible to convert the trace functions across. Note that rather than get into problematic reference counting issues, the trace code only saves the seqno and ring values from the request structure not the structure p

[Intel-gfx] [PATCH 22/29] drm/i915: Remove the now redundant 'obj->ring'

From: John Harrison The ring member of the object structure was always updated with the last_read_seqno member. Thus with the conversion to last_read_req, obj->ring is now a direct copy of obj->last_read_req->ring. This makes it somewhat redundant and potentially misleading (especially as there w

[Intel-gfx] [PATCH 01/29] drm/i915: Remove redundant parameter to i915_gem_object_wait_rendering__tail()

From: John Harrison An earlier commit (c8725f3dc0911d4354315a65150aecd8b7d0d74a: Do not call retire_requests from wait_for_rendering) removed the use of the ring parameter within wait_rendering__tail() but did not remove the parameter itself. As the plan is to remove obj->ring which is where this

[Intel-gfx] [PATCH 09/29] drm/i915: Make 'i915_gem_check_olr' actually check by request not seqno

From: John Harrison Updated the _check_olr() function to actually take a requst object and compare it to the OLR rather than extracting seqnos and comparing those. Note that there is one use case where the request object being processed is no longer available at that point in the call stack. Hen

[Intel-gfx] [PATCH 24/29] drm/i915: Zero fill the request structure

From: John Harrison There is a general theory that kzmalloc is better/safer than kmalloc, especially for interesting data structures. This change updates the request structure allocation to be zero filled. That also means it is no longer necessary to explicitly clear the 'complete' field. For: V

[Intel-gfx] [PATCH 06/29] drm/i915: Convert i915_gem_ring_throttle to use requests

From: John Harrison Convert the throttle code to use the request structure rather than extracting a ring/seqno pair from it and using those. This is in preparation for __wait_seqno() becoming __wait_request(). For: VIZ-4377 Signed-off-by: John Harrison --- drivers/gpu/drm/i915/i915_gem.c |

[Intel-gfx] [PATCH 00/29] Replace seqno values with request structures

From: John Harrison Work in progress for replacing seqno usage with requst structures. There is a general feeling that it is better to move away from using a simple integer 'seqno' value to track batch buffer completion. Instead, the request structure should be used. That provides for much more

[Intel-gfx] [PATCH 02/29] drm/i915: Ensure OLS & PLR are always in sync

From: John Harrison The aim is to replace seqno values with request structures. A step along the way is to switch to using the PLR in preference to the OLS. That requires the PLR to only be valid when and only when the OLS is also valid. I.e., the two must be kept in lock step. Then, code which w

[Intel-gfx] [PATCH 03/29] drm/i915: Add reference count to request structure

From: John Harrison The plan is to use request structures everywhere that seqno values were previously used. This means saving pointers to structures in places that used to be simple integers. In turn, that means that the target structure now needs much more stringent lifetime tracking. That is,

[Intel-gfx] [PATCH 14/29] drm/i915: Convert mmio_flip::seqno to struct request

From: John Harrison Converted the mmio_flip 'seqno' value to be a request structure as part of the on going seqno to request changes. This includes reference counting the request being saved away to ensure it can not be retired and freed while the flip code is still waiting on it. For: VIZ-4377

[Intel-gfx] [PATCH 11/29] drm/i915: Convert i915_wait_seqno to i915_wait_request

From: John Harrison Updated i915_wait_seqno() to take a request structure instead of a seqno value and renamed it accordingly. Internally, it just pulls the seqno out of the request and calls on to __wait_seqno() as before. However, all the code further up the stack is now simplified as it can ju

[Intel-gfx] [PATCH 16/29] drm/i915: Convert 'flip_queued_seqno' into 'flip_queued_request'

From: John Harrison Converted the flip_queued_seqno value to be a request structure as part of the on going seqno to request changes. This includes reference counting the request being saved away to ensure it can not be retired and freed while the flip code is still waiting on it. For: VIZ-4377

[Intel-gfx] [PATCH 15/29] drm/i915: Add IRQ friendly request deference facility

From: John Harrison The next patch in the series converts some display related seqno usage to request structure usage. However, the request dereference introduced must be done from interrupt context. As the dereference potentially involves freeing the request structure and thus call lots of non-i

[Intel-gfx] [PATCH 10/29] drm/i915: Convert 'last_flip_req' to be a request not a seqno

From: John Harrison Converted 'last_flip_req' to be an actual request rather than a seqno value as part of the on going seqno to request changes. This includes reference counting the request being saved away to ensure it can not be retired and freed while the overlay code is still waiting on it.

[Intel-gfx] [PATCH 05/29] drm/i915: Replace last_[rwf]_seqno with last_[rwf]_req

From: John Harrison The object structure contains the last read, write and fenced seqno values for use in syncrhonisation operations. These have now been replaced with their request structure counterparts. Note that to ensure that objects do not end up with dangling pointers, the assignments of

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Use DPINVGTT_STATUS_MASK

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > Some has given a name for the DPINVGTT status bitmask, so let's use it > instead of the magic number. Looks more like the chv code now. Notice that valleyview_irq_postinstall() contains a write using the correct name, but it's under an "#if

[Intel-gfx] [PATCH 07/29] drm/i915: Ensure requests stick around during waits

From: John Harrison Added reference counting of the request structure around __wait_seqno() calls. This is a precursor to updating the wait code itself to take the request rather than a seqno. At that point, it would be a Bad Idea for a request object to be retired and freed while the wait code i

[Intel-gfx] [PATCH 12/29] drm/i915: Convert __wait_seqno() to __wait_request()

From: John Harrison Now that all code above is using request structures instead of seqno values, it is possible to convert __wait_seqno() itself. Internally, it is still calling i915_seqno_passed(), this will be updated later in the series. This step is just changing the parameter list and funct

[Intel-gfx] [PATCH 08/29] drm/i915: Remove 'outstanding_lazy_seqno'

From: John Harrison The OLS value is now obsolete. Exactly the same value is guarateed to be always available as PLR->seqno. Thus it is safe to remove the OLS completely. And also to rename the PLR to OLR to keep the 'outstanding lazy ...' naming convention valid. For: VIZ-4377 Signed-off-by: Jo

[Intel-gfx] [PATCH 04/29] drm/i915: Add helper functions to aid seqno -> request transition

From: John Harrison Added helper functions for retreiving the ring and seqno entries from a request structure. This allows the internal workings of the request structure to be hidden from code that is using these. It also allows for useful workarounds/debug code to be added as or when necessary.

Re: [Intel-gfx] [PATCH 1/6] drm/i915: factor out compute_config from __intel_set_mode

On Wed, 29 Oct 2014 16:30:43 +0200 Ander Conselvan de Oliveira wrote: > On 10/23/2014 09:50 PM, Jesse Barnes wrote: > > This allows us to calculate the full pipe config before we do any > > mode setting work. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_display.c

Re: [Intel-gfx] [PATCH 01/14] drm/i915: Apply some ocd for IMR vs. IER order during irq enable

2014-10-30 15:42 GMT-02:00 : > From: Ville Syrjälä > > When disabling interrupts we do the writes in this order: > IMR,IER,IIR,IIR. But when enabling interrupts we don't do use the > mirrored order, and instead do IIR,IIR,IMR,IER. > > I like consistency unless there's a good reason against it, wh

[Intel-gfx] [PATCH] RFC drm/i915: Deflate error objects upon capture

When we capture the GPU error state, we allocate large amounts of memory to preserve copies of the active objects on the GPU. We can compress the copy in memory, and use an asci85 encoding when printing them out (to avoid presenting binary data to unsuspecting catting of debugfs/procfs). Signed-of

Re: [Intel-gfx] [PATCH v3] drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence

On Tue, Oct 28, 2014 at 5:04 AM, Jani Nikula wrote: > Similar to the hsw/bdw enable sequence rewrite. > > v3: replace vblank wait with a comment > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_audio.c | 58 > +- > 1 file changed, 26 insertio

[Intel-gfx] [PATCH] drm/i915: use the correct obj when preparing the sprite plane

From: Paulo Zanoni Commit "drm/i915: create a prepare phase for sprite plane updates" changed the old_obj pointer we use when committing sprite planes, which caused a WARN() and a BUG() to be triggered. This patch should revert the code back to the previous behavior, fixing the regression. Regre

[Intel-gfx] [PATCH] drm/i915: fix RPS on runtime suspend

From: Paulo Zanoni With this patch, the RPS sequence for runtime suspend/resume is exactly like the sequence for S3 suspend/resume: - flush_delayed_work(&dev_priv->rps.delayed_resume_work) - intel_runtime_pm_disable_interrupts() - intel_suspend_gt_powersave() (suspended) - intel_runtime_pm

Re: [Intel-gfx] [PATCH v3] drm/i915: rewrite hsw/bdw audio codec enable/disable sequences

On Tue, Oct 28, 2014 at 5:03 AM, Jani Nikula wrote: > There's some serious confusion regarding ELD valid bit that gets set and > cleared back and forth etc. Rewrite it all based on the documented audio > codec enable/disable sequences. > > v3: replace vblank wait with a comment > > Signed-off-by:

[Intel-gfx] [PATCH] drm/i915: fix "Unexpected fault" error message line break

From: Paulo Zanoni Fix the message, not the fault :) This is what I see: [ 282.108597] [drm:i915_check_and_clear_faults] Unexpected fault [ 282.108597] Addr: 0x\n Address space: PPGTT [ 282.108597] Source ID: 24 [ 282.108597] Type: 0 Signed-off-by: Paulo Zanoni --- drivers

[Intel-gfx] [PATCH 12/14] drm/i915: Drop useless VLV_IIR writes from vlv_display_irq_postinstall()

From: Ville Syrjälä The extra VLV_IIR writes at the end of vlv_display_irq_postinstall() serve no purpose. Remove them. The VLV_IMR/IER/IIR setup at the start of the function also seems a bit pointless since it doesn't unmask/enable anything. But leave it be for now. Signed-off-by: Ville Syrjäl

[Intel-gfx] [PATCH 14/14] drm/i915: Reinit display irqs and hpd from chv pipe-a power well

From: Ville Syrjälä On chv the pipe-a power well is the new disp2d well, and it kills pretty much everything in the display block. So we need to do the the same dance that vlv does wrt. display irqs and hpd when the power well goes up or down. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i

[Intel-gfx] [PATCH 10/14] drm/i915: Refactor vlv_display_irq_uninstall()

From: Ville Syrjälä Pull the vlv display irq uninstall code into a separate function, for eventual sharing with chv. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/

[Intel-gfx] [PATCH 02/14] drm/i915: Use DPINVGTT_STATUS_MASK

From: Ville Syrjälä Some has given a name for the DPINVGTT status bitmask, so let's use it instead of the magic number. Looks more like the chv code now. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers

[Intel-gfx] [PATCH 09/14] drm/i915: Refactor vlv_display_irq_reset()

From: Ville Syrjälä Pull the vlv display irq reset code to a new functions. The aim is to share the code with chv. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 40 +--- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH 04/14] drm/i915: Drop the extra GEN8_PCU_IIR posting read from cherryview_irq_preinstall()

From: Ville Syrjälä Looks like a leftover POSTING_READ(GEN8_PCU_IIR) in cherryview_irq_preinstall() from some earlier age. GEN5_IRQ_RESET() already does the posting read so this changes nothing, so kill it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 2 -- 1 file changed

[Intel-gfx] [PATCH 13/14] drm/i915: Use vlv display irq setup code for chv

From: Ville Syrjälä Throw away the hand rolled display irq setup code on chv, and instead just call vlv_display_irq_postinstall() and vlv_display_irq_uninstall(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 37 ++--- 1 file changed, 2 inse

[Intel-gfx] [PATCH 00/14] drm/i915: IRQ work for chv mostly

From: Ville Syrjälä After enabling the pipe-a power well on CHV I noticed that hpd and interrupts didn't work too well anymore. The reason is the same as on VLV; the power well kills that stuff. So we need to get CHV to use the vlv display irq management code. Thise series does that, and there's

[Intel-gfx] [PATCH 08/14] drm/i915: Make valleyview_display_irqs_(un)install() work for chv

From: Ville Syrjälä Genralize valleyview_display_irqs_install() and valleyview_display_irqs_uninstall() enough so that they work on chv. The only difference to vlv here being the third pipe that chv brings. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 27 +

[Intel-gfx] [PATCH 05/14] drm/i915: Use a consistent order between IIR, IER, IMR writes on vlv/chv

From: Ville Syrjälä Follow the same ordering rules for the IIR,IER,IMR writes on vlv/chv that we do on other gen5+ platforms. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH 03/14] drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall()

From: Ville Syrjälä Replace the hand rolled macros with gen8_gt_irq_reset() and GEN5_IRQ_RESET() in cherryview_irq_uninstall(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 28 ++-- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH 11/14] drm/i914: Refactor vlv_display_irq_postinstall()

From: Ville Syrjälä Split the vlv display irq postinstall code to a separate function so that we can share it with chv. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq

[Intel-gfx] [PATCH 06/14] drm/i915: Use GEN5_IRQ_RESET() on vlv/chv

From: Ville Syrjälä Replace the hand rolled IIR,IER,IMR disable sequences with GEN5_IRQ_RESET(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 25 + 1 file changed, 5 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/dri

[Intel-gfx] [PATCH 07/14] drm/i915: Call gen5_gt_irq_reset() from valleyview_irq_uninstall()

From: Ville Syrjälä Looks like we forgot to call gen5_gt_irq_reset() for vlv in the uninstall phase. Do so. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c i

[Intel-gfx] [PATCH 01/14] drm/i915: Apply some ocd for IMR vs. IER order during irq enable

From: Ville Syrjälä When disabling interrupts we do the writes in this order: IMR,IER,IIR,IIR. But when enabling interrupts we don't do use the mirrored order, and instead do IIR,IIR,IMR,IER. I like consistency unless there's a good reason against it, which I can't think of here, so change the e

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Unclutter the get_plane() functions

On Thu, Oct 30, 2014 at 05:31:57PM +, Tvrtko Ursulin wrote: > > On 10/29/2014 05:22 PM, Damien Lespiau wrote: > >crtc->base.primary->fb was used everywhere. Use fb to temporarily point > >there and don't forget to assign fb to its final destination at the end. > > > >v2: Rebase on top of misc

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Unclutter the get_plane() functions

On 10/29/2014 05:22 PM, Damien Lespiau wrote: crtc->base.primary->fb was used everywhere. Use fb to temporarily point there and don't forget to assign fb to its final destination at the end. v2: Rebase on top of misc changes (mask of DSPSURF, PAGE_ALIGN) Signed-off-by: Damien Lespiau --- dr

Re: [Intel-gfx] [PATCH] drm/i915: Make sample_c messages go faster on Haswell.

On Thursday, October 30, 2014 01:01:30 PM Ville Syrjälä wrote: > On Thu, Oct 30, 2014 at 02:32:40AM -0700, Kenneth Graunke wrote: > > On Thursday, October 30, 2014 11:00:51 AM Ville Syrjälä wrote: > > > On Thu, Oct 30, 2014 at 10:50:03AM +0200, Ville Syrjälä wrote: > > > > On Wed, Oct 29, 2014 at 0

Re: [Intel-gfx] [PATCH v2 07/18] drm/i915/ddi: write ELD where it's supposed to be done

Reviewed-by: Rodrigo Vivi On Tue, Oct 28, 2014 at 1:28 AM, Jani Nikula wrote: > On Mon, 27 Oct 2014, Rodrigo Vivi wrote: >> On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote: >>> The audio programming sequence states that the ELD must be written and >>> enabled after the pipe is ready. Indeed

Re: [Intel-gfx] [RFC 3/5] drm/i915: Infrastructure for supporting different GGTT views per object

On 10/30/2014 04:41 PM, Chris Wilson wrote: On Thu, Oct 30, 2014 at 04:39:36PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Things like reliable GGTT mappings and mirrored 3d display will need to be to map the same object twice into the GGTT. What's a reliable GGTT mapping and how does

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