Thanks for your comments Thierry.
I agree to all your comments.
I will write a general function to return version and repost the patch
Thanks,
Sonika
On Wednesday 29 October 2014 07:12 PM, Thierry Reding wrote:
On Wed, Oct 22, 2014 at 11:45:23AM +0530, sonika.jin...@intel.com wrote:
From: Soni
On Wed, Oct 29, 2014 at 09:21:20PM +0200, Ville Syrjälä wrote:
> On Thu, Sep 04, 2014 at 12:27:47PM +0100, Damien Lespiau wrote:
> > So we can use it in the modeset checker.
> >
> > v2: Rebase on top of nigthly
> >
> > v3: Rebase on top of -nigthly (minor conflict in intel_drv.h)
> >
> > Signed-
Haswell significantly improved the performance of sampler_c messages,
but the optimization appears to be off by default. Later platforms
remove this bit, and apparently always enable the optimization.
Improves performance in "Counter Strike: Global Offensive" by 18%
at default settings on Iris Pr
On Tue, Oct 28, 2014 at 5:03 AM, Jani Nikula wrote:
> There's some serious confusion regarding ELD valid bit that gets set and
> cleared back and forth etc. Rewrite it all based on the documented audio
> codec enable/disable sequences.
>
> v3: replace vblank wait with a comment
Why did you remove
Oh, I was going to review the rest... but based on this comment I
guess I might wait for a new v2 series right?
On Tue, Oct 28, 2014 at 12:30 AM, Daniel Vetter wrote:
> On Mon, Oct 27, 2014 at 10:52:00AM -0700, Rodrigo Vivi wrote:
>> On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote:
>> > This
On Thu, Oct 16, 2014 at 10:52 AM, wrote:
> From: Ville Syrjälä
>
> CHV adds a bunch of new registers for primary plane size/position and
> pipe blender setup. Initialize all those registers to avoid nasty
> surprises. PRIMSIZE is especially important as without programming it
> the outout will b
First of all thanks for the spec
On Mon, Oct 20, 2014 at 9:47 AM, wrote:
> From: Ville Syrjälä
>
> CHV has a programmable CSC unit on the pipe B sprites. Program the unit
> appropriately for BT.601 limited range YCbCr to full range RGB color
> conversion. This matches the programming we current
On Thu, Sep 04, 2014 at 12:27:48PM +0100, Damien Lespiau wrote:
> v2: minor conflict in i915_debugfs.c
> v3: Rebase on top of the for_each_pipe() change adding dev_priv as first
> argument.
> v4: minor conflict in the i915_debugfs_files array
> v5: minor conflict in the i915_debugfs_files array
On Thu, Sep 04, 2014 at 12:27:47PM +0100, Damien Lespiau wrote:
> So we can use it in the modeset checker.
>
> v2: Rebase on top of nigthly
>
> v3: Rebase on top of -nigthly (minor conflict in intel_drv.h)
>
> Signed-off-by: Damien Lespiau
I don't know if I should even bother with the r-b. Fee
On Thu, Sep 04, 2014 at 12:27:42PM +0100, Damien Lespiau wrote:
> We're going to add a new step, let's not hide the copy of the new WM
> state inside one inner function, but as a 1st level operation in the WM
> update.
The new step being the flush which needs to compare the currnet and new
ddb sta
On Thu, Sep 04, 2014 at 03:27:49PM +0200, Daniel Vetter wrote:
> On Thu, Sep 04, 2014 at 12:27:49PM +0100, Damien Lespiau wrote:
> > v2: Don't check DDB on pre-SKL platforms
> > Don't check DDB state on disabled pipes
> >
> > Signed-off-by: Damien Lespiau
>
> We probably want to do this with
On Wed, Sep 24, 2014 at 03:06:11PM +0100, Damien Lespiau wrote:
> On Fri, Sep 19, 2014 at 01:05:02PM +0300, Ville Syrjälä wrote:
> >
> > If we're going to be paranoid I think we should disable all higher WM
> > levels whose latency is lower than any of the lower levels. And I
> > think we'll want
On Thu, Sep 04, 2014 at 12:27:16PM +0100, Damien Lespiau wrote:
> From: Pradeep Bhat
>
> This patch provides the implementation for reading the pipe wm HW
> state.
>
> v2: Incorporated Damien's review comments and also made modifications
> to incorporate the plane/cursor split.
>
> v3: No n
On Sat, Sep 27, 2014 at 03:17:58PM +0100, Damien Lespiau wrote:
> On Fri, Sep 19, 2014 at 01:03:15PM +0300, Ville Syrjälä wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 0ddcbad..756ff16 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.
On Wed, Oct 15, 2014 at 06:34:41PM +0100, Damien Lespiau wrote:
> Ville found that the sequencing I had to re-program the DDB wasn't quite
> correct and so this is an attempt to do better.
>
> This series reworks patch:
>
> [PATCH 78/89] drm/i915/skl: Flush the WM configuration
>
> of the init
On Wed, Oct 15, 2014 at 06:34:43PM +0100, Damien Lespiau wrote:
> When we write new values for the DDB allocation and WM parameters, we now
> need to trigger the double buffer update for the pipe to take the new
> configuration into account.
>
> As the DDB is a global resource shared between plane
The "check_" prefix ensures the test programs are not installed and are
only built when "make check" is run.
Signed-off-by: Thomas Wood
---
lib/tests/Makefile.am | 5 +
lib/tests/Makefile.sources | 12
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/lib/tes
Fix distcheck issues introduced by commit 685e577 (Move library
selftests to lib/tests).
Cc: Daniel Vetter
Signed-off-by: Thomas Wood
---
lib/tests/Makefile.am | 2 +-
tests/Makefile.sources | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/lib/tests/Makefile.am b/lib/tests/
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 200a62e..c77cf9b 100644
--- a
On Tue, Oct 14, 2014 at 05:30:58PM +0100, Damien Lespiau wrote:
> Here's a few patches on top of the original WM series to both address some
> review comments from Ville and disable the transition WMs (because we noticed
> some underruns with them and the code is not quit ready).
>
> With those, I
We may as well try to be consistent everywhere and know the pipes by
their name.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/
crtc->base.primary->fb was used everywhere. Use fb to temporarily point
there and don't forget to assign fb to its final destination at the end.
v2: Rebase on top of misc changes (mask of DSPSURF, PAGE_ALIGN)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 61 ++
Universal planes have changed a bit the register organization.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 108 ---
1 file changed, 101 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
If we need to change the fb height constraints, it sounds like a good
idea to have to do it in one place only.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 19 +++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_fbdev.c | 3
We will have a skl_ version shortly!
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c77cf9b..02b2a97 100644
--- a/d
crtc->plane can only be different from crtc->pipe pre-Gen4. Don't use it
in new-ish code.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gp
Skylake changed a few things here and there in the plane registers and we
weren't correctly reading out the primary plane state when trying to re-use the
BIOS stolen allocated fb (especially the stride was all wrong). Of course,
weird artefacts ensued when loading the driver.
This series implement
Rather than having "tiled" meaning "is it X-tiled?" convert the field to
explicitely store the tiling mode. The code doesn't have to change much
as 1 is conveniently I915_TILING_X.
This is to accommodate future changes around tiling modes and scannout
buffers.
Signed-off-by: Damien Lespiau
---
On Sat, Sep 27, 2014 at 03:15:00PM +0100, Damien Lespiau wrote:
> v2: Fix the 3rd plane/cursor logic (Pradeep Bhat)
> v3: Fix one-by-one error in the DDB allocation code
> v4: Rebase on top of the skl_pipe_pixel_rate() argument change
> v5: Replace the available/start/end output parameters of
>
On Tue, Sep 23, 2014 at 12:13:50PM +0100, Damien Lespiau wrote:
> From: Pradeep Bhat
>
> This patch implements the watermark algorithm and its necessary
> functions. Two function pointers skl_update_wm and
> skl_update_sprite_wm are provided. The skl_update_wm will update
> the watermarks for the
On Tue, Oct 14, 2014 at 05:31:01PM +0100, Damien Lespiau wrote:
> To align with the ilk WM code and because it makes sense to test against
> the upper bounds as soon as possible, let's move the maximum checks from
> skl_compute_wm_results() to skl_compute_plane_wm().
>
> This has the nice benefit
This fixes the build problems introduced by commit 685e577 (Move library
selftests to lib/tests).
Cc: Daniel Vetter
Signed-off-by: Thomas Wood
---
lib/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 6b1e984..ab82302 100644
On Tue, Oct 14, 2014 at 05:30:59PM +0100, Damien Lespiau wrote:
> Ville suggested that we should use the same semantics as C arrays to
> reduce the number of those pesky +1/-1 in the allocation code.
>
> This patch leaves the debugfs file as is, showing the internal DDB
> allocation structure, not
On Thu, Sep 04, 2014 at 12:27:12PM +0100, Damien Lespiau wrote:
> We now need to allocate space in the DDB for planes being scanned out
> ourselves. The data structure to represent an allocation mirrors what
> we'll need to write in the registers later on: (start, end).
>
> We add that allocation
Signed-off-by: Thomas Wood
---
lib/igt_core.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/lib/igt_core.h b/lib/igt_core.h
index 5318c5e..f7a92ce 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -199,7 +199,7 @@ void __igt_skip_check(const char *file, const int line
Signed-off-by: Thomas Wood
---
lib/igt_core.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/igt_core.h b/lib/igt_core.h
index b8f6702..5318c5e 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -397,7 +397,7 @@ void igt_exit(void) __attribute__((noreturn));
* informat
On Wed, Oct 22, 2014 at 11:45:23AM +0530, sonika.jin...@intel.com wrote:
> From: Sonika Jindal
>
> v2: Reading DP_EDP_REV, only when DISPLAY_CONTROL_CAPABLE field is set
> (Satheesh)
>
> v3: Moving the utility function to drm_dp_helper (Daniel)
>
> Signed-off-by: Sonika Jindal
> ---
> driver
When looking at the bug report logs with triggered
WARN_ON, the person doing bug triaging will have to
find exact kernel source and match file/line.
Attach the condition that triggered the WARN_ON
to kernel log. In most cases the context is self
evident and this way we can save developer time.
Th
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=354/354->353/354
PNV: pass/total=331/331->331
On Wed, Oct 29, 2014 at 02:10:45PM +0200, Mika Kuoppala wrote:
> Zhi Wang writes:
>
> > Currently MI_BATCH_BUFFER_END is missed in null state batch buffer.
> > This fix is trying to append the missed instruction at the end of
> > null state batch buffer gem bo after it was initialized and filled
On Wed, Oct 29, 2014 at 10:11:25AM +0100, Daniel Vetter wrote:
> Just a bit of OCD cleanup on headers - this function isn't the core
> interface any more but just a helper for drivers who haven't yet
> transitioned to universal planes. Put the declaration at the right
> spot and sprinkle necessary
On 10/23/2014 09:50 PM, Jesse Barnes wrote:
This will allow us to consult more info before deciding whether to flip
or do a full mode set.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 36 ++--
1 file changed, 30 insertions(+), 6 delet
On 10/23/2014 09:50 PM, Jesse Barnes wrote:
This allows us to calculate the full pipe config before we do any mode
setting work.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 93 +---
1 file changed, 65 insertions(+), 28 deletions(-)
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=271/271->271/271
PNV: pass/total=331/331->328
Thanks Mika. Just found that command in render state. It mixed the commands
with indirect state together.
And my problem is caused by my old drm-intel-nightly branch. Sorry for being
annoyed.
-Original Message-
From: Mika Kuoppala [mailto:mika.kuopp...@linux.intel.com]
Sent: Wednesda
This is a regression from
4306538d1d3f60877866c39c9ca953cc5e541dae is the first bad commit
commit 4306538d1d3f60877866c39c9ca953cc5e541dae
Author: Daniel Vetter
AuthorDate: Thu Oct 2 11:18:20 2014 +0200
Commit: Daniel Vetter
CommitDate: Thu Oct 2 11:34:55 2014 +0200
tests: Sprinkle
This seems to have been accidentally disabled in
commit 982f7eb238a0898c456e0574dee7c4507738d75f
Author: Chris Wilson
Date: Fri Aug 29 15:19:57 2014 +0100
Prepare for 64bit relocation addresses
Apparently no one noticed.
Cc: Chris Wilson
Signed-off-by: Daniel Vetter
---
tests/Makefile
Zhi Wang writes:
> Currently MI_BATCH_BUFFER_END is missed in null state batch buffer.
> This fix is trying to append the missed instruction at the end of
> null state batch buffer gem bo after it was initialized and filled
> with null state commands.
>
> This issue was exposed under full GPU vir
Chris removed the code using it in:
commit be2d599b5da3936ca92e0187ff50b34b6b8ff997
Author: Chris Wilson
Date: Wed Sep 10 19:52:18 2014 +0100
drm/i915: Remove dead code, i915_gem_verify_gtt
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
1 file changed,
On Wed, 29 Oct 2014, Damien Lespiau wrote:
> As Paulo said when introducing the enum, having more types is really
> good to document what should go where (int foo(int, int, bool, bool).
>
> Cc: Paulo Zanoni
> Signed-off-by: Damien Lespiau
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i91
As Paulo said when introducing the enum, having more types is really
good to document what should go where (int foo(int, int, bool, bool).
Cc: Paulo Zanoni
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
2 files changed
On Wed, Oct 29, 2014 at 11:03:26AM +0200, Jani Nikula wrote:
> Ivybridge + 30" monitor prints a drm error on every modeset, since IVB
> doesn't support DP3 we should even bother trying to use it.
>
> This regression has been introduced in
>
> commit 06ea66b6bb445043dc25a9626254d5c130093199
> Auth
No longer create a work item to clean each execlist queue item.
Instead, move retired execlist requests to a queue and clean up the
items during retire_requests.
v2: Fix legacy ring path broken during overzealous cleanup
v3: Update idle detection to take execlists queue into account
Issue: VIZ-4
Write HWS_PGA address even in execlists mode as the global hardware status
page is still required. This address was previously uninitialized and
HWSP writes would clobber whatever buffer happened to reside at GGTT
address 0.
v2: Break out hardware status page setup into a separate function.
Issu
From: Oscar Mateo
Up until now, we have pinned every logical ring context backing object
during creation, and left it pinned until destruction. This made my life
easier, but it's a harmful thing to do, because we cause fragmentation
of the GGTT (and, eventually, we would run out of space).
This
Same as with the context, pinning to GGTT regardless is harmful (it
badly fragments the GGTT and can even exhaust it).
Unfortunately, this case is also more complex than the previous one
because we need to map and access the ringbuffer in several places
along the execbuffer path (and we cannot mak
It is possible for a mode set to fail if there aren't shared DPLLS that
match the new configuration requirement or other errors in clock
computation. If that step is executed after disabling crtcs, in the
failure case the hardware configuration is changed and needs to be
restored. Doing those thing
Use the infrastructure added in a previous patch to choose shared DPLLs
and calculate clocks before touching the hardware.
v2: Don't set mode_set hooks since dev_priv is kzalloc()'d (Ville)
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 2 --
drivers/gpu/
Use the infrastructure added in a previous patch to choose shared DPLLs
and calculate clocks before touching the hardware.
v2: Don't set mode_set hooks since dev_priv is kzalloc()'d (Ville)
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 13 -
Now that shared DPLLs configuration is staged, there's no need to track
the current ones in the new pipe_config since those are released before
making the new pipe_config effective.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed,
The new struct will be used in a follow up patch to allow a current and
a staged config to exist for the same shared DPLL.
v2: Rebase on by mask_to_refcount()->hweight32() change. (Damien)
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_deb
This will be used in a follow up patch to properly release shared DPLLs
without relying on the shared_dpll field in pipe_config.
v2: Fix white space error (Ville)
Use hweight32() (Ville)
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +--
drivers/g
Use the infrastructure added in a previous patch to choose shared DPLLs
and calculate clocks before touching the hardware.
v2: Don't set mode_set hooks since dev_priv is kzalloc()'d (Ville)
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 8 +++-
1 file
There's no users left after the conversion to calculate clocks before
disabling crtcs during mode set.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 3 ---
drivers/gpu/drm/i915/intel_display.c | 7 ---
2 files changed, 10 deletions(-)
diff --git a/dr
Version 2 of the series with the comments I got so far resolved.
Ander Conselvan de Oliveira (9):
drm/i915: Make *_crtc_mode_set work on new_config
drm/i915: Convert shared dpll reference count to a crtc mask
drm/i915: Move dpll crtc_mask and hw_state fields into separate struct
drm/i915:
This shouldn't change the behavior of those functions, since they are
called after the new_config is made effective and that points to the
current config. In a follow up patch, the mode set sequence will be
changed so this is called before disabling crtcs, and in that case
those functions should wo
I've forgotten to do this in:
commit cb597bb3a2fbfc871cc1c703fb330d247bd21394
Author: Daniel Vetter
Date: Sun Jul 27 19:09:33 2014 +0200
drm: trylock modest locking for fbdev panics
Oops, fix this asap.
In my defense kerneldoc is really awful and there's no way it can pick
up structured
While writing atomic docs I've noticed that I don't get any errors
for my screw-ups in drm_crtc.h. Fix this immediately.
This just does the bare minimum to get starts, lots of stuff isn't
properly documented yet unfortunately.
Signed-off-by: Daniel Vetter
---
Documentation/DocBook/drm.tmpl | 4
I've tried to cc all the people who have recently added new stuff
but forgotten to update documentation.
I've also decided not to bother documenting the massive property list
in struct drm_mode_config. If that beast keeps on growing we might want
to extract it into a separate structure which we wo
Just a bit of OCD cleanup on headers - this function isn't the core
interface any more but just a helper for drivers who haven't yet
transitioned to universal planes. Put the declaration at the right
spot and sprinkle necessary #includes over all drivers.
Maybe this helps to encourage driver maint
On Wed, 29 Oct 2014, Ville Syrjälä wrote:
> On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
>> On Wed, 29 Oct 2014, Ville Syrjälä wrote:
>> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
>> >> From: Dave Airlie
>> >>
>> >> Ivybridge + 30" monitor prints a drm error
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB
doesn't support DP3 we should even bother trying to use it.
This regression has been introduced in
commit 06ea66b6bb445043dc25a9626254d5c130093199
Author: Todd Previte
Date: Mon Jan 20 10:19:39 2014 -0700
drm/i915: Ena
hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
-
For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
to be sent to both Ports during MIPI encoder enabling sequence.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
Signed
For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h|
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.
v2: Commit message added to all patches. All review comments of Jani, Nikula
have been addressed in t
All macros of MIPI regs now uses port no instead of pipe no.Based on the
pipe, port no is determined and used to read or write MIPI regs during
enabling & disbling MIPI encoder.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c | 133 ++
driv
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_pll.c |9 ++---
1 file chan
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.
v2 : Address review comments by Jani
- Removed the bit mask used for ->dual_link
- Used DSI instead of MIPI
We need to program both port registers during dual link enable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 255 ++
hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
-
We need to program both port registers during dual link disable path.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 68 +++--
_PORT macro to be used instead of _TRANSCODER macro for all MIPI DSI regs.
New macro added for mapping the pipe to MIPI Ports.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h |4 ++
drivers/gpu/drm/i915/i915_reg.h | 98 +++
2 files cha
For dual link MIPI Panels, few packets needs to be sent to Port A or
Port C or both. Based on the port no from MIPI Sequence Block#53, these
sequences needs to be sent accordingly.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.h |1 +
This patch is in preparation for the DSI dual link
port enable and disable related changes.
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 43 --
1 file changed, 32 insertions(+), 11 deletions(-)
diff --gi
On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
> On Wed, 29 Oct 2014, Ville Syrjälä wrote:
> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> >> From: Dave Airlie
> >>
> >> Ivybridge + 30" monitor prints a drm error on every modeset, since
> >> IVB doesn't support D
On Tue, 28 Oct 2014, jens stein wrote:
> commit c675949ec58ca50d5a3ae3c757892f1560f6e896
> drm/i915: do not setup backlight if not available according to VBT
>
> prevents backlight setup on Macbook 2,1. Apply quirk to ignore the VBT
> check so backlight is set up properly.
>
> Signed-off-by: J
On Wed, 29 Oct 2014, Ville Syrjälä wrote:
> On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> Ivybridge + 30" monitor prints a drm error on every modeset, since
>> IVB doesn't support DP3 we should even bother trying to use it.
>>
>> Reviewed-by: Daniel Vet
On Wed, Oct 29, 2014 at 10:15:01AM +0200, Ville Syrjälä wrote:
> On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > Ivybridge + 30" monitor prints a drm error on every modeset, since
> > IVB doesn't support DP3 we should even bother trying to use it.
> >
>
On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> Ivybridge + 30" monitor prints a drm error on every modeset, since
> IVB doesn't support DP3 we should even bother trying to use it.
>
> Reviewed-by: Daniel Vetter (on irc)
> Signed-off-by: Dave Airlie
> ---
>
On Tue, Oct 28, 2014 at 04:56:03PM +, Daniel Stone wrote:
> Hi,
>
> On 17 October 2014 01:36, Jiang, Fei wrote:
>
> > Thanks for Emil's suggestion. You are right, we need make sure structure
> > size aligned on 8 bytes, which is important for 32bit-64bit compatible case.
>
>
> While you're
On Tue, Oct 28, 2014 at 05:06:01PM +0200, Jani Nikula wrote:
> On Tue, 28 Oct 2014, Johan Hovold wrote:
> > Hi,
> >
> > I have had some problems with crashes involving suspend-to-disk after
> > updating to v3.16.
> >
> > Below is a log with 3.16.6 from a failed suspend attempt after which I
> > g
On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> Ivybridge + 30" monitor prints a drm error on every modeset, since
> IVB doesn't support DP3 we should even bother trying to use it.
>
> Reviewed-by: Daniel Vetter (on irc)
> Signed-off-by: Dave Airlie
This r
Hi Daniel, we’ve resolved this in patch v2.
From: Daniel Stone [mailto:dan...@fooishbar.org]
Sent: Wednesday, October 29, 2014 0:56
To: Jiang, Fei
Cc: Emil Velikov; Cheng, Yao; intel-gfx@lists.freedesktop.org; Vetter, Daniel;
dri-de...@lists.freedesktop.org
Subject: Re: [RFC PATCH 3/3] libdrm: us
From: Dave Airlie
Ivybridge + 30" monitor prints a drm error on every modeset, since
IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by: Daniel Vetter (on irc)
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1
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