[Intel-gfx] [PATCH] drm/i915: Prevent negative relocation deltas from wrapping

From: Chris Wilson This is pure evil. Userspace, I'm looking at you SNA, repacks batch buffers on the fly after generation as they are being passed to the kernel for execution. These batches also contain self-referenced relocations as a single buffer encompasses the state commands, kernels, verti

Re: [Intel-gfx] [PATCH 01/11] drm/dp_helper: add defines for DP 1.2 and MST support.

On Wednesday, May 21, 2014 11:55 AM, Dave Airlie wrote: > > From: Dave Airlie > > This just adds the defines from the DP 1.2 spec, which we > will use later. > > Signed-off-by: Dave Airlie I checked this patch by using DP 1.2 spec. These definitions are correct. Thank you. Reviewed-by: Jingo

Re: [Intel-gfx] [PATCH 03/11] drm/i915: add some registers need for displayport MST support.

Dave Airlie Tuesday, May 20, 2014 7:54 PM From: Dave Airlie These are just from the Haswell spec. Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/i915_reg.h | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i91

Re: [Intel-gfx] [PATCH 04/11] drm/crtc: add interface to reinitialise the legacy mode group

Dave Airlie Tuesday, May 20, 2014 7:54 PM From: Dave Airlie This can be called to update things after dynamic connectors/encoders are created/deleted. Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_crtc.c | 9 + include/drm/drm_crtc.h | 1 + 2 files chan

Re: [Intel-gfx] [PATCH 01/11] drm/dp_helper: add defines for DP 1.2 and MST support.

Dave Airlie Tuesday, May 20, 2014 7:54 PM From: Dave Airlie This just adds the defines from the DP 1.2 spec, which we will use later. Signed-off-by: Dave Airlie --- include/drm/drm_dp_helper.h | 78 + 1 file changed, 78

Re: [Intel-gfx] [PATCH 02/11] drm: add DP MST encoder type

Dave Airlie Tuesday, May 20, 2014 7:54 PM From: Dave Airlie This adds an encoder type for DP MST encoders. Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_crtc.c | 1 + include/uapi/drm/drm_mode.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add aspect ratio property for HDMI

Adding dri-devel.. On May-22-2014 4:50 PM, Kannan, Vandana wrote: > Create and attach the drm property to set aspect ratio. If there is no user > specified value, then PAR_NONE/Automatic option is set by default. User can > select aspect ratio 4:3 or 16:9. The aspect ratio selected by user would >

[Intel-gfx] [I-G-T][PATCH] Add panning test for primary plane.

Get CRCs of a full red and a full blue surface as reference. Create a big framebuffer that is twice width and twice height as the current display mode. Fill the top left quarter with red, bottom right quarter with blue Check the scanned out image with the CRTC at position (0, 0) of the framebuffe

Re: [Intel-gfx] [PATCH 47/66] drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable

On Thu, May 22, 2014 at 05:38:13PM -0300, Paulo Zanoni wrote: > 2014-04-24 18:55 GMT-03:00 Daniel Vetter : > > With this all the pch pre-enable work has been moved into the special > > hsw crt encoder functions. > > For the same reasons I gave in the other patches, I'm not convinced > this is an i

Re: [Intel-gfx] [PATCH 46/66] drm/i915: Move hsw_fdi_link_train into intel_crt.c

On Thu, May 22, 2014 at 05:28:05PM -0300, Paulo Zanoni wrote: > 2014-04-24 18:55 GMT-03:00 Daniel Vetter : > > The pch encoder case really isn't anything generic on hsw: > > - It's for the vga port only and > > - the vga port does only exist on some hsw platforms. > > > > Imo it helps the generic c

Re: [Intel-gfx] [PATCH 0/6] Execlists prep-work

On Thu, May 22, 2014 at 02:13:32PM +0100, oscar.ma...@intel.com wrote: > From: Oscar Mateo > > These patches contain refactoring and preparatory work for Execlists [1]. > > [1http://lists.freedesktop.org/archives/intel-gfx/2014-May/044847.html] > http://lists.freedesktop.org/archives/intel-gfx/2

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Split the ringbuffers from the rings (3/3)

On Thu, May 22, 2014 at 11:37:50PM +0200, Daniel Vetter wrote: > On Thu, May 22, 2014 at 02:13:36PM +0100, oscar.ma...@intel.com wrote: > > From: Oscar Mateo > > > > Manual cleanup after the previous Coccinelle script. > > > > Yes, I could write another Coccinelle script to do this but I > > don

Re: [Intel-gfx] [PATCH 5/6] drm/i915: s/i915_hw_context/intel_context

On Thu, May 22, 2014 at 02:13:37PM +0100, oscar.ma...@intel.com wrote: > From: Oscar Mateo > > Up until now, contexts had one (and only one) backing object that was > used by the hardware to save/restore render ring contexts (via the > MI_SET_CONTEXT command). Other rings did not have or need thi

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Split the ringbuffers from the rings (3/3)

On Thu, May 22, 2014 at 02:13:36PM +0100, oscar.ma...@intel.com wrote: > From: Oscar Mateo > > Manual cleanup after the previous Coccinelle script. > > Yes, I could write another Coccinelle script to do this but I > don't want labor-replacing robots making an honest programmer's > work obsolete

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Split the ringbuffers from the rings (2/3)

On Thu, May 22, 2014 at 02:13:35PM +0100, oscar.ma...@intel.com wrote: > From: Oscar Mateo > > This refactoring has been performed using the following Coccinelle > semantic script: > > @@ > struct intel_engine_cs r; > @@ > ( > - (r).obj > + r.buffer->obj > | > - (

[Intel-gfx] [PATCH 6/6] drm/i915: Switch to unified plane cursor handling (v4)

The DRM core will translate calls to legacy cursor ioctls into universal cursor calls automatically, so there's no need to maintain the legacy cursor support. This greatly simplifies the transition since we don't have to handle reference counting differently depending on which cursor interface was

[Intel-gfx] [PATCH] drm/i915: Unexport intel_ddi_connector_get_hw_state

The connector->get_hw_state function is actually platform dependent. So move it out of the shared connector init functions. This allows us to drop another intel_ddi.c export. v2: Fix segfaults when the dp connector fails to initialize (e.g. due there not being a panel). Spotted by Paulo. Cc: Paul

Re: [Intel-gfx] [PATCH 47/66] drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > With this all the pch pre-enable work has been moved into the special > hsw crt encoder functions. For the same reasons I gave in the other patches, I'm not convinced this is an improvement to our code. It looks like we're just breaking the abstraction

Re: [Intel-gfx] [PATCH 44/66] drm/i915: Pass port explicitly to intel_ddi_get_hw_state

On Thu, May 22, 2014 at 04:38:07PM -0300, Paulo Zanoni wrote: > 2014-04-24 18:55 GMT-03:00 Daniel Vetter : > > Well, the newly created intel_ddi_get_port_state. > > > > In general intel_ddi.c has way too intimate knowledge with everyone > > else as exemplified with all the encoder/connector noodlin

Re: [Intel-gfx] [PATCH 46/66] drm/i915: Move hsw_fdi_link_train into intel_crt.c

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > The pch encoder case really isn't anything generic on hsw: > - It's for the vga port only and > - the vga port does only exist on some hsw platforms. > > Imo it helps the generic code flow a lot if we shovel all this into > hsw specific enable/disable ho

Re: [Intel-gfx] [PATCH 43/66] drm/i915: Disable pipe before ports on ilk

On Thu, May 22, 2014 at 04:25:05PM -0300, Paulo Zanoni wrote: > 2014-04-24 18:55 GMT-03:00 Daniel Vetter : > > The modeset sequence docs are very clear that we should disable the > > pipe before we switch off any ports, for both pch ports and the cpu > > edp port. > > > > In practice it doesn't see

Re: [Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Move igt_pipe_crc_{new, free} to init

On Thu, May 22, 2014 at 08:12:58PM +0300, Ville Syrjälä wrote: > On Thu, May 22, 2014 at 10:06:37AM -0700, Matt Roper wrote: > > On Thu, May 22, 2014 at 08:01:09PM +0300, Ville Syrjälä wrote: > > > On Thu, May 22, 2014 at 09:47:39AM -0700, Matt Roper wrote: > > > > If a subtest fails, cleanup_crtc(

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Kill intel_crtc->vbl_wait

On Thu, May 22, 2014 at 08:30:23PM +0100, Chris Wilson wrote: > On Thu, May 22, 2014 at 06:05:34PM +0200, Daniel Vetter wrote: > > On Thu, May 22, 2014 at 04:49:03PM +0100, Chris Wilson wrote: > > > On Thu, May 22, 2014 at 06:39:33PM +0300, ville.syrj...@linux.intel.com > > > wrote: > > > > From:

[Intel-gfx] [PATCH 2/2] drm/i915: Extract gen8_gt_irq_reset

Fallout from an intermediate patch revision that I deemed worth saving. Cc: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 1/2] drm/i915: Improve irq handling after gpu resets

Currently we do a full re-init of all interrupts after a gpu hang. Which is pretty bad since we don't restore the interrupts we've enabled at runtime correctly. Even with that addressed it's rather horribly race. But on g4x and later we only reset the gt and not the entire gpu. Which means we only

[Intel-gfx] Screen extremely dim on Dell Latitude D630 after upgrading to Linux kernel-3.14

After upgrading to linux Kernel-3.14, the screen on my Dell Latitude D630 was nearly unreadably dim. When I Boot the 3.13 kernel, my screen is bright. I opened a Bug here: https://bugzilla.redhat.com/show_bug.cgi?id=1094066 and others have chimed in that they have the same problem. I bisect

Re: [Intel-gfx] [PATCH 45/66] drm/i915: Unexport intel_ddi_connector_get_hw_state

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > The connector->get_hw_state function is actually platform dependent. > So move it out of the shared connector init functions. This allows us > to drop another intel_ddi.c export. > > Signed-off-by: Daniel Vetter The nice thing about the current code is

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Improve irq handling after gpu resets

On Thu, May 22, 2014 at 07:51:45PM +0300, Ville Syrjälä wrote: > On Thu, May 22, 2014 at 05:56:35PM +0200, Daniel Vetter wrote: > > Currently we do a full re-init of all interrupts after a gpu hang. > > Which is pretty bad since we don't restore the interrupts we've > > enabled at runtime correctly

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Fix up fifo underrun tracking, take N

On Thu, May 22, 2014 at 07:55:52PM +0300, Ville Syrjälä wrote: > On Thu, May 22, 2014 at 05:56:32PM +0200, Daniel Vetter wrote: > > So apparently this is tricky. > > > > We need to consider: > > - We start out with all the hw enabling bits disabled, both the > > individual fifo underrun interrup

Re: [Intel-gfx] [PATCH 39/66] drm/i915: Check hw state in assert_can_disable_lcpll

On Thu, May 22, 2014 at 9:26 PM, Daniel Vetter wrote: > On Thu, May 22, 2014 at 03:10:37PM -0300, Paulo Zanoni wrote: >> 2014-04-24 18:55 GMT-03:00 Daniel Vetter : >> > All the other checks also check hw state, so checking our software >> > refcounts for the plls looks a bit odd. >> >> As I mentio

Re: [Intel-gfx] [alsa-devel] [RFC] set up an sync channel between audio and display driver (i.e. ALSA and DRM)

On Thu, May 22, 2014 at 02:59:56PM +, Lin, Mengdong wrote: > > -Original Message- > > From: Vetter, Daniel > > Sent: Tuesday, May 20, 2014 11:08 PM > > > > On 20/05/2014 16:57, Thierry Reding wrote: > > > On Tue, May 20, 2014 at 04:45:56PM +0200, Daniel Vetter wrote: > > >> >On Tue, Ma

Re: [Intel-gfx] [PATCH 1/2] drm/i915: fix possible RPM ref leaking during RPS disabling

On Thu, May 22, 2014 at 01:56:17PM +0100, Robert Beckett wrote: > On 13/05/2014 14:54, Daniel Vetter wrote: > >On Tue, May 13, 2014 at 04:46:10PM +0300, Imre Deak wrote: > >>On Mon, 2014-05-12 at 19:51 +0200, Daniel Vetter wrote: > >>>On Mon, May 12, 2014 at 06:35:04PM +0300, Imre Deak wrote: > >>>

Re: [Intel-gfx] [PATCH 40/66] drm/i915: Remove spll_refcount for hsw

On Thu, May 22, 2014 at 03:41:25PM -0300, Paulo Zanoni wrote: > 2014-04-24 18:55 GMT-03:00 Daniel Vetter : > > SPLL would be a reference clock we could potentially share, > > especially if we want to use the SSC mode. But currently we > > don't, so let's rip out this complexity for a simpler conver

Re: [Intel-gfx] [PATCH 44/66] drm/i915: Pass port explicitly to intel_ddi_get_hw_state

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > Well, the newly created intel_ddi_get_port_state. > > In general intel_ddi.c has way too intimate knowledge with everyone > else as exemplified with all the encoder/connector noodling and the > massive exported function list. > > As a first step explictl

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Kill intel_crtc->vbl_wait

On Thu, May 22, 2014 at 06:05:34PM +0200, Daniel Vetter wrote: > On Thu, May 22, 2014 at 04:49:03PM +0100, Chris Wilson wrote: > > On Thu, May 22, 2014 at 06:39:33PM +0300, ville.syrj...@linux.intel.com > > wrote: > > > From: Ville Syrjälä > > > > > > Share the waitqueue that drm_irq uses when p

Re: [Intel-gfx] [PATCH 39/66] drm/i915: Check hw state in assert_can_disable_lcpll

On Thu, May 22, 2014 at 03:10:37PM -0300, Paulo Zanoni wrote: > 2014-04-24 18:55 GMT-03:00 Daniel Vetter : > > All the other checks also check hw state, so checking our software > > refcounts for the plls looks a bit odd. > > As I mentioned before, this contradicts your own previous review of > th

Re: [Intel-gfx] [PATCH 43/66] drm/i915: Disable pipe before ports on ilk

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > The modeset sequence docs are very clear that we should disable the > pipe before we switch off any ports, for both pch ports and the cpu > edp port. > > In practice it doesn't seem to matter too much since for non-DP pch > ports it only matters that the

Re: [Intel-gfx] [PATCH 40/66] drm/i915: Remove spll_refcount for hsw

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > SPLL would be a reference clock we could potentially share, > especially if we want to use the SSC mode. But currently we > don't, so let's rip out this complexity for a simpler conversion > to the new display pll framework. I'm really not a fan of this

Re: [Intel-gfx] [PATCH 42/66] drm/i915: Make intel_wait_for_pipe_off static

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > Noticed while reading around. That's because you killed the intel_tv.c caller in patch 06/66. Reviewed-by: Paulo Zanoni > > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > drivers/gpu/drm/i915/intel_drv.h | 1

Re: [Intel-gfx] [PATCH 41/66] drm/i915: Clean up WRPLL/SPLL #defines

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > Luckily the bit definitions match, but it's still confusing > to use one when handling the other. So sprinkle some OCD over > the #defines to make them match and use the right version in > each place. > > Maybe we should unify these definitions completel

Re: [Intel-gfx] [PATCH 39/66] drm/i915: Check hw state in assert_can_disable_lcpll

2014-04-24 18:55 GMT-03:00 Daniel Vetter : > All the other checks also check hw state, so checking our software > refcounts for the plls looks a bit odd. As I mentioned before, this contradicts your own previous review of the patch that added this code. In addition, you said many times that we sho

Re: [Intel-gfx] [PATCH 01/11] drm/i915: move psr_setup_done to psr struct

2014-05-15 21:13 GMT-03:00 Rodrigo Vivi : > v2: Avoid more than one setup. Removing initialization > and trusting allocation. (By Paulo Zanoni). > v3: rebase. > > Cc: Paulo Zanoni > Signed-off-by: Rodrigo Vivi I guess the commit message needs a little explanation, such as: "Because our driv

[Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Combine data_t and test_data_t

If a subtest fails, cleanup_crtc() never gets called and then the test_data_t structure for the test is lost, including the CRC file descriptor that we never got a chance to release; this causes all subsequent tests to fail with -EBUSY at igt_pipe_crc_new(). The split between permanent data_t and

Re: [Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Move igt_pipe_crc_{new, free} to init

On Thu, May 22, 2014 at 10:06:37AM -0700, Matt Roper wrote: > On Thu, May 22, 2014 at 08:01:09PM +0300, Ville Syrjälä wrote: > > On Thu, May 22, 2014 at 09:47:39AM -0700, Matt Roper wrote: > > > If a subtest fails, cleanup_crtc() never gets called. Currently that > > > also causes igt_pipe_crc_fre

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Improve irq handling after gpu resets

On Thu, May 22, 2014 at 07:51:45PM +0300, Ville Syrjälä wrote: > On Thu, May 22, 2014 at 05:56:35PM +0200, Daniel Vetter wrote: > > Currently we do a full re-init of all interrupts after a gpu hang. > > Which is pretty bad since we don't restore the interrupts we've > > enabled at runtime correctly

Re: [Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Move igt_pipe_crc_{new, free} to init

On Thu, May 22, 2014 at 08:01:09PM +0300, Ville Syrjälä wrote: > On Thu, May 22, 2014 at 09:47:39AM -0700, Matt Roper wrote: > > If a subtest fails, cleanup_crtc() never gets called. Currently that > > also causes igt_pipe_crc_free() to never be called, leading all > > subsequent subtests to also

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add fifo underrun reporting state to debugfs

On Thu, May 22, 2014 at 05:56:31PM +0200, Daniel Vetter wrote: > On platforms with shared interrupt enable bits (which are shared even > with the pipe CRC logic) there's some tricky corner cases. Add > information to make debugging those easier. > > Signed-off-by: Daniel Vetter For patches 1,3,4

Re: [Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Move igt_pipe_crc_{new, free} to init

On Thu, May 22, 2014 at 09:47:39AM -0700, Matt Roper wrote: > If a subtest fails, cleanup_crtc() never gets called. Currently that > also causes igt_pipe_crc_free() to never be called, leading all > subsequent subtests to also fail with -EBUSY at igt_pipe_crc_new(). > Move the calls to igt_pipe_cr

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Fix up fifo underrun tracking, take N

On Thu, May 22, 2014 at 05:56:32PM +0200, Daniel Vetter wrote: > So apparently this is tricky. > > We need to consider: > - We start out with all the hw enabling bits disabled, both the > individual fifo underrun interrupts and the shared display error > interrupts masked. Otherwise if the bio

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Improve irq handling after gpu resets

On Thu, May 22, 2014 at 05:56:35PM +0200, Daniel Vetter wrote: > Currently we do a full re-init of all interrupts after a gpu hang. > Which is pretty bad since we don't restore the interrupts we've > enabled at runtime correctly. Even with that addressed it's rather > horribly race. > > But on g4x

[Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Move igt_pipe_crc_{new, free} to init

If a subtest fails, cleanup_crtc() never gets called. Currently that also causes igt_pipe_crc_free() to never be called, leading all subsequent subtests to also fail with -EBUSY at igt_pipe_crc_new(). Move the calls to igt_pipe_crc_{new,free} into igt_main so that we don't need to worry about clos

[Intel-gfx] [PATCH v2 1/2] drm: Add drm_crtc_vblank_waitqueue()

From: Ville Syrjälä Add a small static inline helper to grab the vblank wait queue based on the drm_crtc. This is useful for drivers to do internal vblank waits using wait_event() & co. v2: Pimp commit message (Daniel) Add kernel doc (Daniel) Suggested-by: Daniel Vetter Signed-off-by: Vil

Re: [Intel-gfx] [PATCH 1/2] drm: Add drm_crtc_vblank_waitqueue()

On Thu, May 22, 2014 at 06:39:32PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Add a small static inline helper to grab the vblank wait queue based on > the drm_crtc. Maybe add that this is useful for drivers to do internal vblank waits using wait event. > Suggested-by

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Kill intel_crtc->vbl_wait

On Thu, May 22, 2014 at 04:49:03PM +0100, Chris Wilson wrote: > On Thu, May 22, 2014 at 06:39:33PM +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Share the waitqueue that drm_irq uses when performing the vblank evade > > trick for atomic pipe updates. > > > > Suggest

Re: [Intel-gfx] linux-next: manual merge of the dma-buf tree with the drm-intel tree

On 20 May 2014 12:25, Stephen Rothwell wrote: > Hi Sumit, > > Today's linux-next merge of the dma-buf tree got a conflict in > drivers/gpu/drm/i915/i915_gem_dmabuf.c between commit 5cc9ed4b9a7a > ("drm/i915: Introduce mapping of user pages into video memory (userptr) > ioctl") from the drm-intel t

[Intel-gfx] [PATCH v2 2/2] drm/i915: Kill intel_crtc->vbl_wait

From: Ville Syrjälä Share the waitqueue that drm_irq uses when performing the vblank evade trick for atomic pipe updates. v2: Keep intel_pipe_handle_vblank() (Chris) Suggested-by: Daniel Vetter Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 5 - drivers/gpu/drm/i

[Intel-gfx] [PATCH 5/5] drm/i915: Improve irq handling after gpu resets

Currently we do a full re-init of all interrupts after a gpu hang. Which is pretty bad since we don't restore the interrupts we've enabled at runtime correctly. Even with that addressed it's rather horribly race. But on g4x and later we only reset the gt and not the entire gpu. Which means we only

[Intel-gfx] [PATCH 4/5] drm/i915: Inline ilk/gen8_irq_reset

No point in having this indirection. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 4d44f09eb833..3cd659b47dd2 100644 ---

[Intel-gfx] [PATCH 3/5] drm/i915: Disable gpu reset on i965g/gm

Ville figured out that it needs a full display reset since apparently a lot more goes down than just the GT. Until that's address it's better to just diable gpu reset. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_uncore.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/driv

[Intel-gfx] [PATCH 2/5] drm/i915: Fix up fifo underrun tracking, take N

So apparently this is tricky. We need to consider: - We start out with all the hw enabling bits disabled, both the individual fifo underrun interrupts and the shared display error interrupts masked. Otherwise if the bios config is broken we'll blow up with a NULL deref in our interrupt handl

[Intel-gfx] [PATCH 1/5] drm/i915: Add fifo underrun reporting state to debugfs

On platforms with shared interrupt enable bits (which are shared even with the pipe CRC logic) there's some tricky corner cases. Add information to make debugging those easier. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 4 1 file changed, 4 insertions(+) diff --

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Kill intel_crtc->vbl_wait

On Thu, May 22, 2014 at 06:39:33PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Share the waitqueue that drm_irq uses when performing the vblank evade > trick for atomic pipe updates. > > Suggested-by: Daniel Vetter > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/d

[Intel-gfx] [RFC][PATCH] drm/i915: Don't promote UC to WT automagically

From: Ville Syrjälä If the object is already UC leave it as UC instead of automagically promoting it to WT in i915_gem_object_pin_to_display_plane() when the hardware is WT capable. Supposedly the user wanted UC for a reason, so let's respect that. Signed-off-by: Ville Syrjälä --- Just somethi

Re: [Intel-gfx] [PATCH] drm/i915: Hold CRTC lock whilst freezing the planes

On Thu, 22 May 2014 09:44:40 +0100 Chris Wilson wrote: > Daniel keeps on ramping up the warning level of the DRM and our display > core to make it complain whenever the locking rules are not followed. > This caught > > commit 24576d23976746cb52e7700c4cadbf4bc1bc3472 > Author: Jesse Barnes > Dat

Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset at boot and resume v3

On Thu, 22 May 2014 09:51:22 +0300 Imre Deak wrote: > On Wed, 2014-05-21 at 21:43 +0300, Ville Syrjälä wrote: > > On Wed, May 21, 2014 at 11:11:15AM -0700, Jesse Barnes wrote: > > > And to answer more specifically... > > > > > > On Wed, 21 May 2014 20:54:03 +0300 > > > Ville Syrjälä wrote: > >

[Intel-gfx] [PATCH 1/2] tests/kms_pipe_crc_basic: Add suspend tests

Currently broken ... Signed-off-by: Daniel Vetter --- tests/kms_pipe_crc_basic.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pipe_crc_basic.c index 282c7f68150a..eedb3f399e45 100644 --- a/tests/kms_pipe_crc_basic.c +++ b/tests/kms_pipe_crc_ba

[Intel-gfx] [PATCH 2/2] tests/kms_pipe_crc_basic: Add gpu hang tests

Currently pipe CRC support is broken after gpu hangs. This tests for this bug. Signed-off-by: Daniel Vetter --- tests/kms_pipe_crc_basic.c | 60 -- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pi

[Intel-gfx] [PATCH 1/2] drm: Add drm_crtc_vblank_waitqueue()

From: Ville Syrjälä Add a small static inline helper to grab the vblank wait queue based on the drm_crtc. Suggested-by: Daniel Vetter Signed-off-by: Ville Syrjälä --- include/drm/drmP.h | 4 1 file changed, 4 insertions(+) diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 76cca

[Intel-gfx] [PATCH 2/2] drm/i915: Kill intel_crtc->vbl_wait

From: Ville Syrjälä Share the waitqueue that drm_irq uses when performing the vblank evade trick for atomic pipe updates. Suggested-by: Daniel Vetter Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 25 ++--- drivers/gpu/drm/i915/intel_display.c | 2

Re: [Intel-gfx] [alsa-devel] [RFC] set up an sync channel between audio and display driver (i.e. ALSA and DRM)

> -Original Message- > From: Vetter, Daniel > Sent: Tuesday, May 20, 2014 11:08 PM > > On 20/05/2014 16:57, Thierry Reding wrote: > > On Tue, May 20, 2014 at 04:45:56PM +0200, Daniel Vetter wrote: > >> >On Tue, May 20, 2014 at 4:29 PM, Imre Deak > wrote: > >>> > >On Tue, 2014-05-20 at 05:5

[Intel-gfx] [PATCH 14/16] drm/i915: Prefer the 5/6 DDB split when primary is disabled

From: Ville Syrjälä When the primary plane is disabled, pick the 5/6 DDB split to give the sprite as much FIFO space as possible. The normal heuristic of just looking at the highest valid WM level won't necessarily pick the optimal split since both splits might have the same number of levels ena

[Intel-gfx] [PATCH 16/16] drm/i915: Don't disable LP1+ watermarks for every frame when scaled

From: Ville Syrjälä If we mark the LP1+ watermarks as disabled every time sprite scaling is enabled, we end doing pointless work applying watermarks even though nothing has changed. This is an artifact of the way dev_priv->wm.lp_disabled affects the operation of ilk_setup_pending_watermarks(). If

[Intel-gfx] [PATCH 15/16] drm/i915: Add a workaround for sprite only <-> primary only switching

From: Ville Syrjälä ILK and IVB don't like switching between sprite only and primary only configurations when LP1+ watermarks have been enabled in the recent past. Like WaCxSRDisabledForSpriteScaling we can avoid the flash by disabling LP1+ watermarks for one frame before the critical plane recon

[Intel-gfx] [PATCH v2 13/16] drm/i915: Keep track of who disabled LP1+ watermarks

From: Ville Syrjälä Currently ilk_disable_lp_wm() just disabled LP1+ watermarks directly. However there's nothing preventing someone else from re-enabling them immediately. To make sure sure LP1+ watermarks stay disabled for the intended period, keep track which pipes require the LP1+ watermarks

[Intel-gfx] [PATCH 12/16] drm/i915: Disable LP1+ watermarks while changing the number of active pipes

From: Ville Syrjälä When we switch between one active pipe and multiple active pipes, the display FIFO gets repartitioned. Disable the LP1+ waterwarks while that is happening to make sure we don't get any glitches on other active pipes while doing a modeset on another other pipe. Signed-off-by:

[Intel-gfx] [PATCH 11/16] drm/i915: Refactor get_other_active_crtc()

From: Ville Syrjälä Pull the code to locate the other active crtc out from haswell_mode_set_planes_workaround() into a separate function. This will have another use later. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 33 + 1 file chang

[Intel-gfx] [PATCH v2 10/16] drm/i915: Wait for watermark updates to finish before disabling a pipe

From: Ville Syrjälä After we've disabled the planes, it seems like a good idea wait for the vblank driven watermark updates to finish before we turn off the vblank interrupts and eventually the entire pipe. v2: Rebase and s/intel_crtc/crtc/ Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH v2 09/16] drm/i915: Actually perform the watermark update in two phases

From: Ville Syrjälä Switch the code over to using the two phase watermark update. The steps generally follow this pattern: 1. Calculate new plane parameters for changed planes 2. Calculate new target and intermediate watermarks 3. Check that both the target and intermediate watermarks are valid

[Intel-gfx] [PATCH 06/16] drm/i915: Add dev_priv->wm.mutex

From: Ville Syrjälä Add a mutex to protect most of the watermark state. Will be useful when we start to update watermarks asynchronously from plane updates, or when we get finer grained locking for planes. Reviewed-by: Paulo Zanoni Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_dr

[Intel-gfx] [PATCH v2 08/16] drm/i915: Split watermark programming into pre and post steps

From: Ville Syrjälä We need to perform watermark programming before and after changing the plane configuration. Add two new vfuncs to do that. The pre phase is supposed to switch over to the intermediate watermarks which are computed so that they can deal with both the old and new plane configura

[Intel-gfx] [PATCH v2 07/16] drm/i915: Add vblank based delayed watermark update mechanism

From: Ville Syrjälä Add a mechanism by which you can queue up watermark update to happen after the vblank counter has reached a certain value. The vblank interrupt handler will schedule a work which will do the actual watermark programming in process context. v2: Rebase and s/intel_crtc/crtc/ S

[Intel-gfx] [PATCH v2 05/16] drm/i915: Refactor ilk_update_wm

From: Ville Syrjälä Split ilk_update_wm() into two parts; one doing the programming and the other the calculations. v2: Fix typo in commit message Reviewed-by: Paulo Zanoni Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 38 ++ 1 file ch

[Intel-gfx] [PATCH v2 01/16] drm/i915: Keep vblank interrupts enabled while enabling/disabling planes

From: Ville Syrjälä Because of the upcoming vblank interrupt driven watermark update mechanism we will have use for vblank interrupts during plane enabling/disabling. So don't call drm_vblank_off() until planes are off, and call drm_vblank_on() just before we start to enable the planes. v2: Pimp

[Intel-gfx] [PATCH 04/16] drm/i915: Refactor ilk_validate_pipe_wm()

From: Ville Syrjälä Pull the LP0 validate out from intel_compute_pipe_wm() into a separate function. We will have further need for such a function to validate both the final watermarks and the intermediate watermarks we will be using while the plane(s) transition between different configurations.

[Intel-gfx] [PATCH 03/16] drm/i915: Check hw vs. sw watermark state after programming

From: Ville Syrjälä Make sure we programmed the watermarks correctly, by reading out the hardware state again after programming and comparing it with the state we supposedly programmed into hardware. Dump the watermark registers after a mismatch, very much like we for the pipe config. The only di

[Intel-gfx] [PATCH 02/16] drm/i915: Leave interrupts enabled while disabling crtcs during suspend

From: Ville Syrjälä The new watermaek update mechanism requires interrupts to work correctly. Because of this we need interrupts while disabling crtcs during suspend. So move the irq disable to happen a bit later. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.c | 3 ++- 1 file

[Intel-gfx] [PATCH v2 00/16] drm/i915: Two part watermark update for ILK+, part 2

From: Ville Syrjälä Here's a rebased and slightly polished version of the two part watermark update series. Several patches already got merged, so we're down to 16 now. Also the drm vblank series got merged as did the atomic sprite series, so there's nothing else blocking this stuff anymore. Pr

[Intel-gfx] [PATCH 3/3] drm/i915: Fix mmio page flip vs mmio set base race

From: Sourab Gupta This patch fixes the race condition between flip done interrupt from set base and mmio based page flip. This patch is dependent on http://lists.freedesktop.org/archives/intel-gfx/2014-April/043761.html Also, for the details of the race condition please refer to the mentioned

[Intel-gfx] [PATCH 2/3] drm/i915: Default to mmio flips on VLV

From: Sourab Gupta This patch is for using mmio flips by default on VLV. The module parameter controlling use of MMIO flips allows us to control the default behaviour, which is set true for VLV and false elsewhere. Signed-off-by: Sourab Gupta --- drivers/gpu/drm/i915/i915_params.c | 5 +++--

[Intel-gfx] [PATCH v7 1/3] drm/i915: Replaced Blitter ring based flips with MMIO flips

From: Sourab Gupta Using MMIO based flips on Gen5+. The MMIO flips are useful for the Media power well residency optimization. These maybe enabled on architectures where Render and Blitter engines reside in different power wells. The blitter ring is currently being used just for command streamer

[Intel-gfx] [PATCH v2 0/3] Replace Blitter ring based flips with MMIO flips

From: Sourab Gupta This patch series replaces Blitter ring based flips with MMIO based flips. This is useful for Media power well residency optimization. These may be enabled on architectures where Render and Blitter engines reside in different power wells. The blitter ring is currently being use

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk

On Tue, May 20, 2014 at 11:46:45AM -0700, Jesse Barnes wrote: > On Mon, 19 May 2014 19:23:27 +0300 > ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä > > > > Apparently we need to disable VCP unit clock gating around media reset > > on g4x. > > > > Signed-off-by: Ville Syrjälä >

Re: [Intel-gfx] [RFC] set up an sync channel between audio and display driver (i.e. ALSA and DRM)

> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Imre Deak > Sent: Thursday, May 22, 2014 1:08 AM > > On Wed, 2014-05-21 at 18:05 +0200, Daniel Vetter wrote: > > On Wed, May 21, 2014 at 5:56 PM, Babu, Ramesh > wrote: > > >> On Tue, May

Re: [Intel-gfx] [PATCH v3] drm/i915: Add null state batch to active list

"Volkin, Bradley D" writes: > On Wed, May 21, 2014 at 07:02:56AM -0700, Mika Kuoppala wrote: >> +if (ring->id == RCS && !to->is_initialized && from == NULL) { >> +ret = i915_gem_render_state_init(ring); >> +if (ret) >> +DRM_ERROR("init render state:

Re: [Intel-gfx] [PATCH v8 3/9] drm/i915: Make sprite updates atomic

On Thu, May 22, 2014 at 03:03:56PM +0200, Daniel Vetter wrote: > On Tue, Apr 29, 2014 at 01:35:46PM +0300, ville.syrj...@linux.intel.com wrote: > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > > b/drivers/gpu/drm/i915/intel_drv.h > > index 96ae78d..d8b540b 100644 > > --- a/drivers/gpu/drm/i915/

[Intel-gfx] [PATCH 5/6] drm/i915: s/i915_hw_context/intel_context

From: Oscar Mateo Up until now, contexts had one (and only one) backing object that was used by the hardware to save/restore render ring contexts (via the MI_SET_CONTEXT command). Other rings did not have or need this, so our i915_hw_context struct had a 1:1 relationship with a a real HW context.

[Intel-gfx] [PATCH 4/6] drm/i915: Split the ringbuffers from the rings (3/3)

From: Oscar Mateo Manual cleanup after the previous Coccinelle script. Yes, I could write another Coccinelle script to do this but I don't want labor-replacing robots making an honest programmer's work obsolete (also, I'm lazy). Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_dma.c

[Intel-gfx] [PATCH 2/6] drm/i915: Split the ringbuffers from the rings (1/3)

From: Oscar Mateo As advanced by the previous patch, the ringbuffers and the engine command streamers belong in different structs. This is so because, while they used to be tightly coupled together, the new Logical Ring Contexts (LRC for short) have a ringbuffer each. In legacy code, we will use

[Intel-gfx] [PATCH 3/6] drm/i915: Split the ringbuffers from the rings (2/3)

From: Oscar Mateo This refactoring has been performed using the following Coccinelle semantic script: @@ struct intel_engine_cs r; @@ ( - (r).obj + r.buffer->obj | - (r).virtual_start + r.buffer->virtual_start | - (r).head + r.buffer->head |

[Intel-gfx] [PATCH 6/6] drm/i915: Kill private_default_ctx off

From: Oscar Mateo It's barely alive now anyway, so give it the "coup de grâce". Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_debugfs.c | 7 --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gem_context.c | 14 -- 3 files changed, 8 i

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