From: Yanzhang Wang
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf
when enabling -mno-omit-leaf-frame-pointer
(riscv_option_override): Override omit-frame-pointer.
(riscv_frame_pointer_required): Save s0 for non-leaf function
From: Yanzhang Wang
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
There're two exceptions,
- The vector_size attribute.
- The intrinsic functions.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Se
From: Yanzhang Wang
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
There're two exceptions,
- The vector_size attribute.
- The intrinsic functions.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Se
From: Yanzhang Wang
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
There're two exceptions,
- The vector_size attribute.
- The intrinsic functions.
Some cases that need to add -Wno-psabi to ignore the warning.
gcc/ChangeLog:
From: Yanzhang Wang
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf
when enabling -mno-omit-leaf-frame-pointer
(riscv_option_override): Override omit-frame-pointer.
(riscv_frame_pointer_required): Save s0 for non-leaf function
From: Yanzhang Wang
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf
when enabling -mno-omit-leaf-frame-pointer
(riscv_option_override): Override omit-frame-pointer.
(riscv_frame_pointer_required): Save s0 for non-leaf function
From: Yanzhang Wang
This patch will optimize the below mulh example,
vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) {
return __riscv_vmulh_vx_i32m1(v1, 0, vl);
}
from mulh pattern
vsetvli zero, a2, e32, m1, ta, ma
vmulh.vx v24, v24, zero
vs1r.vv24, 0(a0)
to belo
From: Yanzhang Wang
The pattern is enabled for scalar but not for vector. The patch try to
make it consistent and will convert below code,
shortcut_for_riscv_vrsub_case_1_32:
vl1re32.v v1,0(a1)
vsetvli zero,a2,e32,m1,ta,ma
vrsub.viv1,v1,-1
vs1r.v v1
From: Yanzhang Wang
This patch will optimize the below mulh example,
vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) {
return __riscv_vmulh_vx_i32m1(v1, 0, vl);
}
from mulh pattern
vsetvli zero, a2, e32, m1, ta, ma
vmulh.vx v24, v24, zero
vs1r.vv24, 0(a0)
to belo
From: Yanzhang Wang
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/acle/asm/subr_s8.c: Modify subr with -1
to not.
Signed-off-by: Yanzhang Wang
---
Tested on my local arm environment and passed. Thanks Andrew Pinski's comment
the code is the same with that.
gcc/testsuite/gcc.
From: Yanzhang Wang
PR 109617
gcc/ChangeLog:
* config/riscv/vector-iterators.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Signed-off-by: Yanzhang Wang
Co-authored-by: Pan Li
---
gcc/config/riscv/vector-iterators.md
From: Yanzhang Wang
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_scalable_vector_type_p):
(riscv_arg_has_vector):
(riscv_pass_in_vector_p):
(riscv_get_arg_inf
From: Yanzhang Wang
PR 109617
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when
MIN_VLEN >= 128.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Signed-off-by: Yanzhang Wang
Co-authored-by: Pan Li
---
g
From: Yanzhang Wang
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
gcc/ChangeLog:
* config/riscv/riscv.cc:
(riscv_scalable_vector_type_p): Determine whether the type is scalable
vector.
(riscv_arg_has_vector): Det
From: Yanzhang Wang
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
gcc/ChangeLog:
* config/riscv/riscv.cc:
(riscv_scalable_vector_type_p): Determine whether the type is scalable
vector.
(riscv_arg_has_vector): Det
From: Yanzhang Wang
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-v.cc (default_zero_call_used_regs):
(riscv
From: Yanzhang Wang
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-protos.h (GCC_RISCV_PROTOS_H):
(emit_hard_
From: Yanzhang Wang
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
* confi
From: Yanzhang Wang
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
* confi
From: Yanzhang Wang
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
* confi
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