[PATCH V1] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c

From: yulong I find fail of the xtheadcondmov-indirect-rv64.c test case and provide the way to solve it. In this patch, I modify the check information of the function(ConEmv_imm_imm_reg and ConNmv_imm_imm_reg) body. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-indirect-rv

[PATCH V2] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c

From: yulong I find fail of the xtheadcondmov-indirect-rv64.c test case and provide a way to solve it. In this patch, I take Kito's advice that I modify the form of the function bodies.It likes *[a-x0-9]. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-indirect-rv32.c:Modify

[PATCH V1] RISC-V:Add float16 tuple type support

From: yulong This patch adds support for the float16 tuple type. gcc/ChangeLog: * config/riscv/genrvv-type-indexer.cc (valid_type): Enable FP16 tuple. * config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro. (ADJUST_ALIGNMENT): Ditto. (RVV_TUPLE_PARTIAL_MODES

[PATCH V1] RISC-V: Fix a bug that causes an error insn.

From: yulong I test the following rvv intrinsics. vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) { return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);} And I got an error info,that is error: unrecognizable insn:(insn 17 16 18 2 (set (reg:

[PATCH V1] RISC-V:Add float16 tuple type abi

From: yulong gcc/ChangeLog: * config/riscv/vector.md: Add float16 attr at sew、vlmul and ratio. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-10.c: Add float16 tuple type case. * gcc.target/riscv/rvv/base/abi-11.c: Ditto. * gcc.target/riscv/rvv/base/a

[PATCH V1] RISC-V: Fix a redefinition bug for the fd-4.c

From: yulong This patch fix a redefinition bug. There are have a definition about mode_t in the fd-4.c, but it duplicates the definition in stdio.h.There are have a definition about mode_t in the fd-4.c, but it duplicates the definition in stdio.h. gcc/testsuite/ChangeLog: * gcc.dg/an

[PATCH V0] RISC-V: Fix a redefinition bug for the fd-4.c

From: yulong This patch fix a redefinition bug. There are have a definition about mode_t in the fd-4.c, but it duplicates the definition in stdio.h. gcc/testsuite/ChangeLog: * gcc.dg/analyzer/fd-4.c: delete the definition of mode_t. --- gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -

[PATCH V3 0/3] RISC-V:Add mininal support for Zicbo[mzp]

From: yulong This patchset adds support for three recently ratified RISC-V extensions: - Zicbom (Cache-Block Management Instructions) - Zicbom (Cache-Block Management Instructions) - Zicboz (Cache-Block Zero Instructions) Patch 1: Add Zicbom/z/p mininal support Patch 2: Add Zicbom/z/p ins

[PATCH V3 1/3] RISC-V: Add mininal support for Zicbo[mzp]

From: yulong This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. (MASK_ZICBOM): New. (MASK_ZI

[PATCH V3 2/3] RISC-V:Cache Management Operation instructions

From: yulong This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions. diff with the previous two versions: 1.We change the instruction format from "prefetch.i\t%0" to "prefetch.i\t%a0" about the prefetch.i, cbo.clean, cbo.flush, cbo.inval, cbo.ze

[PATCH V3 3/3] RISC-V:Cache Management Operation instructions testcases

From: yulong This commit adds testcases about CMO instructions. diff with the previous two versions: We change the names of builtin about cbo.clean, cbo.flush, cbo.inval, cbo.zero and prefetch.i instructions in the testcases. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbom-1.c:

[PATCH V4 0/3] RISC-V:Add mininal support for Zicbo[mzp]

From: yulong This patchset adds support for three recently ratified RISC-V extensions: - Zicbom (Cache-Block Management Instructions) - Zicbop (Cache-Block Prefetch hint instructions) - Zicboz (Cache-Block Zero Instructions) Patch 1: Add Zicbom/z/p mininal support Patch 2: Add Zicbom/z/p

[PATCH V4 1/3] RISC-V: Add mininal support for Zicbo[mzp]

From: yulong This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. (MASK_ZICBOM): New. (MASK_ZI

[PATCH V4 2/3] RISC-V:Cache Management Operation instructions

From: yulong This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions. diff with the previous version: We use unspec_volatile instead of unspec for those cache operations. We use UNSPECV instead of UNSPEC and move them to unspecv. gcc/ChangeLog:

[PATCH V4 3/3] RISC-V:Cache Management Operation instructions testcases

From: yulong This commit adds testcases about CMO instructions. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbom-1.c: New test. * gcc.target/riscv/cmo-zicbom-2.c: New test. * gcc.target/riscv/cmo-zicbop-1.c: New test. * gcc.target/riscv/cmo-zicbop-2.c: New

[PATCH V1] RISC-V: Add mininal support for zabha extension.

From: yulong This patch add the mininal support for zabha extension. The doc url as follow: https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc There are have no amocas.[b|h] instructions, because the zacas extension is not merged. gcc/ChangeLog: * common/config/riscv/riscv-

[PATCH] RISC-V: Bugfix for Duplicate entries for -mtune in --target-help[Bug 116347]

From: yulong This patch try to fix a bug[116347]. I change the name of the micro-arch, because I think micro-arch and core have the same name that caused the error. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Rename. (RISCV_CORE): Ditto. --- gcc/config/riscv/ri

[PATCH V1 0/1] UNRATIFIED RISC-V:Add 'ZiCond' extension

From: yulong *** WAIT FOR SPECIFICATION FREEZE *** This is an implementation for unratified and not frozen RISC-V extension and not intended to be merged for now. The intent to submit this patchset is to synchronize with the implementation of binutils about the ZiCond extension. This patchset ad

[PATCH V1 1/1] UNRATIFIED RISC-V: Add 'ZiCond' extension

From: yulong [DO NOT MERGE] Until 'ZiCond' extension is frozen/ratified and final version number is determined, this patch should not be merged upstream. This commit uses version 1.0 as in the documentation. This commit adds support for the latest draft of RISC-V Integer Conditional (ZiCond) ex

[PATCH] RISC-V:Fix a bug that is the CMO builtins are missing parameter

From: yulong We changed the RTL mode and builtins format about zicbom and zicboz subextensions. gcc/ChangeLog: * config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed "RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)" * config/riscv/riscv-ftypes.def (0): deleted DEF_RISCV_FTYPE

[PATCH V2] RISC-V:Fix a bug that is the CMO builtins are missing parameter

From: yulong We changed builtins format about zicbom and zicboz subextensions and added test cases. diff with the previous version: 1.We deleted the RLT mode's second input operand. 2.We modified the type of builtins from RISCV_BUILTIN_DIRECT to RISCV_BUILTIN_DIRECT_NO_TARGET. 3.We modified the

[PATCH V3] RISC-V:Fix a bug that is the CMO builtins are missing parameter

From: yulong We changed builtins format about zicbom and zicboz subextensions and modified test cases. diff with the previous version: 1.We modified the FUNCTION_TYPE from RISCV_VOID_FTYPE_SI/DI to RISCV_VOID_FTYPE_VOID_PTR. 2.We added a new RISCV_ATYPE_VOID_PTR in riscv-builtins.cc and a new

[PATCH V3] RISC-V: Fix a redefinition bug for the fd-4.c

From: yulong This patch fix a redefinition bug. There are have a definition about mode_t in the fd-4.c, but it duplicates the definition in stdio.h. gcc/testsuite/ChangeLog: * gcc.dg/analyzer/fd-4.c: delete the definition of mode_t. --- gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -

[PATCH V1] RISCV: Modified validation information for contracts-tmpl-spec2.C

From: yulong This patch fixes the problem of the contracts-tmpl-spec2.c running failure. When run the dejagnu test, I find that the output is inconsistent with that verified in the testcase. So I try to modify it, and then it can be passed. gcc/testsuite/ChangeLog: * g++.dg/contracts/

[PATCH V4] RISC-V: Fix a redefinition bug for the fd-4.c

From: yulong This patch fix a redefinition bug. There are have a definition about mode_t in the fd-4.c, but it duplicates the definition in types.h that be included by stdio.h. gcc/testsuite/ChangeLog: * gcc.dg/analyzer/fd-4.c: delete the definition of mode_t. --- gcc/testsuite/gcc.d

[PATCH V2] RISC-V: Modified validation information for contracts-tmpl-spec2.C

From: yulong This patch fixes the problem of the contracts-tmpl-spec2.c running failure. When run the dejagnu test, I find that the output is inconsistent with that verified in the testcase. So I try to modify it, and then it can be passed. gcc/testsuite/ChangeLog: * g++.dg/contracts/c

[PATCH V5] Testsuite: Fix a redefinition bug for the fd-4.c

From: yulong This patch fix a redefinition bug. There are have a definition about mode_t in the fd-4.c, but it duplicates the definition in types.h that be included by stdio.h. Thanks to Jeff Law for reviewing the previous version. gcc/testsuite/ChangeLog: * gcc.dg/analyzer/fd-4.c: del

[PATCH V2 0/2] RISC-V:Add Cache Management Operation ISA Extensions Intrinsics

From: yulong This patchset adds intrinsic support for CMOs extensions. cf. ; Patch 1: Add Zicbom/z/p intrinsic support Patch 2: Add test cases. Diff with V1: Add intrinsic support for the prefetchi instruction. yulong (2): RISC-V:Add

[PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions

From: yulong gcc/ChangeLog: * config.gcc: Add riscv_cmo.h. * config/riscv/riscv_cmo.h: New file. --- gcc/config.gcc | 2 +- gcc/config/riscv/riscv_cmo.h | 93 2 files changed, 94 insertions(+), 1 deletion(-) create mode 10064

[PATCH 2/2] RISC-V:Add intrinsic cases for the CMOs extensions

From: yulong gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-32.c: New test. * gcc.target/riscv/cmo-64.c: New test. --- gcc/testsuite/gcc.target/riscv/cmo-32.c | 58 + gcc/testsuite/gcc.target/riscv/cmo-64.c | 58 + 2 files change

[PATCH 0/2] RISC-V:Add Cache Management Operation ISA Extensions Intrinsics

From: yulong This patchset adds intrinsic support for CMOs extensions.But it not include prefetchi. cf. ; Patch 1: Add Zicbom/z/p intrinsic support Patch 2: Add test cases. yulong (2): Add intrinsic support for the CMOs extensions

[PATCH 2/2] Add intrinsic cases for the CMOs extensions

From: yulong gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-32.c: New test. * gcc.target/riscv/cmo-64.c: New test. --- gcc/testsuite/gcc.target/riscv/cmo-32.c | 52 + gcc/testsuite/gcc.target/riscv/cmo-64.c | 52 + 2 files change

[PATCH 1/2] Add intrinsic support for the CMOs extensions

From: yulong gcc/ChangeLog: * config.gcc: Add riscv_cmo.h. * config/riscv/riscv_cmo.h: New file. --- gcc/config.gcc | 2 +- gcc/config/riscv/riscv_cmo.h | 84 2 files changed, 85 insertions(+), 1 deletion(-) create mode 10064

[PATCH] RISC-V: Add norelax function attribute

From: yulong This patch adds norelax function attribute that be discussed in riscv-c-api-doc PR#94. URL:https://github.com/riscv-non-isa/riscv-c-api-doc/pull/94 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_declare_function_name): Add new attribute. --- gcc/config/riscv/riscv.cc

[PATCH 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.

From: yulong This commit adds testcases for Xsfvqmaccqoq/dod. Co-Authored by: Kito Cheng Co-Authored by: Monk Chiang Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: * gcc.target/ri

[PATCH 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvqmaccqoq/dod.

From: yulong This patch implements the Sifvie vendor extension Xsfvqmaccqoq and Xsfvqmaccdod[1] support to gcc. Providing intrinsic functions vqmacc (signed-signed mac), vqmaccu (unsigned-unsignedmac), vqmaccsu (signed-unsigned mac), vqmaccus (unsigned-signed mac) for 4x8x4 and 2x8x2 martix multi

[PATCH 1/2] RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.

From: yulong This commit adds intrinsics support for Xsfvqmaccqoq/dod. Co-Authored by: Kito Cheng Co-Authored by: Monk Chiang Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config.gcc: Add new SiFive *.o files. * config

[PATCH V1] RISC-V: Add the mini support for SiFive extensions.

From: yulong This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and xsfvfnrclipxfqf extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New. * config/riscv/riscv.opt: New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-sf-3.c: New test.

[PATCH 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions.

From: yulong This commit adds testcases for Xsfvfnrclipxfqf. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vfnr

[PATCH 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvfnrclipxfqf extension.

From: yulong This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] support to gcc. Providing support for FP32-to-int8 Ranged Clip instrctions. [1] https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao

[PATCH 1/2] RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.

From: yulong This commit adds intrinsics support for XXsfvfnrclipxfqf. We also redefine the enum type frm_op_type in riscv-vector-builtins-bases.h file, because it be used in sifive-vector-builtins-bases.cc file. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan

[PATCH V4 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

From: yulong This commit adds intrinsics support for Xsfvcp extension. Diff with V3: Add new RTL mode and sifive_vector.h file. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config.gcc: Add sifive_vector.h. * config/ris

[PATCH V4 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

From: yulong This patch implements the Sifvie vendor extension Xsfvcp[1] support to gcc. Providing a flexible mechanism to extend application processors with custom coprocessors and variable-latency arithmetic units intrinsics. [1] https://www.sifive.com/document-file/sifive-vector-coproces

[PATCH V4 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

From: yulong This commit adds testcases for Xsfvcp. Diff with V3: Change h file from riscv_vector.h to sifive_vector.h. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.

[PATCH 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

From: yulong This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] support to gcc. Providing support for FP32-to-int8 Ranged Clip instrctions. [1] https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-Authored by: Jiawei Chen Co-Authored by

[PATCH 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

From: yulong This commit adds intrinsics support for Xsfvcp extension. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config/riscv/constraints.md (Ou01): New constraint. (Ou02): Ditto. * config/riscv/generic-vecto

[PATCH] testsuite:RISC-V:Modify the char string.

From: yulong This patch modifies the char string from __riscv_xsfvcp to __riscv_xsfcease. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-sf-2.c: Modify the char string. --- gcc/testsuite/gcc.target/riscv/predef-sf-2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --gi

[PATCH V2 2/2] RISC-V: Add intrinsic testcases for SiFive Xsfvcp extensions.

From: Liao Shihua This commit adds testcases for Xsfvcp. Diff with V1: Reduce some cases. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test. * gcc.target/riscv/rvv

[PATCH V2 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

From: yulong This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] support to gcc. Providing support for FP32-to-int8 Ranged Clip instrctions. [1] https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-Authored by: Jiawei Chen Co-Authored by

[PATCH V2 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

From: yulong This commit adds intrinsics support for Xsfvcp extension. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config/riscv/constraints.md (Ou01): New constraint. (Ou02): Ditto. * config/riscv/generic-vecto

[PATCH V5 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

From: yulong This commit adds intrinsics support for Xsfvcp extension. Diff with V4: Delete the sifive_vector.h file. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config/riscv/constraints.md (Ou01): New constraint. (Ou0

[PATCH V5 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

From: yulong This patch implements the Sifvie vendor extension Xsfvcp[1] support to gcc. Providing a flexible mechanism to extend application processors with custom coprocessors and variable-latency arithmetic units intrinsics. [1] https://www.sifive.com/document-file/sifive-vector-coproces

[PATCH V5 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

From: yulong This commit adds testcases for Xsfvcp. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.

[PATCH V3 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

From: yulong This commit adds intrinsics support for Xsfvcp extension. Diff with V2: Change the RTL mode from unspec to unspec_volatile. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config/riscv/constraints.md (Ou01): New cons

[PATCH V3 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

From: Liao Shihua This commit adds testcases for Xsfvcp. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.

[PATCH V3 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

From: yulong This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] support to gcc. Providing support for FP32-to-int8 Ranged Clip instrctions. [1] https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-Authored by: Jiawei Chen Co-Authored by