OK. Sounds reasonable.
But from my side, I used to commit patches after full coverage testing.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-12-21 11:28
To: 钟居哲; cooper.joshua; gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma;
Cooper Qu
Subject: Re
erand"))
(match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero")]
UNSPEC_SEL))]
"TARGET_SVE"
)
Otherwise, LGTM. But I'd like to expect Kito chime in.
Thanks.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-21 10:48
To: gcc-patches
CC: kito.cheng; jeffreyalaw;
RVV intrinsics s
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
\ No newline at end of file
Each file needs a newline.
+ (match_operand:VSI 1 "vector_merge_operand&q
\ No newline at end of file
Still no new line in vector-iterator.md
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-22 09:38
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v7 2/3] RISC-V: Add crypto machine descriptions
Patch v7: Remove mode of
Also the copy right is incorrect:
+;; Copyright (C) 2022-23 Free Software Foundation, Inc.
It should be:
Copyright (C) 2023 Free Software Foundation, Inc.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-22 09:38
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject
Machine description part is ok from my side.
But I don't know the plan of vector crypto.
I'd like to wait kito or Jeff to make sure we allow vector-crypto intrinsics as
part of GCC-14 release.
Thanks.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-22 09:59
To: gcc-
erlap constraint using attribute, More details
you can learn from
(set_attr "group_overlap"
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2023-12-22 11:33
收件人： 钟居哲; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Jeff Law; Christoph
Müllner; jinma; Cooper Qu
主题： 回复：[PATCH
uot;)
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_VECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx&qu
end of file
New line should be added into prefix.c
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-25 14:25
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4
OK. This sub-patch is ok to commit after adding new line to prefix.c
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2023-12-25 15:08
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： 回复：[PATCH v4 4/6] RISC-V
OK.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-25 16:14
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4 4/6] RISC-V: Adds the prefix "th.&quo
send V2 with test tweak:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641447.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-27 09:52
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Disallow transformation into
LGTM assume you have passed the regression.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-29 12:06
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V
LGTM assume you have passed the regression.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-29 12:10
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V
+/* Static information about a set of crypto vector functions. */
+struct crypto_function_group_info
+{
+ struct function_group_info rvv_function_group_info;
+ /* Whether the function is available. */
+ unsigned int (*avail) (void);
+};
What is this used for ?
juzhe.zh...@rivai.ai
From
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-02 17:18
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v6 1/2] RISC-V: Add crypto vector builtin function.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def
Move all tests into gcc.target/riscv/rvv/base
All of these:
#include
change them into:
#include "riscv_vector.h"
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-02 15:47
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v5 2/2] RISC-V: Add cry
\ No newline at end of file
All files Need newline.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-03 09:01
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v6 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v6: Move intrinsic tests into rvv/base
We have no choice. You should know theadvector is totally unrelated with RVV1.0
standard ISA.
Adding `%^' which missing totally unrelated ISA makes no sens to me.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2024-01-03 10:54
To: 钟居哲
CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilso
No. It will need to change all patterns in vector.md.
It's a nightmare.
You should note I will refine vector.md in GCC-15, mixing theadvector things
make me impossible to maintain
RVV1.0.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2024-01-03 11:19
To: juzhe.zh...@rivai.
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-03 13:21
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v7 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base
While working on PR113209, I noticed it is same issue so this patch not only
fixes PR113206 bug, but also fixes
PR113209.
Send V2 with adding PR113209 test and PR target/113209:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641740.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date
\ No newline at end of file
Each file needs newline.
I am not able to review arch stuff. This needs kito.
Besides, Andrew Pinski want us defer theadvector to GCC-15.
I have no strong opinion here.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-04 17:15
收件人： 钟居哲; Jeff Law; gcc-patches
抄送
rs)
I suspect you didn't enable rtl check in the regression:
../../configure --enable-gcc-checking=rtl.
Plz enable rtl check in the regression tests.
juzhe.zh...@rivai.ai
o revert the patch, then commit it after he fixes the ICE with
enabling RTL check.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-01-05 11:24
To: juzhe.zhong
CC: gcc-patches; Kito Cheng; Kito.cheng
Subject: Re: [committed] RISC-V: Add crypto vector builtin function.
On Thu, 04 Jan 2024 1
I have reverted those 2 commits:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=960c2620db254a1edc2cd61e608df73073b3de0d
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b3ec98d458f2b285bb7b3fa4fcd93fd830fee069
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-01-05 11:24
To: juzhe.zhong
_int 5)
Ah, I knew something go wrong in case of attribute bugs.
I think it should be a separate patch which is "Fix vlmax type attribute bugs
of vclmul and vclmulh instructions".
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-05 16:51
To: gcc-patches
CC: kito.cheng; jeffreyalaw
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-05 17:23
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Fix avl-type operand index error for ZVBC
This patch fix the rtl-checking error for crypto vector. The root
cause is the avl-type
Yes. It does sufficient. Send a patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642216.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-09 00:45
To: 钟居哲; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; Jeff Law
Subject: Re: [PATCH] RISC-V: Teach liveness computation
with index < 4.
For bias, I think that won't be the issue. Currently, BIAS is not used by RVV
and only used on len_load/len_store for IBM targets.
So, the bias value by default is 0 in all other situations except
len_load/len_store specifically for IBM.
juzhe.zh...@rivai.ai
From: Tam
always 0.
But for consistency, I think we should use the codes as follows.
I see your patch is so big and separate into multiple sub-patches.
Do you have a patch that directly can be applied for whole support.
I want to support length and test that base your patch.
Thanks.
juzhe.zh...@rivai.ai
return true;
- }
+ riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD);
+ return true;
+}
+
+ return false;
+}
I don't understand why you touch scalar part here ? It looks like formating ?
If yes, it should be another separate patch.
Otherwise, Ok from my
nds[2]))
-DONE;
- else if (riscv_expand_block_move (operands[0], operands[1], operands[2]))
+ if (riscv_expand_block_move (operands[0], operands[1], operands[2]))
DONE;
I think it should be an NFC patch in another separate patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-01
All regressions (zve64d/zvl128b/zvl256b/zvl512b/zvl1024b) passed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-01 08:51
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS regression
This patch fix 2 regression (one
DE (int_reg), dest)));
Use emit_move_insn
+ emit_insn (
+ gen_movdf (dest, gen_lowpart (GET_MODE (dest), int_reg)));
Use emit_move_insn
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-01 15:52
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-01 17:27
To: Roger Sayle; gcc-patches
CC: rdapp.gcc; juzhe.zh...@rivai.ai
Subject: Re: [RISC-V PATCH] Improve style to work around PR 60994 in host
compiler.
Yes, OK, thanks for that. CC'ing Juzhe as this is his pass.
Regards
Robin
One more comment:
+ unsigned int num = (smode == DImode || smode == DFmode)
+ && !TARGET_VECTOR_ELEN_64 ? 2 : 1;
change it into:
unsigned int num = known_eq (GET_MODE_SIZE (smode), 8) &&
!TARGET_VECTOR_ELEN_64 ? 2 : 1;
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-
patches as follows:
1. Add crypto march support (riscv-common.cc）
2. Add crypto machine descriptions (vector-cryptio.md)
3. Add crypto builtin.
4. Add testcases.
Thanks.
juzhe.zh...@rivai.ai
LGTM Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-04 16:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test case for bug PR112813
From: Pan Li
The bugzilla 112813 has been fixed recently, add below test
case for the bug
+ if (!TARGET_64BIT
+ && maybe_gt (GET_MODE_SIZE (scalar_mode), GET_MODE_SIZE (Pmode)))
I think if (maybe_gt (GET_MODE_SIZE (scalar_mode), GET_MODE_SIZE (Pmode)))
should be enough.
Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-05 16:22
To: gcc-pa
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-05 16:38
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution
test) on RV32
From: xuli
This patch fixs the issue of g++.dg/torture/vshuf-v2di.C
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-05 23:13
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add vec_init expander for masks [PR112854].
Hi,
PR112854 shows a problem on rv32 with zvl1024b. During the course
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-06 12:49
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Remove useless modes
From: xuli
gcc/ChangeLog:
* config/riscv/riscv.md: Remove.
---
gcc/config/riscv/riscv.md | 1 -
1 file changed, 1 deletion
cmp (instance.base_name, "vsha2ch") == 0
+ || strcmp (instance.base_name, "vsha2cl") == 0
+ || strcmp (instance.base_name, "vsm3me") == 0)
+ && overloaded_p))
+ b.append_name (operand_suffixes[instance.op_info->op]);
Split them into another s
roup
;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0,
v2, or v4 is not).
;; So the source operand should have LMUL >= 1.
Reference patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/638869.html
Currently, I don't have a soluti
gff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops)
change it into:
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops, true)
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-07 10:15
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; zhusonghe; panciy
perand"" i")
+ (match_operand 8 "const_int_operand"" i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (ashift:VWEXTI
+(zero_extend:VWEXTI
+ (match_operand: 3
I think you can send a single separate patch with adding unsigned int (*avail)
(void)
into current function_group_info first.
And test full coverage current rvv intrinsics.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-12-07 10:28
To: wangfeng; gcc-patches
CC: kito.cheng
Resend the patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639728.html
with changelog changes.
No codes change.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-07 18:15
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC
-types.def \
$(RISCV_BUILTINS_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-vector-builtins.cc
in t-riscv file.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-07 20:17
To: gcc-patches
CC: kito.cheng; jeffreyalaw
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-08 16:00
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in
V_F2DI_CONVERT_BRIDGE
From: Pan Li
The mode attr V_F2DI_CONVERT_BRIDGE converts the floating
+ if (shuffle_series (d))
+ return true;
Could you rename it into shuffle_series_patterns ?
Just to make naming consistent.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-09 21:18
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
dest operand always LMUL = 1 mode.
So, when -march=rv64gcv, the dest mode should be V4SI, if
-march=rv64gcv_zvl256b, the dest mode should be V8SI.
...etc. Different TARGET_MIN_VLEN, different M1 mode. It's going to be a big
change in RISC-V backend.
juzhe.zh...@rivai.ai
From: Robin Dapp
I think it's reasonable refactor reduction instruction pattern work around this
issue.
Going to send a patch to apply this solution.
So drop this patch. Sorry for bothering Richard S.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-11 17:01
To: Juzhe-Zhong; gcc-patches
CC: rdap
Oh. I just confirmed. V1SI make perfect sens since we never apply partial
vectorization for VLSmode.
Drop this patch and going to refactor reduction pattern to fix this issue.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-11 17:11
To: juzhe.zh...@rivai.ai; gcc-patches
CC
. */
+
+static bool
+select_appropriate_lmul (HOST_WIDE_INT length_in,
+HOST_WIDE_INT &lmul_out)
+{
I don't think we need this, you only need to use TARGET_MAX_LMUL
juzhe.zh...@rivai.ai
else if (partial_subreg_p (use->mode (), mode))
use->set_mode (mode);
}
use->record_reference (ref, false);
}
Is it reasonable to you ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-11 19:45
To: juzhe.zhong\@rivai.ai
CC: Robin Dapp; g
Thanks Richard.
Committed with V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640172.html
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-11 20:12
To: juzhe.zhong\@rivai.ai
CC: Robin Dapp; gcc-patches
Subject: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for
lgtm.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-12 16:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
From: Pan Li
This patch would like to disable the avl propagation for the follow
reasons
disable multilib. */
#ifndef _RISCV_VECTOR_WRAP_H
#define _GCC_WRAP_STDINT_H
#include "stdint-gcc.h"
#include_next
#define _RISCV_VECTOR_WRAP_H
#endif
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-12 18:01
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2...@intel.c
ctor.
I committed it with a separate patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-22 23:35
To: Kito Cheng
CC: Robin Dapp; Juzhe-Zhong; GCC Patches; Jeff Law
Subject: Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS
It's really great improvement
L12:
vsetvli a7,zero,e8,mf8,ta,ma
addi a5,a5,1
vle8.v v1,0(a6)
vse8.v v1,0(a4)
addi a0,a0,4
addi a1,a1,4
beq a2,a5,.L10
.L5:
addi a4,a1,-1200
addi a6,a0,-1200
bltu a3,a5,.L12
vsetvli t1,zero,e8,m8,ta,ma
addi a5,a5,1
vlm.v v1,0(a0)
vsm.v v1,0(a1)
addi a0,a0,4
addi a1,a1,4
bne a2,a5,.L5
.L10:
ret
ju
Thanks kito.
Address all comments and committed with V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628423.html
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-25 01:01
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V2] RISC-V: Refactor
Ok.
I am not familiar with scheduling stuff but I hope you can fix those 2 issues.
I have no objection with this patch and I prefer Jeff or kito make the decision
for this patch.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-23 22:56
To: 钟居哲; gcc-patches; palmer; kito.cheng
Thanks for taking care of this issue.
Ok to backport GCC-13.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-08-28 10:33
To: xuli1; gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfying REG_P(operand[1
Address comment:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628546.html
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-28 11:48
To: Juzhe-Zhong
CC: gcc-patches; lehua.ding; kito.cheng
Subject: Re: [PATCH] RISC-V: Enable vec_init testsuite for RVV VLA vectorization
top, we will be missing fuse user vsetvl (in bb 3 e32 m1)
into user vsetvl (in bb 2 e8 mf4).
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-28 16:58
To: Robin Dapp
CC: Juzhe-Zhong; gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Disable user vsetvl fusion into EMPTY block
I
Address comments:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628568.html
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-08-28 16:58
To: Robin Dapp
CC: Juzhe-Zhong; gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Disable user vsetvl fusion into EMPTY block
Is it possible to
Ok. Add -Wno-psabi which reduce 5 FAILS.
V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628572.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-28 16:22
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Enable
Ok.
It reduced some failures, and new report is updated on the commit log in V4:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628580.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-28 18:29
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
>> Juzhe mentioned he doesn't want to commit this before
>> all/most bugs are addresses anyway, right?
Yes.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-28 22:27
To: Kito Cheng; Juzhe-Zhong
CC: rdapp.gcc; gcc-patches; kito.cheng
Subject: Re: [PATCH V4] RISC-V: Enable
Ping. This patch also fixed issue occurred in RISC-V backend:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71
Thanks.
juzhe.zh...@rivai.ai
Ok for trunk. But not sure whether it's ok for GCC-13.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-08-30 17:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
This patch fix pr111234 (a vsetvl pass ICE) when f
simple patch for dynamic cost model:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629212.html
committed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-04 17:08
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-05 18:32
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP SGNJ autovec for VLS mode
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary
pred_mov
(mode),
insn_flags, operands, operands[2]);
}
DONE;
}
[(set_attr "type" "vmov")]
)
We split special case use emit_insn (gen_rtx_SET (operands[0], operands[1]));
Missing this pattern will cause ICE but current testcases didn't produce such
Sure. Thanks kito.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-11 10:57
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]
OK, but could you split this patch into two patches? pre-approved for both.
On Mon
Type:\\tREFERENCE
ADDRESS\n" 1
FAIL: gcc.dg/tree-ssa/split-path-11.c scan-tree-dump-times split-paths "join
point for if-convertable half-diamond" 1
These are bogus dump FAILs and I have 100% confirm each of them, we are having
same behavior as SVE.
So is this patch ok for trunk ?
j
Committed. Thanks kito.
>> I guess you will remove get_all_predecessors once LMUL cost
>> model can use dominator info as well?
Yes. I am trying but there is a failed case for dynamic LMUL.
Not sure whether it can work now.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09
Thanks for supporting it even though I don't like this feature :).
The framework is LGTM.
Let's wait for kito's more comments.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-11 15:57
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RI
ase, shape, mode, types, pred);
registered_function *rfn
= function_table->find_with_hash (instance, instance.hash ());
return rfn ? rfn->decl : NULL_TREE;
}
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-11 17:04
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; yanzhang.wang
Subjec
>> What about one test with global live ranges? Not a necessity IMHO we can
>> still
>> add it later.
We already have.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 04:31
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re:
Add a function call get_non_overloaded_instance into instance.
The instance already know it is void vmv (void).
In this function search the arglist. and return the real non-overloaded decl.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-09-12 09:20
To: 钟居哲
CC: kito.cheng; gcc-patches; Wang
Ping this simple optimization.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 11:34
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Enhance AVL propagation for complicate reduction
auto-vectorization
I notice we
e the fallbacks to VLS still
>> available when we prefer scalable vectors?
Yes. since it is -fno-vect-cost-model.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:23
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV
On 11/6/23
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-07 14:41
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP ceil to i/l/ll diff size autovec
From: Pan Li
This patch would like to support the FP below API auto vectorization
with
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:52
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix FAIL of SAD tests for RVV
On 11/6/23 20:36, Juzhe-Zhong wrote:
> RVV didn't ex
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:49
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV
On 11/6/23 20:30, juzhe.zh...@rivai.ai wrote
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:53
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix
FAIL of vect-sdiv-pow2-1.c for RVV#
On 11/6
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-11-07 15:49
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Fixed failed rvv combine testcases
Hi,
This patch fixed the fellowing failed testcases on
able
vect_pack_trunc test.
But I think we don't need it any more. Your fix looks more reasonable.
juzhe.zh...@rivai.ai
So, this patch not only fixes RVV FAIL, but also fixes GCN ?
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 18:09
To: Juzhe-Zhong; gcc-patches@gcc.gnu.org
CC: jeffreya...@gmail.com; rguent...@suse.de
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 07:44
Could you try this ?
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {
xfail { { ! vect_hw_misalign } || { vect512 } } } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" {
xfail { ! vect512 }
} } } } */
Could you try again ? If it works for you, I am gonna send V2 patch to Richi.
Thank you so much for help.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 19:21
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428
{
target { ! vect512 } } } } */
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-11-07 19:23
To: ams; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
Do you mean this ?
/* { dg-final { scan-tree-dump-times &qu
SLP" 4 "vect" {
target { vect512 } } } } */
Tested on RVV is OK.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 19:44
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 11:24, juzhe.zh...@rivai.a
It need command line to enable SIMD auto-vectorization (VLS mode in RVV).
It will enable VLS modes auto-vectorization by default if we didn't add RISCV
into vect_cmdline.
So adding it to disable VLS mode vectorization which will fix the FAILs like
other targets.
juzhe.zh...@rivai.ai
Thanks a lot ! I will send V2 for Richi to review.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 20:05
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 12:03, juzhe.zh...@rivai.ai wrote
Thanks. Committed.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-07 20:10
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
> It need command line to enable SIMD auto-vectorizat
Thanks Lehua.
Appreciate for supporting subreg liveness tracking with tons of work.
A nit comments, I think you should mention these following PRs:
106694
89967
106146
99161
No need send V2 now. You can send V2 after Richard and Vlad reviewed.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date
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