I think it just trigger a latent bug that we didn't encounter.
Hi, Robin. Would you mind give me preprocessed file to reproduce the issue ?
I suspect it triggers latent bug in VSETVL PASS.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-02-05 12:36
To: Juzhe-Zhong; gcc-patches
CC: kito.
Did you run the C compiler compile C++ intrinsic test ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-02-06 16:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty
args
From: Pan Li
There is
Why is it 2 not 1 or other value ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-02-07 17:27
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function
checker
From: Pan Li
There is another corn case
Hi, Robin. Could you continue on this LICM issue ?
I am not sure whether my fix is correct, or you may find another way to make
LICM works ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-06 21:14
To: juzhe.zh...@rivai.ai; kito.cheng
CC: rdapp.gcc; gcc-patches; Kito.cheng; jeffreyalaw
Ping this patch which is simple fix on VSETVL PASS.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2024-02-01 17:02
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH v2] RISC-V: Suppress the vsetvl fusion for conflict successors
lgtm.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-23 04:02
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai
CC: rdapp.gcc; jeffreyalaw
Subject: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].
Hi,
for a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to
Sorry, I missed review the testcase:
+/* { dg-final { scan-assembler-times "vmv\.v\.i\tv\[0-9\],0" 0 } } */
I think you should use "scan-assembler-not"
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-23 04:02
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@ri
ibute on GCC-14.
But I'd like to CC more RISC-V GCC folks to see the votes.
If most of the people don't want this in GCC-14 and defer it to GCC-15, I won't
insist on it.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-02-23 16:29
To: Kito Cheng; pan2.li
CC: gcc-patch
LANES)
return DR_GROUP_SIZE (stmt_info);
}
return 0;
}
juzhe.zh...@rivai.ai
ctors (kind, stmt_info))
{
case 2:
stmt_cost += simd_costs->ld2_st2_permute_cost;
break;
case 3:
stmt_cost += simd_costs->ld3_st3_permute_cost;
break;
case 4:
stmt_cost += simd_costs->ld4_st4_permute_cost;
break;
}
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-26 23:54
T
If the scheduling model increases the vsetvls, we shouldn't set it as default
scheduling model
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-26 21:29
To: Edwin Lu; gcc-patches
CC: rdapp.gcc; gnu-toolchain; pan2.li; juzhe.zh...@rivai.ai
Subject: Re: [PATCH] RISC-V: Update
Thanks for supporting this.
I'd rather leave this patch review to kito's since it's kito's proposal.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-02-27 09:17
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; xuli
Subject: [PATCH] RISC-V: Add riscv_vector_cc fun
I suggest specify -fno-schedule-insns to force tests assembler never change for
any scheduling model.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-02-28 08:55
To: jeffreyalaw
CC: juzhe.zhong; Robin Dapp; ewlu; gcc-patches; gnu-toolchain; pan2.li
Subject: Re: [PATCH] RISC-V: Update
should remove them.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-02-28 22:55
To: 钟居哲
CC: pan2.li; gcc-patches; yanzhang.wang; rdapp.gcc; Jeff Law
Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for
RVV
Hmm, maybe only keep --param=riscv-autovec-preference=none
so the regression of RV32 an RV64 of GCC testsuite.
Do you have more patches of theadvector that I didn't review ? plz point them
to me again.
Thanks.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-10 10:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; phi
" vr, vr,
vi, vi, vr, vr, vi, vi")])
+ (match_operand: 2 "vector_merge_operand"" vu,0,
vu,0, vu,0, vu,0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)"
"vms%B3.v%o5\t%0,%4,
ing "no")
+ ]
Change it into:
+ (and (eq_attr "group_overlap" "thv_disabled")
+ (match_test "TARGET_XTHEADVECTOR"))
+ (const_string "no")
+
+ (and (eq_attr "group_overlap" "rvv_disabled")
+ (match_test "TARGET
LGTM from myside. Give another a few more days that some one want to chime in.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-10 14:51
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html
This patch is ok from my side.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma
Foundation, Inc.
Incorrect copyright
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector
Why do you need to invade existing shapes ?
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 15:16
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Handle differences
So vlb has not only sew = 8 ?
But why do you add intrinsics as follows ?
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds,
i8_v_scalar_const_ptr_ops)
Why it is not :
DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds,
all_v_scalar_const_ptr_ops)
?
juzhe.zh...@rivai.ai
发件人
Ok from myside. CCing Robin to see whether he has any more concerns.
Thanks.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-11 10:39
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma
have problem if
they tried to use RVV GCC with like zvl8192b.
juzhe.zh...@rivai.ai
Thanks Richard.
So you think increase scalar_to_vec cost is not the correct approach to fix
this case?
Or could you give me a suggestion to fix this case ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2024-01-11 17:18
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; kito.cheng
8 = .VEC_EXTRACT (vect_patt_27.14_145, _147);
b_5 = _148;
a = 19;
_14 = b_5 != 0;
_15 = (int) _14;
return _15;
The vect dump tree only compute cost include vector_stmt and scalar_to_vec.
It seems it didn't consider VEC_EXTRACT cost ?
juzhe.zh...@rivai.ai
From: Richard Biener
Dat
7;t
>>seem that bad.
Yeah... I just noticed. I should set it as 4 to fix it with biggest VLEN size,
that is, -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=m8...
I am confused now how to fix this case.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 17:52
To: juzhe.zh...@r
>> That said, we also don't really cost all our vsetvls yet (difficult...).
If cost vsetvl, we will need to cost 1 more for each STMT.
However, it is not accurate. Since our VSETVL PASS will eliminate redundancy...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 18:09
And also I have investigate LLVM cost model. They don't cost vsevli in
vectorization cost model.
But their cost model does a good job...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 18:09
To: Richard Biener
CC: rdapp.gcc; juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; Kito.
t_26 1 times scalar_to_vec costs 1 in prologue
This cost should be higher since it cost 3 instructions:
li a4,-32768
addiw a4,a4,104
vmv.v.x v16,a4
Am I correct ?
I guess if we cost 1 case as 1 cost and 2 case as 3 cost. Then we will be good.
juzhe.zh...@rivai.ai
From: Robi
e it.
-zvl65536b, RVV Clang also doesn't vectorize it.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 18:40
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1
h can work well.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
> I think we shouldn't vectorize it with
126 1 times scalar_to_vec costs 3 in prologue
32872 spends 2 scalar instructions + 1 scalar_to_vec cost:
li a4,-32768
addiw a4,a4,104
vmv.v.x v16,a4
It seems reasonable but only can fix test with -march=rv64gcv_zvl256b but
failed on -march=rv64gcv_zvl4096b.
juzhe.zh...@rivai.ai
From: Robin Da
for this test.
Is it reasonable ? IMHO, scalar move (vmv.v.x or vfmv.v.f) should be more
costly than normal vadd.vv since it is transferring data between different
pipeline/register class.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC
e later pass failed
to CSE it...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
> I think we sho
3%]
[local count: 359464610]:
goto ; [100.00%]
}
Final ASM:
main:
lui a5,%hi(a)
li a4,19
sb a4,%lo(a)(a5)
li a0,0
ret
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 20:56
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject:
Good catch. LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-12 09:35
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t
The length of vfloat16m8_t ABI-name should be 17.
gcc/ChangeLog:
* config/riscv
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-01-12 10:52
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Update the comments of riscv_v_ext_mode_p [NFC]
From: Pan Li
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_mode_p): Update
OK.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:21
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Adds the prefix "th.&quo
This patch needs kito review. I can't approve that.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; kito.cheng; Jun Sha (Joshua); Jin Ma; Xianmiao
Qu
Su
ok
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v6] RISC-V: Handle differences between XTheadvector
ok.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:23
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v6] RISC-V: Fix register overlap issue for some
ok.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:24
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Rewrite some instructions using ASM
. */
if (!loop_vinfo)
record_stmt_cost (cost_vec, 1, vec_to_scalar, stmt_info, NULL_TREE,
0, vect_epilogue);
Since it's stage 4, I guess we can't change this now.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2024-01-11 17:57
To: Robin Dapp
CC
I think you should also remove riscv_vector_abi
since vector ABI is ratified and we should by default enable vector calling
convention by default.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding; yanzhang.wang
LGTM. I think removing riscv_vector_abi can be another separate followup patch.
But plz make sure you have passed the regression before committed.
Thanks.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding
94 & mask__4.12_197;
vect_patt_158.14_199 = .VCOND_MASK (mask_patt_157.13_198, { 1, 1, 1, 1, 1, 1,
1, 1 }, { 0, 0, 0, 0, 0, 0, 0, 0 });
vect_patt_159.15_200 = [vec_unpack_lo_expr] vect_patt_158.14_199;
vect_patt_159.15_201 = [vec_unpack_hi_expr] vect_patt_158.14_199;
juzhe.zh...@rivai.ai
Fr
{ 1, 2, 3, 4 };
_1 = b[0];
_5 = b[2];
MEM [(int *)&a] = vect__2.6_25;
_11 = b[4];
_13 = b[6];
_27 = {_1, _5, _11, _13};
vect__9.9_28 = _27 * { 3, 4, 5, 7 };
MEM [(int *)&a + 16B] = vect__9.9_28;
We can confirm it here: https://godbolt.org/z/6jGrEoz9s
juzhe.zh..
Are you saying using glibc lib ? I do the testing with newlib, I didn't
anything wrong.
It seems that this patch triggers latent bug of VSETVL PASS (Even though this
patch doesn't change anything related to VSETVL PASS).
I will investigate it.
Thanks.
juzhe.zh...@rivai.ai
From
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-01-17 17:00
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix asm checks regression due to recent middle-end
change
From: Pan Li
The recent middle-end change result in some asm check
OK
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 10:34
To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
CC: Kito Cheng
Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
Use "does not" rather than "cannot", because it's im
int8_t *...)
2. __riscv_vle8 (const uint8_t *...)
3. __riscv_vle8 (const int32_t *...) ---> I worry this will cause ICE since
pointer type doesn't match the expecting type,
I wonder whether it will cause ICE while resolving API.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-
Could you show me the ICE message ?
Is it in front-end ? If yes, it's ok.
I wonder whether it is "internal compiler error".
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-19 16:04
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer; zhengyu; pan2.li
Subject: Re: Re: [PATCH]
Thanks. I will commit V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/643420.html
after I finishing testing.
V2 no difference from V1 in codes except adding:
PR target/113495
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 16:19
To: Juzhe-Zhong
CC: gcc-patches
(test for errors, line )
FAIL: gcc.target/riscv/attribute-10.c -Os (test for excess errors)
Could you take a look at it ?
I am not sure whether they are caused by this patch. But I find only this
patch looks related.
juzhe.zh...@rivai.ai
LGTM.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 17:40
To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; jeffreyalaw;
christoph.muellner; juzhe.zhong; rep.dot.nop
CC: Kito Cheng
Subject: [PATCH v2] RISC-V: Documnet the list of supported extensions
Try to list all
zvl_unimplemented-2.c should also be fixed.
juzhe.zh...@rivai.ai
From: rep.dot.nop
Date: 2024-01-19 17:40
To: Kito Cheng; juzhe.zh...@rivai.ai
CC: Kito.cheng; jeffreyalaw; Robin Dapp; gcc-patches
Subject: Re: [PATCH] RISC-V: Tweak the wording for the sorry message
On 19 January 2024 03:41:57
Ok.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 18:08
To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
CC: Kito Cheng
Subject: [committed] RISC-V: Update testcase due to message update
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-27.c: Update scan message
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-22 12:11
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
From: xuli
v2:
Avoid internal ICE for the case below.
vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t
-O3 -g (test for excess errors)
FAIL: gcc.dg/torture/pr48124-4.c -Os (internal compiler error: in
reg_or_subregno, at jump.cc:1895)
FAIL: gcc.dg/torture/pr48124-4.c -Os (test for excess errors)
juzhe.zh...@rivai.ai
OK I guess change register_operand into REG_P should fix those ICEs.
I will have a try and send a patch.
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2024-01-22 15:14
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; kito.cheng; jeffreyalaw; vineetg; Robin Dapp;
palmer
No, we didn't undo the optimization.
We just disallow move pattern for (set (reg) (VL_REGNUM)).
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-22 19:25
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix regressions d
ok
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-24 08:50
To: gcc-patches
CC: juzhe.zhong; kito.cheng; law; rdapp; vineetg; Patrick O'Neill
Subject: [PATCH] RISC-V: Add regression test for vsetvl bug pr113429
The reduced testcase for pr113429 (cam4 failure) needed
-final { scan-assembler-not {csrr} } } */
This needs a XFAIL, I am not sure whether the spiling is reasonable, so XFAIL
this case.
We will analyze this case whether it is reasonable.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-25 15:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2
rv64 } */
/* { dg-require-effective-target riscv_v } */
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-24 09:20
To: juzhe.zh...@rivai.ai; gcc-patches
CC: kito.cheng; law; rdapp; vineetg
Subject: [Committed] RISC-V: Add regression test for vsetvl bug pr113429
The reduced testcas
It's fixed by this commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d40b3c1e439db05c835b6bd4fd5bba58fda71dd6
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-01-17 09:45
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Patrick O'Neill
Subject: Re: [Committed V2] RISC-V: Fix regressi
ok
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-27 10:50
To: gcc-patches
CC: juzhe.zhong; Patrick O'Neill
Subject: [PATCH] RISC-V: Add require-effective-target to pr113429 testcase
The pr113429 testcase fails with newlib spike runs. Adding
require-effective-targe
ot:
+ (match_operand: 4 "register_operand" " r, r, r, r")))
+ (match_operand:VI 2 "vector_merge_operand" "vu, vu, 0, 0")))]
+ "TARGET_ZVBB || TARGET_ZVKB"
+ "vandn.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "v
oups[i]);
+ }
I think it should be:
for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
if (avail)
builder.register_function_group (function_groups[i]);
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-13 17:12
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe
-intrinsic v0.11)?
Intrinsics stuff should be very safe.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-12-13 18:09
To: Feng Wang
CC: gcc-patches; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan
Subject: Re: [PATCH v2 1/4] RISC-V:Add crypto vector implied ISA info.
LGTM
On Wed, Dec 13, 2023 at 5
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-13 19:12
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai; pan2...@intel.com
Subject: [PATCH v2] RISC-V: Fix dynamic lmul tests depended on abi
Some toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or
_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
\
+ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO},
3. Recover all DEF_RVV_FUNCTION back to the original.
4. In the following vector crypto intrinsic, you should add like
DEF_RVV_CRYPTO_FUNCTION like aarch64 does
, my question is the COST should be 1 or 2.
It seems that COST = 1 is better for using SELECT_VL.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-13 18:17
To: Juzhe-Zhong
CC: gcc-patches; richard.sandiford; jeffreyalaw
Subject: Re: [PATCH] Middle-end: Adjust decrement IV sty
is better than COST=2.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-14 18:46
To: juzhe.zhong
CC: gcc-patches; richard.sandiford; jeffreyalaw
Subject: Re: [PATCH] Middle-end: Adjust decrement IV style partial
vectorization COST model
Am 14.12.2023 um 09:28 schrieb
Thanks Richard. Committed.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-14 23:10
To: Juzhe-Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH] Middle-end: Do not model address cost for SELECT_VL style
vectorization
On Thu, 14 Dec 2023, Juzhe-Zhong wrote:
> Fol
CCing Kito.
I am sorry I can't review ABI even though it is vector related, this patch
needs kito's review.
But I will be available on reviewing the following real vector BF16 intrinsic
and auto-vectorization support.
Thanks.
juzhe.zh...@rivai.ai
From: Xiao Zeng
Date: 2023-12-1
s but that will probably clash if there are more than
>>two npatterns.
No, we definitely can not use this. more details you can see the current test
vmerge-*.c .
We have various patterns:
E.g.
0, nunits + 1, nunits+ 2, ... it is 011
nunits, 1, 2 it 100.
....
Many different kinds of patte
ITSIZE (GET_MODE_INNER (vmode)) == 8、
&& indices_fit_selector_p
&& !vec_len.is_constant ())
return false;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-15 20:25
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PAT
<< GET_MODE_BITSIZE (GET_MODE_INNER (vmode)));
if (GET_MODE_BITSIZE (GET_MODE_INNER (vmode)) == 8
&& indices_not_fit_selector_p
&& !vec_len.is_constant ())
return false;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-15 20:25
To: juzhe.zh...@rivai.ai; gcc
r_p && !vec_len.is_constant ())
return false;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-15 20:44
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix vmerge optimization bug in vec_perm
vectorization
> Oh. I t
LGTM from my side.
Give kito 1 day to chime in,
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-18 11:28
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Add required_extensions in function_group
In order to add other vector related extensions in
Could you add -fno-schedule-insns -fno-schedule-insns2 ?
So that the test won't be fragile to break a again when we tune the scheduling
model and cost model.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-18 14:40
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-18 15:05
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] testsuite: Fix cpymem-1.c dump checks under different
riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base
check according to this suggestion.
Also, rename the test from const-vector-0.c into bug-7.c
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-18 15:04
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for the RVV const vector
From: Pan Li
OK. LGTM. It's an obvious fix and not easy to add the test (No need to add such
test).
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-18 15:35
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for the RVV const vector
From: P
Update in V2 with more information in commit log:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640863.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-18 18:59
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V
Thanks for refactor it. You can commit it today.
Thanks.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-18 11:28
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Add required_extensions in function_group
In order to add other vector related
OK。
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-19 09:44
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] testsuite: Fix cpymem-2.c dump checks under different
riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem
Looking at the implementation it's odd that we can handle
VECTOR_CST_NELTS_PER_PATTERN == 1 (duplicate) and
== 3 (stepped) but not == 2 (not sure what that would be).
Maybe the tests can be re-formulated in terms of
VECTOR_CST_NELTS_PER_PATTERN?
Richard.
> Thanks.
>
>
>
>
|| code == BIT_IOR_EXPR
|| code == BIT_XOR_EXPR);
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-12-19 17:12
To: juzhe.zh...@rivai.ai
CC: Robin Dapp; gcc-patches; pan2.li; richard.sandiford; Richard Biener; pinskia
Subject: Re: Re: [PATCH] fold-const: Handle AND, IOR, XOR with st
| code == BIT_IOR_EXPR
|| code == BIT_XOR_EXPR);
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-12-19 17:45
To: juzhe.zh...@rivai.ai
CC: rguenther; Robin Dapp; gcc-patches; pan2.li; richard.sandiford; Richard
Biener; pinskia
Subject: Re: Re: [PATCH] fold-const: Handle AND,
or RVV.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-19 18:40
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; Robin Dapp; gcc-patches; pan2.li; Richard Biener;
pinskia
Subject: Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors
[PR112971].
Richard Biener writes:
> O
hints ?
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2023-12-20 10:04
To: Richard Biener; juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; pan2.li;
Richard Biener; pinskia; richard.sandiford
Subject: Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors
[PR112971].
On Tue, Dec 19, 20
+ if (known_eq (ele_0 - 0, ele_n - v.npatterns ()))
->
for (i = 0; i < v.npatterns (); )
check each nelt of npatterns is equal to vid.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-20 10:39
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PA
ass rvv_builder
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-20 14:56
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; jeffreyalaw
Subject: [PATCH v2] RISC-V: Bugfix for the const vector in single steps
From: Pan Li
This patch would like to fix the below execution fail
tch_operand: 4 "register_operand" " r, r, r, r")))
->
+ (and:VI_QHS+ (not:VI_QHS+(vec_duplicate:VI_QHS
+(match_operand: 4 "register_operand" " r, r, r, r")))
+ (match_operand:VI_QHS 3 "register_operand" "vr, v
>> The description in the spec is"Each bit of Op1 is inverted and logically
>> ANDed with the corresponding bits in vs2",
>> so I think the "and" should be placed outside.
Ah. Yes.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-20 16:09
To
OK。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-20 17:35
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; jeffreyalaw
Subject: [PATCH v3] RISC-V: Bugfix for the const vector in single steps
From: Pan Li
This patch would like to fix the below execution failure when
LMUL (I am happy with those 2 cases be changed as using larger
LMUL )?
It seems this patch is ignoring the first vectorized statement during the live
calculation ?
Thanks.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2023-12-20 16:15
To: gcc-patches@gcc.gnu.org
CC: juzhe.zh...@rivai.ai;
I see. LGTM. Thanks for explanation.
I will ask Li Pan commit it for you.
Thanks.
juzhe.zh...@rivai.ai
From: Demin Han
Date: 2023-12-20 19:10
To: juzhe.zh...@rivai.ai; gcc-patches
CC: pan2.li
Subject: Re: [PATCH] RISC-V: Fix calculation of max live vregs
Hi juzhe,
The live ranges are
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