LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-04 20:26
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
From: Pan Li
This patch would like to take FRM_DYN const
Thank you for using intel's machines test it for me.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-07-05 19:15
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
CC: richard.sandif...@arm.com; rguent...@suse.de
Subject: RE: [PATCH V5] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE
LGTM. Thanks for fixing this.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-05 21:00
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Change truncate to float_truncate in narrowing
Hi,
Juzhe noticed that several floating
Thank you so much.
I have sent V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623734.html
which is working fine for both stride = constant and variable.
Could you take a look at it?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-06 14:43
To: Ju-Zhe Zhong
CC: gcc
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-07-07 16:22
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; Li Xu
Subject: [PATCH] RISCV: Fix local_eliminate_vsetvl_insn bug in VSETVL
PASS[PR110560]
This patch fixes this issue happens on GCC-13.
https://gcc.gnu.org
CCing Li Pan to backport this patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-07 17:04
To: juzhe.zh...@rivai.ai
CC: Li Xu; gcc-patches; palmer; zhengyu
Subject: Re: [PATCH] RISCV: Fix local_eliminate_vsetvl_insn bug in VSETVL
PASS[PR110560]
LGTM
On Fri, Jul 7, 2023 at 4
ng shift when combining it with
>>scale_log != 0?
RVV has widening shift? I didn't know that. Current natural approach is first
extend offset then shift.
>>instead. This avoid the (surprising) weird subreg being generated
>>at all and we don't need to ensure, probably redundant
>>When reading it I considered unifying both cases and have modulo_sel_indices
>>just do nothing when the constant already satisfies the range requirement.
>>Would that work?
I tried but it turns out to cause execution faile.
Sorry, I can try to refine this code.Thanks.
ju
Hi, Robin.
I have fixed all issues for you with V4 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623856.html
1. Apply your approach on poly int
2. Fix comments.
3. Normalize "modulo" codes and make it no redundancy.
...
Could you take a look at it?
Thanks.
juzhe.zh..
Hi, Richard.
I find out I just only need to export 'insert_insn_end_basic_block' for global
used by RISC-V port (current riscv-vsetvl.cc and future riscv.cc).
Does it look more reasonable ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-10 15:25
To: Ju-Zhe Zho
Sorry, I forget to add the patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623960.html
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-07-10 15:58
To: rguenther
CC: gcc-patches; jeffreyalaw
Subject: Re: Re: [PATCH] GCSE: Export add_label_notes as global function
Hi
block BB with
+ same instruction pattern with PAT. */
+rtx_insn *
+insert_insn_end_basic_block (rtx_insn *pat, basic_block bb)
Is it better ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-10 16:01
To: juzhe.zh...@rivai.ai
CC: gcc-patches; jeffreyalaw
Subject: Re: Re: [PATCH
Thanks Richi.
I added "BIAS" for you:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623978.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-10 18:40
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford; linkw; krebbel
Subject: Re: [PATCH] VECT: Add
Bootstraped and Regression on X86 last night with no surprise fails.
This patch has already included 'BIAS' argument.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-07-10 19:35
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V2]
with dummy mask = { -1, -1, ..., -1}.
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-07-11 09:17
To: Richard Biener
CC: gcc-patches; richard.sandiford; linkw; krebbel; Ju-Zhe Zhong; Segher
Boessenkool; David Edelsohn; Peter Bergner
Subject: Re: [PATCH] VECT: Add COND_LEN_* operations for
when preference fixed-vlmax[PR111857]
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vls-mode-6.c
Change all tests name into pr111857-1.c...etc.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-10-20 16:43
To: Richard Biener
CC: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang,
UNARY_OP_TAMU_FRM_DYN = UNARY_OP_TAMU | FRM_DYN_P,
UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P,
UNARY_OP_TAMU_FRM_RDN = UNARY_OP_TAMU | FRM_RDN_P,
Are they still necessary ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 09:26
To: gcc-patches
CC: juzhe.zhong; pan2.li
OK。 LGTM。
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-10-23 09:42
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for merging undefined tmp register in
math
Yes, it is required by the second cvt. The unmasked elements keep the
e" "vmov,vlde,vste")
(set_attr "mode" "")
(set (attr "avl_type") (const_int INVALID_ATTRIBUTE))])
We classify this pattern as vlde/vste/vmov, this pattern doesn't have AVL TYPE
operands.
I realize that when I am adding new pre-RA optimizatio
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 10:39
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove unnecessary asm check for rounding autovec
From: Pan Li
The vsetvl asm check is unnecessary for the rounding
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 15:53
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc
From: Pan Li
For trunc function autovec, there will be one step like below take MU
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 17:54
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove unnecessary asm check for vec cvt
From: Pan Li
The vsetvl asm check is unnecessary for the vector convert. We
should be
XFLAGS='-O0 -g3'
'CFLAGS_FOR_TARGET=-Os-mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-Os
-mcmodel=medany'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)
juzhe.zh...@rivai.ai
From: P
Fixed on trunk. Pl;z verify it.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-10-24 09:01
To: juzhe.zh...@rivai.ai; 丁乐华
CC: kito.cheng; Robin Dapp; palmer; jeffreyalaw; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
IIRC --enable-checking=yes does not
CCing Patrick...
Hi, @Patrick.
Could you apply this patch and trigger your regression CI?
I don't have an environment to test fortran for now (I only test it on C/C++).
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-24 11:32
To: gcc-patches
CC: kito.cheng; kito.
, 3, r0);
tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16);
r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0);
}
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-24 14:22
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Calling vget
Ok for trunk (You can commit it to the trunk now).
For GCC-13, I'd like to wait for kito's comment.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-24 15:29
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsi
vectype (slp_op, mask_vectype))
+ gcc_unreachable ();
}
As you can see, except MASK_LEN_GATHER_LOAD, other LOADs, I pass 'NULL' same as
before.
Only MASK_LEN_GATHER_LOAD passes '&slp_op'. It works fine for RVV. But I don't
think it's a correct code, we may need
hese tests like others.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 16:35
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite
Hi Juzhe,
I guess that's OK but what's the pr
all of these FAILs
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 16:35
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite
Hi Juzhe,
I guess that's OK but what's the pr
Hmmm. I am not familiar with Binutils...
I just adapted tests like others in the testsuite make them consistent.
And turns out it can fix the issues...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 16:44
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng
Committed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-25 16:35
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Change MD attribute avl_type into avl_type_idx[NFC]
Address kito's comments of AVL propagation patch.
C
Thanks. Committed with NFC mentioned.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-25 17:06
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Export some functions from riscv-vsetvl to riscv-v
LGTM, but plz mention it's NFC in the
I'm on other things.
No worry, I won't commit this patch. I will use this patch in my local.
You can fix it when you have time.
I don't know how to fix it since I am really noob about testing.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 17:15
To: juzhe
n-1.c execution test
These 2 already exist on the trunk for RV32.
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c
execution test
This FAIL for RV64 is odd. I don't have it. Could you share me the debug log ?
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date
er_load_run-11.c
execution test
I use SPIKE works fine. This is my SPIKE configuration
spike \
--isa=rv64gcv_zvfh_zfh \
--misaligned \
${PK_PATH}/pk${xlen} "$@"
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-10-26 09:22
To: juzhe.zh...@rivai.ai; gcc-patches
C
Ls).
I am not familiar with popcount, Robin. Any suggestions?
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-10-26 15:33
To: juzhe.zh...@rivai.ai; Patrick O'Neill; gcc-patches
CC: kito.cheng; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: RE: Re: [PATCH] RISC-V: Add AVL propagation PAS
Thanks Kito.
I have sent V3 with adapting testcases (2 additional dump FAILs detected by
both Pan Li and Patrick).
No need to review.
I will wait for patrick is ok to ignore popcount FAILs for now then commit it.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-26 15:51
To: Juzhe-Zhong
gi?id=111970
I guess they are related to make RVV GCC unstable, so testing various in
different machines.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-26 16:34
To: juzhe.zh...@rivai.ai; Kito.cheng
CC: rdapp.gcc; gcc-patches; kito.cheng; jeffreyalaw; Patrick O'Neill
Subject: Re: [PATCH
Hi, Richard.
I tried your pseudo code, but report a warning:
../../../../gcc/gcc/doc/invoke.texi:20243: warning: `.' or `,' must follow
@xref, not )
I have tried several changes, still failed to eliminate this warning.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-2
Oh. I made a mistake here.
Forget about my last email.
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634376.html
Here is the V2 address comments as you suggested.
Could you take a look ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-26 17:25
To: Juzhe-Zhong
Thanks Richard. Committed.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-26 17:56
To: Juzhe-Zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] DOC: Update COND_LEN document
Juzhe-Zhong writes:
> gcc/ChangeLog:
>
> * doc/md.texi: Adapt COND_LEN pseudo code.
O
scv-autovec-lmul=dynamic
--param=riscv-autovec-preference=fixed-vlmax
We will need your help of CI. Currently, it's still stage 1 and we are working
on pushing as many optimizations as possible.
Thanks.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-10-27 02:43
To: Robin
LGTM from my side.
The original integer division COST seems too low.
Hi, Jeff and Kito. Could take a look at this patch ?
Thanks.
juzhe.zh...@rivai.ai
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-27 15:38
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add rawmemchr expander.
> Suggested adapt codes as follows:
>
> unsigned int element_size = GET_MODE_S
I notice we have expand_block_move
in riscv-v.cc
Maybe we should move it into riscv-string.cc ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-27 15:51
To: Kito Cheng; juzhe.zh...@rivai.ai
CC: rdapp.gcc; gcc-patches; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add rawmemchr
LGTM as long as you add HONOR_SNANS
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-31 03:26
To: Joseph Myers
CC: rdapp.gcc; gcc-patches; palmer; Kito Cheng; jeffreyalaw;
juzhe.zh...@rivai.ai
Subject: Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.
> Aren't they actually
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-31 11:39
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Add the missed combine of [u]int64 -> _Float16 and
vcond
Hi,
This patch let the INT64 to FP16 convert split
LGTM from my side.
Give kito one more day to review it.
Thanks for support this feature !
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-31 17:03
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV
intrinsic
From
Thanks Robin. Address comments on V2.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-31 16:45
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; richard.sandiford; rguenther; jeffreyalaw
Subject: Re: [PATCH] OPTABS/IFN: Add
mask_len_strided_load/mask_len_strided_store OPTABS/IFN
Hi Juzhe
It is new vectorization optimization which needs middle-end patches.
I believe you didn't apply these following 2 patches:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634812.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634813.html
juzhe.zh...@rivai.ai
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-01 14:35
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Support vundefine intrinsics for tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-02 08:54
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog
update with more dump information in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/634950.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-02 11:06
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix redundant
_vectype))
return false;
+ /* MASK_LEN_GATHER_LOAD dummy mask -1 should always match the
+MASK_VECTYPE. */
+ if (mask_index >= 0 && slp_node && mask_dt == vect_constant_def
+ && !vect_maybe_update_slp_op_vectype (slp_op, mask_vectype))
+
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-03 11:26
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Refactor prefix [I/L/LL] rounding API autovec
iterator
From: Pan Li
Update in v2:
* Add mode size equal check to disable
Does it look reasonable ? Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-02 22:34
To: 钟居哲
CC: gcc-patches; Jeff Law; richard.sandiford; rdapp.gcc
Subject: Re: Re: [PATCH V2] OPTABS/IFN: Add
mask_len_strided_load/mask_len_strided_store OPTABS/IFN
On Thu, 2 Nov 2023, ??? wrote:
&
ve(tail or unmasked) elements, I
am wondering whether it will cause issues.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-03 15:40
To: juzhe.zh...@rivai.ai
CC: gcc-patches; jeffreyalaw; richard.sandiford; Robin Dapp
Subject: Re: Re: [PATCH V2] OPTABS/IFN: Add
mask_len_strided_load/m
. Operand 0 is the vector to modify,
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-03 15:40
To: juzhe.zh...@rivai.ai
CC: gcc-patches; jeffreyalaw; richard.sandiford; Robin Dapp
Subject: Re: Re: [PATCH V2] OPTABS/IFN: Add
mask_len_strided_load/mask_len_strided_store OPTABS/I
Sorry.
This is middle-end patch, sending to wrong CC lists.
Forget about this patch.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 14:52
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] VECT: Support mask_len_strided_load
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-06 16:33
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Adjust FP rint round tests for RV32
From: Pan Li
The FP rint test cases for RV32 need some additional adjust
for types and data
Testcase already existed on the trunk, which is added by Li Pan added recently
when supporting rounding mode autovec.
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635280.html
math-llrintf-run-0.c passed on RV64 but cause ICE on RV32.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date
data loaded by VNx8BI (vbool8_t ) in VNx4BI (vbool16_t ).
In this example, GCC thinks data loaded for vbool8_t v3 can be replaced by
vbool16_t v4 which is already loaded
It's incorrect for RVV.
Maybe @kito can give us more information about RVV ISA if I don't explain it
clearly.
juzhe
I am not sure changing the precision inner mode of BImode is correct for RVV.
Since by definition , each single 1-bit mask in RVV mask layout are consecutive.
Maybe we can wait for Kito answer this question ?
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-13 16:46
To: juzhe.zh
itsize are different but byteszie are all same.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-02-13 17:41
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; incarnation.p.lee; gcc-patches; Kito.cheng; ams
Subject: Re: [PATCH] RISC-V: Bugfix for mode tieable of the rvv bool types
Richard
: both vlm.v are loading same address)
Such asm will not happen in GCC. It will become like this since bool modes are
tied:
vsetvl e8,mf8
vlm.v v8, a0 (v8 is a 8-bit mask)
vsm.v v8,a0
vsm.v v8,a1
I am not sure whether it's correct. Maybe I should ask RVV ISA community.
juzhe.zh...@riv
ompile-time unknown)
vsm.v v8,a2
(Note: both vlm.v are loading same address)
Such asm will not happen in GCC. It will become like this since bool modes are
tied:
vsetvl e8,mf8
vlm.v v8, a0 (v8 is a N x 1-bit mask, N is compile-time unknown))
vsm.v v8,a0
vsm.v v8,a1
Such asm codegen is
quite huge and not easy to maintain.
So.. I think I can reduce the tests into 1/3 of them in the next. But it's
still very big (you can take a look at LLVM).
Let's see whether kito has more comments about it.
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-02-16 17:38
To: j
s the mature and better test-generator (much better than mine)
to commit since rvv-intrinsic doc is their work.
As long as we can make kito's test-generator embedded into GCC regression, this
issue will be fixed. And I believe we can fix it soon.
So...Let's wait for kito.
juzhe.zh...@
and
VSETVL PASS) of RVV now.
Now, I am pulling as many resources as possible to do the testing.
From now to April (until GCC 14 is open), I will only keep testing and fix bugs
or some codes refine && simplification.
I won't push any more features especially autovec until GCC 14 is open
d to adjust the precision btw.
>
> Richard.
>
> > Thanks.
> > Replied Message
> > From
> > incarnation.p@outlook.com
> > Date
> > 02/16/2023 23:12
> > To
> > gcc-patches@gcc.gnu.org
> > Cc
> > juzhe.zh...@rivai.ai,
>
e 2/8 byte, 4/8 byte, 1/8 bytes. I think we can't
access in bit alignment. so they will the same in the access.
However, if VNx8BI occupty 8 byte, Well, VNx2BI,VN4BI, VNx1BI are 1byte,
2bytes, 4bytes. They are accessing different size.
This is my comprehension of RVV ISA, feel free to corre
?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-01 20:03
To: 盼 李 via Gcc-patches
CC: 盼 李; juzhe.zhong\@rivai.ai; pan2.li; Kito.cheng; rguenther
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
盼 李 via Gcc-patches writes:
> Just have a test with
Fortunately, we won't have aggregates, arrays of vbool*_t in the future.
I think it's not an issue.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-02 16:25
To: juzhe.zhong
CC: richard.sandiford; pan2.li; gcc-patches; Pan Li; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugf
the
whole poly (1,1) size.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-02 17:39
To: juzhe.zhong\@rivai.ai
CC: rguenther; pan2.li; gcc-patches; incarnation.p.lee; Kito.cheng
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks for the explanation a
Thank you for fixing this. I am not familiar with this.
This generator code (genrvv-type-indexer.cc) is written by @kito.
Kito ? Can you take a look at this?
juzhe.zh...@rivai.ai
From: Sam James
Date: 2023-03-14 08:23
To: gcc-patches
CC: Kito Cheng; Palmer Dabbelt; Andrew Waterman; Jim
Kito commit patch for me.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-15 02:13
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fix Bug 109092
On 3/13/23 08:17, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> This patch fix bug: https://gcc.gn
to make it into GCC-13.
More patches I am gonna to send are going to expected to be merged into GCC-14.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-15 02:08
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fine tune gather load RA constraint
On 3/1
ke sure each file has a newline at the end of file.
After these change, it LGTM.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-05-10 10:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions sati
LGTM. Let's wait for kito's feedback.
Thanks :)
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-05-10 12:02
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfying REG_P(operand[1]) in
This part LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-10 23:24
To: gcc-patches; juzhe.zh...@rivai.ai; Kito Cheng; Michael Collison; palmer;
jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] riscv: Clarify vlmax and length handling.
Hi,
this patch tries to improve the wrappers that
LGTM.
The whole implementation is your own work, but tests are mostly base on Michael
so add Michael as co-author in testcase patch and then commit.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-10 23:24
To: gcc-patches; juzhe.zh...@rivai.ai; Kito Cheng; Michael Collison; palmer
Thank you so much.
Can you take a look at this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618110.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 12:50
To: 钟居哲
CC: gcc-patches; rguenther
Subject: Re: [PATCH V4] VECT: Add decrement IV iteration loop
OK, thanks for Richard Sandiford.
Waiting for Richard Biener comment before commit.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 16:14
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V5] VECT: Add tree_code into "creat_iv" and allow it can
handle
length () == 1.
When it is loop_lens->length () != 1, it means it is Case 2 or Case 3. We
always force MIN_EXPR using VF in non-final iteration.So the data reference IV
is added by constant value (poly or non-poly). Maybe the codes here is ugly
with using loop_lens->length () == 1?Could you
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:27
To: Kito Cheng; Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
Subject: [PATCH v2] RISC-V: Add autovectorization tests for binary integer,
operations
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:29
To: Kito Cheng; Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
Subject: [PATCH v2] RISC-V: Clarify vlmax and length handling.
Changes from v1:
- Change
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:33
To: Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; Kito Cheng; collison; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Split off shift patterns for autovectorization
LGTM. You should commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:26
To: 钟居哲; gcc-patches; kito.cheng; Michael Collison; palmer; Jeff Law
CC: rdapp.gcc
Subject: [PATCH v2] RISC-V: Add vectorized binops and insn_expander helpers
I just saw Kito has LGTM in V1 patch.
Let's wait for Kito LGTM for V2.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:36
To: juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; collison; palmer; jeffreyalaw
Subject: Re: [PATCH v2] RISC-V: Add vectorized binops and insn_expander he
Oh, I see. But I saw there is a variable using_partial_vectors_p
in the loop data structure.
Can I add a variable call using_select_vl_p ?
Since it may increase the size of data structure, I am not sure whether it is
appropriate.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date
: rgc->max_nscalarper_iter != 1
Case 3 : rgc->max_nscalarper_iter == 1 but rgc->factor != 1?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 19:29
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V4] VECT: Add decrement IV iteration loop control by
v
This patch has tested on both RV32/RV64, and all fails in RVV are cleaned up.
Ok for trunk?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-12 07:29
To: gcc-patches
CC: kito.cheng; palmer; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix RVV binary auto-vectorizaiton test fails
From
sending patch for GCC
to make sure
the implementation is correct.
The slidedown method is totally the same as LLVM.
Sorry about that, I won't send any information related to LLVM gain. Thanks :)
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-12 10:23
To: juzhe.zhong
CC: gcc-pa
vec_init is auto-vectorization pattern.
The test is not loop since using vector type is easier to test the patterns.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-12 16:53
To: Li, Pan2; Kito Cheng; juzhe.zh...@rivai.ai
CC: gcc-patches@gcc.gnu.org; pal...@dabbelt.com; jeffreya
The implementation is copied directly from ARM SVE.
I applied in my downstream GCC for a year and there is no issue so far.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-13 19:44
To: gcc-patches
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH
prefer the second approach ? Then I can send
V2 patch.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-15 10:38
To: juzhe.zh...@rivai.ai
CC: gcc-patches; palmer; Robin Dapp; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support
TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize co
Hi, address comment and send V2 patch here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618477.html
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-15 10:56
To: juzhe.zh...@rivai.ai
CC: gcc-patches; palmer; Robin Dapp; jeffreyalaw
Subject: Re: Re: [PATCH] RISC-V: Support
The implementation LGTM.
But I am not sure testcase since we don't include any intrinsic API testcases
in GCC testsuite.
I think it needs Kito's decision.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-05-15 11:14
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yan
Thanks. Can you take a look at this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618398.html
This has been fixed 5 rounds. I already fixed it as you suggested
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-15 13:01
To: 钟居哲
CC: GCC Patches; Kito Cheng; Palmer Dabbelt; Palmer
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