I have sent V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617504.html
adding more comments.
Is that OK?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-05 14:21
To: juzhe.zhong
CC: gcc-patches; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Fix PR109615
Could you
Yeah, you should also swap mode and code in rtx_def according to Richard
suggestion
since it will not change the rtx_def data structure.
I think the only problem is the mode in tree data structure.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-06 09:53
To: Li, Pan2
CC: Richard Biener
Gentle ping this patch.
Is this Ok for trunk? Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-06 19:14
To: gcc-patches
CC: kito.cheng; Juzhe-Zhong
Subject: [PATCH] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli
[PR 109743]
From: Juzhe-Zhong
This patch is
vendor wants to degenerate select_vl to min, it can
>>just adopt the same
>>handlings with min by not defining select_vl optab.
You mean like this:
doing this inside vect_set_loop_controls_directly ?
if (use_while_len_p)
return vect_set_loop_controls_by_while_len (..
incorporate those
codes into "vect_set_loop_controls_directly" when they
finish the review process of "vect_set_loop_controls_by_select_vl".
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-05-08 15:55
To: juzhe.zh...@rivai.ai
CC: gcc-patches; rguenther; richard.sandiford
Subject: Re
Hi，Richards. Would you mind reviewing this patch?
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-05-07 23:19
To: juzhe.zhong; gcc-patches
CC: richard.sandiford; rguenther
Subject: Re: [PATCH V4] VECT: Add decrement IV iteration loop control by
variable amount support
On 5/4/23 07
I understand the concern, the current implementation are in the isolated
function "vect_set_loop_controls_by_select_vl",
it's easier to review the implementation.
Maybe we can first make the whole implementation codes in
"vect_set_loop_controls_by_select_vl" to be stable after review,
then
CPROP remove the second the "pred_broadcast" instruction and
propagate the result to the second "pred_add" instruction。
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-01 20:40
To: Ju-Zhe Zhong
CC: gcc-patches; kito.cheng; richard.sandiford; jeffreyalaw; apinski
Subje
t sure
whether CSE can propagate the 151 pseudo
to the second pred_add ??
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-01 20:51
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng; richard.sandiford; jeffreyalaw; apinski
Subject: Re: Re: [PATCH] CPROP: Allow cprop optimization wh
ass [VL_REGNUM] = NO_REGS;
riscv_regno_to_class [VTYPE_RENUM] = NO_REGS;
The CSE now can do the optimization now!
1) Would you mind telling me the difference between them?
2) If I set these 2 global status register as NO_REGS, will it create issues
for the global status configuration of each RVV in
Thank you so much. Kito helped me fix it already.
RVV instruction patterns can have CSE optimizations now.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-02-02 20:26
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng; richard.sandiford; jeffreyalaw; apinski
Subject: Re: Re: [PATCH
Sorry for the wrong title, it should be add vwsubu.wv C API tests
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-02-07 14:17
To: gcc-patches
CC: kito.cheng; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Add vwsubu.wx C API tests
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target
This ICE is introduced by this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606523.html
PLCT lab is helping with this bug fix.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2022-11-20 17:24
To: juzhe.zhong
CC: gcc-patches; monk.chiang; kito.cheng
Subject: Re: [PATCH] RISC
evert it. Thanks
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2022-11-21 16:38
To: schwab
CC: gcc-patches; monk.chiang; kito.cheng; jiawei
Subject: Re: Re: [PATCH] RISC-V: Add RVV registers register spilling
This ICE is introduced by this patch:
https://gcc.gnu.org/pipermail/gcc-patch
Yeah, I personally want to support RVV intrinsics in GCC13.
As RVV intrinsic is going to release soon next week.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2022-11-29 09:38
To: Jeff Law
CC: 钟居哲; gcc-patches; palmer
Subject: Re: [PATCH] RISC-V: Add attributes for VSETVL PASS
Actually, I am
In case of RVV intrinsic support, there is no changes outside RISC-V backend
since we don't do the autovectorization support for now.
I will postpone autovectorization until GCC14 is open.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2022-11-29 10:56
To: juzhe.zhong
CC: Kito
It's ok to defer them GCC-14. I will keep testing and fix bugs during these 2
months.
I won't support any more feature or optimizations until GCC-14 is open.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-20 00:55
To: juzhe.zh...@rivai.ai; gcc-patches
CC: kito.cheng
Subject:
The last patch. Kito is still keep testing with pressure tests.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-20 01:03
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fix bugs of ternary integer and floating-point
ternary intrinsics.
On 3/15/23 00:37
upporting RVV auto-vectorization. I think we can have a sync up meeting
(share my current new ideas) before I start to support RVV auto-vectorization
before GCC 14.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-03-18 00:57
To: gcc-patches; Vineet Gupta
CC: Kito Cheng; collison; juzhe.
sues, would you mind looking at this
issue?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108016
Thanks.
juzhe.zh...@rivai.ai
sues, would you mind looking at this
issue?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108016
Thanks.
juzhe.zh...@rivai.ai
Thanks Richard && Pan.
Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I
have write access now).
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-29 17:24
To: pan2.li
CC: gcc-patches; juzhe.zhong; kito.cheng; yanzhang.wang
Subject: Re: [PATCH v2
s.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-03 12:13
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix SEW64 of vrsub.vx runtime fail in RV32 system
On 4/2/23 18:38, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> It's quit
riscv_vector {
+extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
+}
namespace riscv_vector should be put in the riscv-protos.h. Since there is
already a riscv_vector namespace there.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2023-04-06 21:34
To: gcc-patches
CC: juzhe.zhong
Address all comments, and fix all of them in these splitted patches:
These 5 patches only including RISC-V port changes:
https://patchwork.sourceware.org/project/gcc/patch/20230407011143.46004-1-juzhe.zh...@rivai.ai/
https://patchwork.sourceware.org/project/gcc/patch/20230407012129.63142-1
Hi, I have checked SDnode in LLVM which is a similiar data structure with RTX
in GCC.
The SDnode in LLVM occupy 80bytes.
Can we have some tool to test the memory consuming of the whole GCC with
extended-size RTX?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-11 04:42
To: juzhe.zhong
nd fusion generate a new vsetvl instructions "vsetvl e8,mf8,TU"
which is available for both RVV instructions "vadd" and "vle",
and update the first vsetvl "vsetvl e8,mf8,TA" to "vsetvl e8,mf8,TU"
Then, I tell LCM "vsetvl e8,mf8,TU" is
quot;vint8mf8x3_t", I don't known
how to define such instruction RTL pattern. Should its dest operand mode be
BLKmode?
But we want the dest operand is a register operand.
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-04-11 17:16
To: juzhe.zhong
CC: Jeff Law; gcc-patches; kito.che
?
Thanks for all comments.
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-04-11 17:59
To: juzhe.zhong; Jeff Law; gcc-patches; kito.cheng; palmer; rguenther;
richard.sandiford
Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to
16-bit
On Tue, Apr 11, 2023 at 10:46
rand 0)
(set dest operand 1)
(set dest operand 2)...])
...
NF = 7:
define_insn "vlseg7"
[(parallel_with_continguous_reg
(set dest operand 0)
(set dest operand 1)
(set dest operand 2)
(set dest operand 2)
(set dest operand 2)...])
juzhe.zh...@rivai.ai
From: Jakub Jel
9 bit (512 modes) mode should be enough for RVV.
In the future, I would expect we will have BF16 vector, FP16 vector,.. matrix
modes.
And I think it will not be more 512 modes in the future.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-11 19:11
To: Richard Biener
CC
the SEW/LMUL ratio is not enough.
Some instructions like comparison instructions, they don't care about tail
policy
Some instructions like vmv.x.s, doesn't care about VL.
etc.
Quite complicated, so we have defined several fusion rules in VSETVL PASS
juzhe.zh...@rivai.a
Hi, Richards.
Kindly Ping this patch.
This is the most important patch for RVV auto-vectorization support.
Bootstraped on X86 has passed.
Feel free to comments.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-04-07 09:47
To: gcc-patches
CC: richard.sandiford; rguenther
is the only mask
register to predicate RVV operation
vle32.v v25,(a1),v0.t
vadd.vv v24,v24,v25
vse32.v v24,(a0),v0.t
add a2,a2,a4
add a0,a0,a4
add a1,a1,a4
bne a3,zero,.L3
.L1:
ret
This is the how RVV works.
Feel free
nerated
by comparison)
I think we can CC IBM folks to see whether we can make WHILE_LEN works
for both IBM and RVV ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-12 16:42
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches; jeffreyalaw
Subject: Re: Re: [PATCH] V
Sorry for incorrect typo.We can predicate vadd.vv with v1 - v31.
>
We can't predicate vadd.vv with v1 - v31.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-04-12 17:15
To: rguenther
CC: richard.sandiford; gcc-patches; jeffreyalaw
Subject: Re: Re: [PATCH] VECT: Add W
related
addressing-mode choosing.
I think I must missed something, would you mind giving me some hints so that I
can study on ivopts
to find out which case may generate inferior codegens for varialble IV step?
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-12 19:17
V hardware and the open-source
simulator generate "vl" = VLMAX. (Sorry about that)
Expecting any suggestions and comments.
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-13 14:47
To: 钟居哲
CC: richard.sandiford; gcc-patches; Jeff Law; rdapp; linkw; kito.chen
\s+v[0-9]+,\s*v[0-9]+} } } */
It's better add more assembler check
check how many vmclr.m or vmset.m should be.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-04-14 10:32
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; pan2.li
Subject: [PATCH] RISC-V: Add test cases for the RVV
LGTM. Wait for Kito more comments.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-04-14 10:45
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; pan2.li
Subject: [PATCH v2] RISC-V: Add test cases for the RVV mask insn shortcut.
From: Pan Li
There are sorts of shortcut codegen for
e basically agree with the concept of this patch?
Would you mind giving more suggestions that I can fix this patch to make more
benefits for IBM (s390 or rs6000)?
For example, will you try this patch to see whether it can work for IBM in case
of multiple rgroup of SLP?
Thanks.
juzhe.zh...@riva
hat we can switch to this flow ?
Is it more reasonable ?
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-04-14 10:54
To: 钟居哲
CC: gcc-patches; Jeff Law; rdapp; richard.sandiford; rguenther
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Hi Ju
backend patches on vector with length
>> exploitation since
>> the existing vector with length support already works well on functionality.
Ok, I get your point. I am gonna refine the patch to make it work for both RVV
and IBM.
Thanks all your comments.
juzhe.zh...@rivai.ai
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