Thanks Richi. I am gonna merge it after Richard's final approve.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-02 16:56
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; linkw
Subject: Re: [PATCH V3] VECT: Change flow of decrement IV
On Thu, 1 Jun 2023, juz
Oh there is 2 INTVAL (op) == GET_MODE_MASK...
I only change one :)
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2023-06-02 17:29
To: juzhe.zhong
CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Fix warning in predicated.md
Hi, I fixed it :
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620462.html
Just feel free to commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2023-06-02 17:29
To: juzhe.zhong
CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re
flow of single-rgoup:
...
length = min (vf)
...
vsetvli zero. length <=== insert by VSETLVI PASS
load (pointer IV)
vadd.
...
pointer IV = pointer IV + VF
I want to optimize it into:
...
length = vsetvli (Vf)
... <=== not need to insert vsetvlli.
load (pointer IV)
vadd.
...
pointer IV =
ame
+DEF_RVV_WCONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_WCONVERT_U_OPS (vuint32m1_t, 0)
+DEF_RVV_WCONVERT_U_OPS (vuint32m2_t, 0)
+DEF_RVV_WCONVERT_U_OPS (vuint32m4_t, 0)
+DEF_RVV_WCONVERT_U_OPS (vuint32m8_t, 0)
same
Otherwise, LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023
n "vsetvli "?
"vsetvli zero" is the same cost as "vsetvli gpr",
I think for (b), solution 2 and solution 3 should be almost the same.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-06-05 15:57
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenth
Thanks for catching this.
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-05 16:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in
vector-iterators.md.
gcc/ChangeLog:
*
LGTM,
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-05 16:20
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point
t's more comprehensive than I wrote.
I will send V3 patch with appending your comments.
Thanks you so much!
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-06-05 18:09
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] VECT: Add SELECT_VL support
"juz
Hi, Richard and Richi.
Thanks for the help.
This patch is boostrap PASS. Ok for trunk？
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-05 18:30
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V3] VECT: Add SELECT_VL support
From: Ju-Zhe Zhong
Co-authored
More update, just passed regression on X86.
Thanks.
juzhe.zh...@rivai.ai
发件人： juzhe.zh...@rivai.ai
发送时间： 2023-06-05 18:40
收件人： 钟居哲; gcc-patches
抄送： richard.sandiford; rguenther
主题： Re: [PATCH V3] VECT: Add SELECT_VL support
Hi, Richard and Richi.
Thanks for the help.
This patch is boostrap
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-05 22:49
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point
intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH
Oh. YES. Thanks for catching this.
VF will be used in autovec for example: vfadd.
When specify zfhmin, the vfadd autovec will be enabled unexpectedly.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-06 09:32
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang
I think we should split instructions pattern which belongs to ZVFHMIN.
And add ZVFH gating into all original iterator for example: VF VWFetc.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-06 09:32
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang
Subject
addiw a5,a5,3
> sb a5,799(a0)
> ret
Ideally, this scalar codes should be able to vectorized like aarch64.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-06 14:55
To: juzhe.zhong
CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw;
rd
reasonable.
I didn't have the time take a look at how LLVM do now but I will take a look at
it in the future.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-06-02 19:43
To: juzhe.zhong\@rivai.ai
CC: rguenther; gcc-patches; linkw
Subject: Re: [PATCH V3] VECT: Change fl
Ping this patch. Ok for trunk ?
Since following patches are blocked by this.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-06 12:16
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li;
Juzhe-Zhong
Subject: [PATCH] RISC-V: Support RVV VLA SLP
LGTM.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-07 10:22
To: pan2.li
CC: gcc-patches; juzhe.zhong; kito.cheng; yanzhang.wang; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Fix ICE when include riscv_vector.h with rv64gcv
lgtm, thanks for fixing this :)
On Wed, Jun 7, 2023 at 10:19 AM Pan
To make sure we won't break and cause ICE.
Committed soon.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-07 10:38
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; palmer; palmer; jeffreyalaw; Robin Dapp; pan2.li
Subject: Re: [PATCH] RISC-V: Support RVV VLA SLP auto-vectorizatio
mp; TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-07 11:00
To: gcc-
s - 1 the bump is actually exactly VF?
Yes, we only do the SELECT_VL for single-rgroup, so ncopies should always be 1.
For ncopies != 1, we always use VF.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-07 15:41
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject
I am not sure for load/stores of FP16 vector should be gated by ZVFHMIN or ZVFH?
Since IMHO, load/stores of FP16 is no different from load/stores of INT16?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-07 16:06
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang
& riscv_vector::float_mode_supported_p (mode)"
"vf.vv\t%0,%3,%4%p1"
[(set_attr "type" "")
(set_attr "mode" "")])
bool
float_mode_supported_p (machine_mode mode)
{
if (GET_MODE_INNER (mode) == HFmode)
return TARGET_ZVFH;
ret
Hi, Richi. Since SELECT_VL only apply on single-rgroup (ncopies == 1 && vec_num
== 1)
Should I make SELECT_VL stuff out side the loop?
for (i = 0; i < vec_num; i++)
for (j = 0; j < ncopies; j++)
....
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-07 15:41
To
Rename float_point_mode_supported_p into float_mode_supported_p
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-08 14:06
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang
Subject: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li
This
LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16
autovec.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-08 14:29
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v8] RISC-V: Refactor requirement of ZVF
Bootstrap && Regression PASSed
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-08 10:05
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V5] VECT: Add SELECT_VL support
From: Ju-Zhe Zhong
Co-authored-by: Richard Sandiford
Co-aut
Oh. Good suggestion. It's much better than my solution I think.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-08 15:58
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Robin Dapp; jeffreyalaw; yanzhang.wang
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHM
tr "type" "vfalu")
(and eq_attr "mode" "VNx1HF")
(match_test "!TARGET_ZVFH")))
(const_string "no")
]
(const_string "yes")))
I think you can do experiment with this to see whether it can disable MD
pattern.
juzh
t;)
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+(const_string "yes")
+
+(and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VN
t;yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
I think it should not be changed.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-09 14:23
To: juzhe.zh..
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-09 15:07
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li
This patch would like to refactor the requirement
Ok.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-09 15:53
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix one warning of frm enum.
From: Pan Li
This patch would like to fix one warning similar as below, and add
re not using SELECT_VL, we always use VF.
>>Can't this be done in vect_get_data_ptr_increment by instead
>>of using VF for LOOP_VINFO_USING_SELECT_VL_P use
>>vect_get_loop_len () and so only change one place?
oK, I will try that in V6 patch.
Thanks.
juzhe.zh...@rivai.
Hi, Richi. I have fixed by following your suggestions
Could you take a look at it?
V6 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621122.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-09 16:13
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject
Just finish running Boostrap on X86 has passed.
Ok for trunk?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-09 16:39
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V6] VECT: Add SELECT_VL support
From: Ju-Zhe Zhong
Co-authored-by: Richard
This patch removed 2nd time initialization of RTL_SSA which is the approach we
both hate.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-09 18:45
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li
Subject: Re: [PATCH V2] RISC-V: Rework Phase 5
Thanks, Richi.
Should I wait for Richard ACK gain ?
Since the last email of this patch, he just asked me to adjust comment no codes
change.
I am not sure whether he is ok.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-09 19:02
To: Ju-Zhe Zhong
CC: gcc-patches
Thanks a lot Richi.
Even though last time Richard asked me no need to wait for 2nd ACK,
I am still want to wait for Richard final approval since I am not sure this
patch is ok for him.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-09 19:02
To: Ju-Zhe Zhong
CC: gcc-patches
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-12 10:57
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul
trunc
From: Pan Li
This patch would like to add more
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-12 15:40
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16
Ok. Add comments in V2 patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-12 17:39
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add ZVFHMIN autovec block testcase
Hi Juzhe,
no complaints here. Just
/2023-February/612574.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-12 17:51
To: 钟居哲; gcc-patches
CC: rdapp.gcc; kito.cheng; palmer; Jeff Law
Subject: Re: [PATCH] RISC-V: Fix V_WHOLE && V_FRACT iterator requirement
> + (VNx16QI "TARGET_MIN_VLEN <= 128
Is this patch ok for trunk?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-12 10:41
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectorization
From: Juzhe-Zhong
(match_operand: 2 "register_operand"))
(sign_extend:VWEXTI
(match_operand: 3 "register_operand")))
(match_operand:VWEXTI 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_in
Ok.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/thread.html
I have add comments as you suggested.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-13 07:21
To: juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc; pan2.li
Subject: Re: [PATCH V2] RISC-V
ntion for fixed-vlmax.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-13 03:16
To: Robin Dapp; gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai
Subject: Re: [PATCH] RISC-V: Implement vec_set and vec_extract.
On 6/12/23 08:55, Robin Dapp wrote:
> Hi,
>
> this implements t
Oh. Sorry. Since I want to commit my patch so I asked Pan to commit your test
as well.
I think you can resend a fix of this testcase and drop this patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-13 15:20
To: pan2.li; gcc-patches
CC: rdapp.gcc; juzhe.zhong; jeffreyalaw
(How about some assembly checks for the non-run tests?
No, I tried. I can't add assembly check in the tests since we are SLP using
different LMUL.
Different LMUL will end up with different SLP style and their instructions are
quite different.
Unless we can have assembly check with predicate
Send V2 patch with changelog.
Thanks.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-13 18:53
To: gcc-patches; juzhe.zhong
Subject: [PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`
Hi,
This patch remove the duplicate `#include "riscv-vector-switch.
LGTM.
Thanks.
Will merge it soon.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-13 18:59
To: gcc-patches; juzhe.zhong
Subject: [PATCH V2] RISC-V: Remove duplicate `#include
"riscv-vector-switch.def"`
Hi,
This patch remove the duplicate `#include "riscv-vector-switch.
/store) is
blocked which is prerequisite for reduction
if you understand how reduction works.
Maybe next you could find the way to optimize vv->vx ?
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-13 20:00
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; pal
-march=zve32*)
vsetvli ...e64,m1
vmv.v.x/vmv.s.x
We can't support such code sequence.
You should demonstrate it clearly in the comments.
Otherwise, this patch LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-14 08:58
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jef
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-14 10:15
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split
From: Pan Li
This patch is considered as the follow
issues. So, we can go ahead.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-14 14:09
To: Li, Pan2; juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; jeffreyalaw; Wang, Yanzhang; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for
define_insn_and_split
H
ps://gcc.gnu.org/pipermail/gcc-patches/2023-June/621610.html can fix these 2
issues?
If yes, please send V2 patch with append these information into patch log.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-14 14:52
To: juzhe.zh...@rivai.ai; pan2.li; gcc-patches
CC: rdapp.g
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-14 15:16
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add (u)int8_t to binop tests.
Hi,
this patch adds the missing (u)int8_t types to the binop tests.
I suggest in the
glish speaker, I'd like to see Jeff or Robin comments
that.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-14 15:29
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for vec_init repeating auto vector
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-14 17:00
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v3] RISC-V: Bugfix for vec_init repeating auto vectorization in
RV32
From: Pan Li
When constructing a vector mask from
Add PR target/pr110119
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-14 18:34
To: gcc-patches; juzhe.zhong
Subject: [PATCH] RISC-V: Fix PR 110119
Hi,
This patch fix the PR 110119.
The reason for this bug is that in the case where the vector register is set
to a fixed length (with
Thanks for fixing this.
This patch let RVV type (both vector and tuple) return in memory by default
when there is no vector ABI support.
It makes sens to me.
CC more RISC-V folks to comments.
Thanks.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-14 19:03
To: gcc-patches; juzhe.zhong
riscv_v_ext_tuple_mode_p
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-14 19:03
To: gcc-patches; juzhe.zhong
Subject: [PATCH] RISC-V: Ensure vector args and return use function stack to
pass [PR110119]
Hi,
The reason for this bug is that in the case where the vector register is set
to a fixed length (with
Also
p110119-1.c
change name of test into
pr110119-1.c
juzhe.zh...@rivai.ai
发件人： juzhe.zh...@rivai.ai
发送时间： 2023-06-14 19:17
收件人： 丁乐华; gcc-patches
抄送： jeffreyalaw; Robin Dapp; palmer
主题： Re: [PATCH] RISC-V: Ensure vector args and return use function stack to
pass [PR110119]
Oh. I see.
Change
\ No newline at end of file
Add newline for each test.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-14 19:33
To: 钟居哲; gcc-patches
CC: Jeff Law; Robin Dapp; palmer
Subject: Re: [PATCH] RISC-V: Ensure vector args and return use function stack
to pass [PR110119]
Fix all comment from
LGTM now. Thanks for fixing it.
Good to see a Fix patch of the ICE before Vector ABI patch.
Let's wait for more comments.
Lehua Ding takes care of Vector ABI implementation and hopefully will send it
soon.
Thanks.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-14 19:56
To: gcc-pa
LGTM now. Thanks for fixing it.
Good to see a Fix patch of the ICE before Vector ABI patch.
Let's wait for more comments.
Lehua Ding takes care of Vector ABI implementation and hopefully will send it
soon.
It seems the email of Jeff is wrong. CC Jeff .for you.
Thanks.
juz
s email is also wrong. CC Robin too for you
Thanks.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-14 19:56
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; palmer
Subject: [PATCH V2] RISC-V: Ensure vector args and return use function stack to
pass [PR110119]
The V2 pat
ere, otherwise, return false. */
Send V3 with adding more comments and merge thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-15 09:52
To: gcc-patches
CC: juzhe.zhong; palmer; rdapp.gcc; jeffreyalaw; kito.cheng
Subject: [PATCH v2] RISC-V: Use merge approach to optimize vector permuta
LGTM thanks,.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-15 10:18
To: gcc-patches
CC: juzhe.zhong; palmer; rdapp.gcc; jeffreyalaw; kito.cheng
Subject: [PATCH v3] RISC-V: Use merge approach to optimize vector permutation
From: Juzhe-Zhong
This patch is to optimize the permuation case
u.org/pipermail/gcc-patches/2023-June/621322.html
this patch.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-14 23:31
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add autovec FP unary operations.
Hi,
this patch adds flo
LGTM
juzhe.zh...@rivai.ai
From: shiyulong
Date: 2023-06-15 13:40
To: gcc-patches
CC: palmer; kito.cheng; jim.wilson.gcc; juzhe.zhong; pan2.li; wuwei2016;
jiawei; shihua; dje.gcc; mirimmad; yulong
Subject: [PATCH V1] RISC-V:Add float16 tuple type support
From: yulong
This patch adds support
on
>>should possibly return the corresponding IFN as well.
ok
>>use the proper ifn index compute fn
ok
>>so this answers my question - you just have len_mask{load,store}?
Yes.
>>I think we really want to common this somehow, having
>>if (loop_lens) do the final
(without BIAS argument)? And extend it with
>>BIAS if
>>PowerPC want to use LEN_MASK_ *
Oh, sorry. Forget about this information. I will add BIAS argument too.
Thanks for comments.
Will send splitted patch with only IFN and optab patch for review.
Thanks a lot.
juzhe.zh...@rivai.a
Ok. I will add BIAS argument too for the convenience of possible s390 needed.
Even though we (RVV) don't really need it.
Thank. Will send a small patch V3 soon.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-15 16:58
To: juzhe.zh...@rivai.ai; rguenther
CC: rdapp.gcc; gcc-pa
!
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-15 17:52
To: Robin Dapp
CC: juzhe.zh...@rivai.ai; gcc-patches; richard.sandiford; krebbel; uweigand;
linkw
Subject: Re: [PATCH V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow
control for length loop control
On Thu, 15 Jun 2023, Robin
0b111. */
};
But you only change frm_field_enum
into rounding_mode. It makes these 2 rounding mode odd.
I suggest you change bothe of them into fixed_point_rounding_mode and
floating_point_rounding_mode.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-15 23:10
To: gcc-patches; palmer; Kito
TL
>>interfaces?
I saw ARM SVE is using them in many places for expanding patterns.
And I think it's convenient so that's why I use them.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-07-12 10:01
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; rdapp.gcc
Subject: Re: [PATCH
LGTM
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-07-12 11:27
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; kito.cheng; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or
supervisor extension
Hi,
This tiny patch add a check for extension
RVV indexed load/store with vector offset
(vluxei/vsuxei).
Jeff is worrying about whether we are using SSA_NAME_DEF_STMT at this point
(during the stage "expand" expanding gimple ->rtl).
I am also wondering whether I am doing wrong here.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff
to another unknown(may be same or
different from previous dynamic mode) Dynamic mode.frm_unknown_dynamic_p
The reset refactoring looks good.Let's see whether kito has more comments.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-12 13:50
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffr
expand_scatter_store_optab_fn
of internal-fn.cc
Am I right? Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-12 15:27
To: juzhe.zh...@rivai.ai
CC: jeffreyalaw; gcc-patches; Kito.cheng; Robin Dapp; richard.sandiford
Subject: Re: Re: [PATCH V5] RISC-V: Support gather_load/scatter RVV
auto-vectorization
On
Thanks Richard so much!
I am gonna prepare V7 of this patch with dropping the strided load/store
support on RISC-V backend.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-12 15:56
To: juzhe.zh...@rivai.ai
CC: jeffreyalaw; gcc-patches; Kito.cheng; Robin Dapp; richard.sandiford
Thank you so much.
I have addressed all comments with V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624237.html
Could you take a look at it whether it looks reasonable to you?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-07-12 17:29
To: juzhe.zhong
CC: gcc
Thank you so much.
I am gonna wait for Richi's final approval.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-07-12 18:53
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] VECT: Apply COND_LEN_* into vectorizable_operation
juzhe.zh...@rivai.ai writes:
&
CT_VL, at the last iteration, it's
probably partial vector, so the element >= length should
keep the original value.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-07-12 18:53
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] VECT: Apply CO
i] CODE B[i];
else
LHS[i] = ELSE[i];
}
Does it look reasonable to you?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-07-12 18:53
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] VECT: Apply COND_LEN_* into vectorizable_operation
juzhe.zh...@rivai.ai
E[i];
+ }
+*/
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-12 18:59
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches
Subject: Re: Re: [PATCH V2] VECT: Apply COND_LEN_* into vectorizable_operation
On Wed, 12 Jul 2023, juzhe.zh...@rivai.ai wrote:
> Thank yo
ermail/gcc-patches/2023-July/624395.html
Does it look more reasonable ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-13 15:53
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH] SSA MATH: Support COND_LEN_FMA for floating-point math
optimization
On Thu,
cause such issue.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-13 19:40
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Enable COND_LEN_FMA auto-vectorization
Hi Juzhe,
thanks, no complaints from my side apart
Could you tell me how to add the comment?
I am not familiar with link/binutils stuff.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-13 19:40
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Enable COND_LEN_FMA
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-14 10:50
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support basic floating-point dynamic rounding mode
From: Pan Li
This patch would like to support the basic floating-point dynamic
, loc, new_rtx, in_group);
+ gcc_assert (change_p);
+}
as you suggested.
Could you take a look again?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-17 15:00
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support non-SLP unordered
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-14 21:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li
Refine the run test case to avoid interactive checking in RV32, by
separating
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-18 10:49
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li
Refine the run test case to avoid interactive checking in RV32, by
separating
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-07-18 14:55
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; kito.cheng; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Remove testcase that cannot be compiled because VLEN
limitation
Hi,
Since the latter patch
(https://gcc.gnu.org/pipermail
Not familiar with this stuff.
I leave it other RISC-V folks to review.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-07-18 15:42
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; kito.cheng; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Fix testcase failed when default -mcmodel=medany
Hi,
This
Address comment with V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624754.html
with moving the location of VSET_SHI_INSERT patterns.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-18 15:54
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject
. */
+ bool static_frm_p;
Add a structure wrapper to wrap these 2 variable up.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-19 11:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan
vfadd2
}
}
vfadd1 and vfadd2 can be either static or dyn.
test3 (16 combinations):
for (...) {
if () {
vfadd1
call
vfadd2
} else {
vfadd3
call
vfadd4
}
}
vfadd1 and vfadd2 and vfadd3 and vfadd 4 can be either static or dyn.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023
Thanks.
Some more tests:
test 1:
if (){
vadd (integer RVV intrinsic)
}else{
CALL
}
vfadd static
return
test 2:
if (){
vfadd DYN
}else{
CALL
}
vfadd static
return
test 3:
if (){
vfadd static
}else{
CALL
}
vfadd static
return
I think that's enough, no more tests.
juz
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