[PATCH 2/9] RISC-V: Handle differences between xtheadvector and vector

This patch is to handle the differences in instruction generation between vector and xtheadvector, mainly adding th. prefix to all xtheadvector instructions. gcc/ChangeLog: * config.gcc: Add header for XTheadVector intrinsics. * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):

[PATCH 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c: New test. * gcc

[PATCH 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c: New test. * gc

[PATCH 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c: New test. * gc

[PATCH 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for ternary and unary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c: New test.

[PATCH 7/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part5)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for auto-vectorization. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c: New test. * gc

[PATCH 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics

This patch only involves the generation of xtheadvector special load/store instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * config/riscv/riscv-vector

[PATCH 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension

Because the XTheadVector extension does not support fractional operations, so we need to delete the related intrinsics. The types involved are as follows: v(u)int8mf8_t, v(u)int8mf4_t, v(u)int8mf2_t, v(u)int16mf4_t, v(u)int16mf2_t, v(u)int32mf2_t, vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t gcc/C

[PATCH v2 0/9] RISC-V: Support XTheadVector extensions

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ I updated my patch series, because I forgot to add co-authors in the last version. Contributors: Jun Sha (Joshua) Jin Ma Christoph

[PATCH v2 1/9] RISC-V: minimal support for xtheadvector

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * common

[PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector

This patch is to handle the differences in instruction generation between vector and xtheadvector, mainly adding th. prefix to all xtheadvector instructions. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * config.gcc: Add header for

[PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog

[PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog

[PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog

[PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for ternary and unary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite

[PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics

This patch involves the generation of xtheadvector special load/store instructions. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin

[PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension

Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_v_ext_mode_p): New extern. * config/riscv/riscv-vector-builtins-shapes.cc (check_type): New function. (build_one): If the

Patch to split out new warning flag for floating point conversion

modified correctly. == Testcases == This patch has passes the existing -Wconversion testcases. gcc/testsuite/c-c++-common/Wconversion-real.c and other testcases possibly could be modified. == Changelog == 2013-10-08 Joshua Cogliati Splitting out a -Wfloat-conversion from -Wconversion for

[PATCH, PR 53001] Re: Patch to split out new warning flag for floating point conversion

h does not. I am not certain that c.opt was modified correctly. == Testcases == This patch has passes the existing -Wconversion testcases. It modifies Wconversion-real.c, Wconversion-real-integer.c and pr35635.c to be more specific == Changelog == 2013-10-13 Joshua Cogliati Splitt

Re: [PATCH, PR 53001] Re: Patch to split out new warning flag for floating point conversion

Attached is a patch that addresses most of Dodji Seketeli's comments. Explanations for the rest are inline. On 10/14/2013 03:04 AM, Dodji Seketeli wrote: > Thank you Joshua for following up on this. Please find below some > comments of mine that mostly belong to the nitpicking depar

Re: [PATCH, PR 53001] Re: Patch to split out new warning flag for floating point conversion

On 10/14/2013 05:34 PM, Joseph S. Myers wrote: > On Mon, 14 Oct 2013, Dodji Seketeli wrote: > >>> This patch has passes the existing -Wconversion testcases. It >>> modifies Wconversion-real.c, Wconversion-real-integer.c and >>> pr35635.c to be more specific >> >> If the patch passes existing tes

Re: [PATCH, PR 53001] Re: Patch to split out new warning flag for floating point conversion

-Wfloat-conversion On 10/18/2013 09:21 AM, Joseph S. Myers wrote: > On Fri, 18 Oct 2013, Joshua J Cogliati wrote: > >> This patch does not change any of the non-commented c and c++ >> code. It changes the dg comments. Example: - fsi (3.1f); /* { >> dg-warning "

Re: [PATCH, PR 53001] Re: Patch to split out new warning flag for floating point conversion

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 == Administrivia == This is my first patch. I have emailed in the signed copyright transfer documents already. Several versions of this patch have been sent to the mailing list already. I believe that I have incorporated all comments into the attac

Re: [PATCH, PR 53001] Re: Patch to split out new warning flag for floating point conversion

sions that are warned about by -Wfloat-conversion On 10/28/2013 02:50 AM, Dodji Seketeli wrote: > Hello Joshua, > > Joshua J Cogliati writes: > >> I am not certain that c.opt was modified correctly. > > I don't see any problem with the c.opt part. So unle

Re: [PATCH, PR 53001] Re: Patch to split out new warning flag for floating point conversion

have one very small nit for one ChangeLog entry, expressed > below. If nobody objects in the next 48 hours, I'd say this is OK > to commit with the nit fixed. > > I am not seeing your name in the MAINTAINERS file. Have you filed > copyright assignment to the FSF and do you ha

回复：[PATCH] Asan changes for RISC-V.

Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in to reconfigure, there are compiling errors. Is it because # libsanitizer not supported rv32, but it will break the rv64 multi-lib build, so we

回复：[PATCH] Asan changes for RISC-V.

Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in to reconfigure, there are compiling errors. Is it because # libsanitizer not supported rv32, but it will break the rv64 multi-lib build, so we

回复：[PATCH] Asan changes for RISC-V.

Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in to reconfigure, there are compiling errors. Is it because # libsanitizer not supported rv32, but it will break the rv64 multi-lib build, so we

[RISC-V] Add support for AddressSanitizer on RISC-V GCC

From: cooper.joshua gcc/ * config/riscv/riscv.c (asan_shadow_offset): Implement the offset of asan shadow memory for risc-v. (asan_shadow_offset): new macro definition. --- gcc/config/riscv/riscv.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/gcc/co

回复：[RISC-V] Add support for AddressSanitizer on RISC-V GCC

32 bit targets is fine. > > [1] > https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/asan/asan_mapping.h#L159 > > Hi Joshua: > > Could you update that for RV32, and this patch will be pending until > LLVM accepts the libsanitizer part. This is ABI, and Linux onl

[RISC-V] Add support for AddressSanitizer on RISC-V GCC

From: cooper.joshua gcc/ * config/riscv/riscv.c (asan_shadow_offset): Implement the offset of asan shadow memory for risc-v. (asan_shadow_offset): new macro definition. libsanitizer/ * sanitizer_common/sanitizer_common.h (ModuleArch): New enumerator.

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