[PATCH V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. There are no instructions that do traditional AltiVec addresses (i.e. with the low four bits of the address masked off) for OOmode and XOmode objects. The solution is to modify the constraints used in the movoo

[PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. When the user specifies PTImode as an attribute, it breaks. Created a tree node to handle PTImode types. PTImode attribute helps in generating even/odd register pairs on 128 bits. 2023-07-20 Jeevitha Palanisam

[PING ^1][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Ping! please review. Thanks & Regards Jeevitha On 20/07/23 10:05 am, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > When the user specifies PTImode as an attribute, it breaks. Created > a tree node to handle PTImode types. PTImod

[PING^1][PATCH V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

Ping! please review. Thanks & Regards Jeevitha On 19/07/23 10:16 pm, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > There are no instructions that do traditional AltiVec addresses (i.e. > with the low four bits of the address mas

[PATCH] MAINTAINERS: Add myself to write after approval

2023-05-30 Jeevitha Palanisamy ChangeLog: * MAINTAINERS (Write After Approval): Add myself. diff --git a/MAINTAINERS b/MAINTAINERS index 2dc51154446..4a7c963914b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -584,6 +584,7 @@ Patrick O'Neill Brad

[PATCH] rs6000: Remove duplicate expression [PR106907]

PR106907 has few warnings spotted from cppcheck. In that addressing duplicate expression issue here. Here the same expression is used twice in logical AND(&&) operation which result in same result so removing that. 2023-06-05 Jeevitha Palanisamy gcc/ PR target/106907 * config/r

Re: [PATCH] rs6000: Remove duplicate expression [PR106907]

Thanks for reviewing Segher. Will work on backports as well :). Jeevitha

[PATCH] rs6000: Remove redundant initialization [PR106907]

PR106907 has few warnings spotted from cppcheck. In that addressing redundant initialization issue. Here the initialized value of 'new_addr' was overwritten before it was read. Updated the source by removing the unnecessary initialization of 'new_addr'. 2023-06-07 Jeevitha Palanisamy gcc/

[PATCH] Add parentheses to clarify precedence between operators [PR106907]

PR106907 has few warnings spotted from cppcheck. Inorder to clarify the order of precedence between operators added parentheses to explicitly group operations based on desired order of evaluation. 2023-06-07 Jeevitha Palanisamy gcc/ PR target/106907 * config/gcn/gcn.cc (gcn_hsa

[PATCH] rs6000: Change bitwise xor to inequality operator [PR106907]

PR106907 has few warnings spotted from cppcheck. Here we have warnings for precedence clarification since boolean results are used in bitwise operation. Bitwise xor performed on bool is similar to checking inequality. So changed to inequality operator (!=) instead of bitwise xor (^). And fixed comm

[PATCH V2] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile register. However, it can be used as volatile for PCREL addressing. Therefore, modified r2 to be non-fixed in FIXED_REGISTERS and se

[PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile register. However, it can be used as volatile for PCREL addressing. Therefore, if the code is PCREL and the user is not explicitly req

[PATCH] rs6000: Don't ICE when generating vector pair load/store insns [PR110411]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. while generating vector pairs of load & store instruction, the src address was treated as an altivec type and that type of address is invalid for lxvp and stxvp insns. The solution for this is to avoid altivec

Re: [PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]

On 07/07/2023 A 12:11 am, Peter Bergner wrote: > I believe the untested patch below should also work, without having to scan > the (uncommonly used) options. Jeevitha, can you bootstrap and regtest the > patch below? Yeah Peter, Bootstrapped and regtested the below patch on powerpc64le-linux