Please add ChangeLog and the trunk patch revision.
http://codereview.appspot.com/6206055/
http://codereview.appspot.com/6206055/diff/4001/gcc/ChangeLog
File gcc/ChangeLog (right):
http://codereview.appspot.com/6206055/diff/4001/gcc/ChangeLog#newcode11
gcc/ChangeLog:11:
It seems you also merged in another patch r187012, please mention it.
http://codereview.appspot.com/6206055/diff/40
OK for google branch.
google/gcc-4_7 may also need this patch.
http://codereview.appspot.com/6206055/
LGTM
thanks
Carrot
On Thu, Jan 28, 2016 at 11:53 AM, Han Shen wrote:
> Backport trunk:r232727 fix for PR/69403 - wrong
> thumb2_ior_scc_strict_it insn pattern.
>
> Note this only affect armv7-a tuned for armv8 arch, tested / booted
> affected ChromeOS book.
>
> Ok for
Hi
When compiling an internal application I got an ICE
due to an invalid instruction generated by reload.
Before IRA, I have following insns:
(insn 139 136 581 10 (set (reg:DI 567)
(const_int 0 [0])) ./strings/stringpiece.h:205 discrim 1 520
{*movdi_internal64}
(expr_list:REG_EQUIV
Thank you for the comment, I've updated the patch.
OK for trunk and 4.9 branch?
2014-08-08 Guozhi Wei
* config/rs6000/rs6000.md (*movdi_internal64): Add a new constraint.
On Wed, Aug 6, 2014 at 7:28 PM, Segher Boessenkool
wrote:
> On Wed, Aug 06, 2014 at 04:48:26PM -0700
Hi
Current AArch64 backend can generate rtl expressions like
(vec_duplicate:DI (const_int 0 [0])), which causes ICE in
simplify_const_unary_operation because vec_duplicate should generate
vector mode only.
As suggested by Andrew in the bug entry, I split the original insn
patterns to avoid scalar
q_u64_s32(rows.val[1]);
+ uint64x1_t row3l = vget_low_u64(row01.val[0]);
+ row01.val[0] = vcombine_u64(vget_low_u64(row01.val[1]), row3l);
+ int32x4_t xxx = vreinterpretq_s32_u64(row01.val[0]);
+ int32x4_t out = vtrn1q_s32 (xxx, xxx);
+ bar(out);
+}
On Wed, Aug 20, 2014 at 4:26 AM, Kyrill Tkachov
Hi
In insn pattern "*andim_ashift_bfiz", if the operands[2] is larger than
the size of register, gcc may generate invalid assembler code. If operands[2]
is larger than the size of the underlying type of INTVAL, the following insn
condition may also be undefined.
"exact_log2 ((INTVAL (operands[3])
AArch64 maintainers, could you help to review following patches?
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg01966.html
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg02060.html
thanks
Guozhi Wei
On Wed, Aug 20, 2014 at 12:51 PM, Carrot Wei wrote:
> Good suggestion. Add the testc
On 20 August 2014 20:51, Carrot Wei wrote:
>> Good suggestion. Add the testcase.
>>
>> thanks
>> Guozhi Wei
>>
>> 2014-08-20 Guozhi Wei
>>
>> PR target/62040
>
LGTM.
Your description could be more detail, such as which tests on which target.
On Tue, Oct 7, 2014 at 2:06 PM, Sterling Augustine
wrote:
> The enclosed patch for google 4.9 is a backport of r210828 from
> trunk.
>
> googleref:b/14623977
>
> The given tests now pass when run by hand, but timeou
Hi
In current vectorization pass, when a new vector pointer is created,
its alignment is not set correctly. We should use DR_MISALIGNMENT (dr)
since only this alignment is adjusted when loop peeling or multi
version is occurred.
This patch passed following tests:
x86_64 bootstrap.
x86_64 regressi
20, 2014 at 1:19 AM, Richard Biener
wrote:
> On Fri, Oct 17, 2014 at 7:58 PM, Carrot Wei wrote:
>
> I miss a testcase. I also miss a comment before this code explaining
> why DR_MISALIGNMENT if not -1 is valid and why it is not valid if
DR_MISALIGNMENT (dr) == -1 means some unk
DR_MISALIGNMENT.
2014-10-22 Guozhi Wei
PR tree-optimization/63530
gcc.dg/vect/pr63530.c: New testcase.
On Tue, Oct 21, 2014 at 1:04 AM, Richard Biener
wrote:
> On Mon, Oct 20, 2014 at 10:10 PM, Carrot Wei wrote:
>> Hi Richard
>>
>> An arm testcase that can reproduce
Hi
The more strict devirtualization condition in this patch helps to fix
google bug b/19872411.
Bootstraped and regression tested on x86-64.
OK for google 4.9 branch?
patch
Description: Binary data
This patch fixes google internal bug b/19277289. It can only be
reproduced in google 4.9 branch.
In function param_change_prob, there is following function call
walk_aliased_vdefs (&refd, gimple_vuse (stmt), record_modified, &info, NULL);
If the source code is compiled with optimization, but cfu
Hi
I forgot to notify df framework when I removed an insn, it caused df
verification failure described in google bug b/16155462.
The following patch passed regression test on arm qemu in both thumb
and arm modes.
OK for google 4.9 branch?
Index: simplify-got.c
==
On Tue, Jun 9, 2015 at 11:43 PM, Richard Sandiford
wrote:
> Carrot Wei writes:
>> Index: simplify-got.c
>> ===
>> --- simplify-got.c (revision 224174)
>> +++ simplify-got.c (working copy)
>> @@ -1
Hi
In aarch64 backend of google/4.9 branch, the split pattern for insn
aarch64_lshr_sisd_or_int_3 destroys one of the source operands,
causes the later usage of the operand get a wrong value (google bug
17907351).
The bug has been fixed in trunk by r220860. This patch backports it to
google/4.9 b
Hi
In Google application we hit the same problem as
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63341, so we also need
the patch r215585 for Google/4.9 branch.
It passed following tests:
bootstrap and regression test on x86-64.
regression test on ppc.
Google reference 18687126.
OK for Google/4
Yes, it has been long time since last merge, so it is good idea to do
another merge.
On Tue, Dec 16, 2014 at 11:32 AM, Xinliang David Li wrote:
> The fix is already in upstream gcc-4.9 branch? If yes, we just need a merge.
>
> David
>
> On Tue, Dec 16, 2014 at 11:30 AM, Carrot We
n our testing environment since all other executions
with different compiler options failed. All testing of tls-test.c pass native
power64 testing.
thanks
Carrot
2013-05-02 Guozhi Wei
* coverage.c (gcov_info_type): New global variable.
(coverage_obj_init): Move the construction of gcov constr
This patch outline the construction of gcov constructor from coverage_obj_init
as a separate function build_init_ctor.
It passed bootstrap and regression test on x86-64.
OK for trunk and google 4.7 branch?
thanks
Carrot
2013-05-02 Guozhi Wei
* coverage.c (gcov_info_type): New
On Fri, May 3, 2013 at 1:03 AM, Richard Biener
wrote:
> On Thu, May 2, 2013 at 10:41 PM, Carrot Wei wrote:
>> This patch outline the construction of gcov constructor from
>> coverage_obj_init
>> as a separate function build_init_ctor.
>>
>> It passed bootst
commited as 198591.
On Fri, May 3, 2013 at 11:51 AM, Xinliang David Li wrote:
> Please do what Richard suggested. gcov_info_type can be obtained from
> gcov_info_var decl.
>
> David
>
>
> On Fri, May 3, 2013 at 11:31 AM, Carrot Wei wrote:
>> On Fri, May 3, 2013
After the refactoring has been checked in, the bug fixing part is simply
a moving a function call.
Tested by running ./buildit with both x86-64 and power64 targets.
The last time regression of tls-tests.c disappeared. So it is really flaky
in our testing environment.
thanks
Carrot
2013-05-02
OK for google branch. Should it also be in gcc4.8 branch?
thanks
Carrot
On Tue, May 7, 2013 at 12:01 PM, Han Shen(沈涵) wrote:
> Backport trunk@198344 - another fix to PR rtl-optimization/56847 - to
> google/gcc-4_8 branch.
>
> The first fix was trunk@198101 -
> http://gcc.gnu.org
ly or indirectly called from anywhere. So we need to check if
a decl can be safely passed into varpoo_node before calling it.
Tested by ./buildit with targets x86-64 and power64 without regression.
OK for google branches?
thanks
Carrot
2013-05-09 Guozhi Wei
varasm.c (notice_global_s
by lipo, before that
these functions can't call into varpool_node. So could it because the original
implementation of these functions didn't consider the restrictions of
varpool_node
since it couldn't be called from there?
thanks
Carrot
> David
>
> On Thu, May 9, 2013 at 1
all cases. It can pass bootstrap
and regression test on x86-64.
Any comments?
thanks
Carrot
2013-05-09 Guozhi Wei
* dwarf2asm.c (dw2_output_indirect_constant_1): Mark new decl STATIC.
Index: dwarf2asm.c
OK for google branches.
On Thu, May 9, 2013 at 1:40 PM, Han Shen(沈涵) wrote:
> Hi, I'm to backport trunk patch @198547 for pr target/56732 to google
> branch google/gcc-4_8.
>
> This patch fixes arm ICE.
>
> Ok for google/gcc-4_8?
>
> [patch attached]
>
> H.
Hi
Since b/8397853 has been fixed, the related tests now passed, so we can remove
them from powerpc64-grtev3-linux-gnu.xfail now.
Tested with ./buildit --run_tests.
OK for google 4.7 branch?
thanks
Carrot
2013-05-29 Guozhi Wei
* powerpc64-grtev3-linux-gnu.xfail (*** g++): Remove passed
OK for google/gcc-4_7.
On Wed, Jun 5, 2013 at 2:45 PM, Jing Yu wrote:
> Add new validator manifest xfail file for native powerpc64 toolchain.
> Ok for google/gcc-4_7?
>
> Tested:
> ./validate_failures.py
> --manifest=powerpc64-grtev3-linux-gnu-native.xfail --
> results="gcc/gcc.sum g++/g++.sum gf
Hi
The extended register width in add/adds/sub/subs/cmp instructions is
not always the same as target register, it depends on both target
register width and extension type. But in current implementation the
extended register width is always the same as target register. We have
noticed it can gener
Ping.
On Mon, Sep 22, 2014 at 11:41 AM, Carrot Wei wrote:
> Hi
>
> The extended register width in add/adds/sub/subs/cmp instructions is
> not always the same as target register, it depends on both target
> register width and extension type. But in current implementation the
>
Hi
The last operand of instruction sqdmulh can only be low fp registers,
so we should use constraint "x". But the intrinsic functions use "w".
This patch fixed the constrains in these intrinsics.
Passed dejagnu test on aarch64 qemu. OK for trunk, 4.9 and 4.8?
thanks
Guozhi Wei
2014-05-19 Guoz
last operand's constraint.
(vqdmulhq_n_s16): Likewise.
On Mon, May 19, 2014 at 11:50 PM, James Greenhalgh
wrote:
> On Tue, May 20, 2014 at 07:18:40AM +0100, Carrot Wei wrote:
>> Hi
>
> Hi,
>
>> The last operand of instruction sqdmulh can only be low fp r
Committed to trunk, 4.9, and waiting for the release of 4.8.3.
OK for google/main and google/4.9?
thanks
Carrot
On Wed, May 21, 2014 at 1:34 AM, Richard Biener wrote:
> On Wed, 21 May 2014, Marcus Shawcroft wrote:
>
>> On 21 May 2014 09:28, Marcus Shawcroft wrote:
>> >
Hi
The following patch fixes an obvious wrong index used to access the
dense array. The patch has passed the bootstrap and regression tests
on x86-64.
OK for trunk?
thanks
Carrot
2014-02-23 Guozhi Wei
* sparseset.h (sparseset_pop): Fix the wrong index.
Index: sparseset.h
OK for google/gcc-4_7.
thanks
Carrot
On Tue, Aug 14, 2012 at 7:14 AM, Han Shen(沈涵) wrote:
>
> Hi Carrot, could you take a look at this patch? Thanks!
>
> The modification is in upstream trunk patch revision - 186859.
>
> The same patch has been back ported to goog
Hi Jakub
The same problem also affects gcc4.6,
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54398. Could this be
ported to 4.6 branch?
thanks
Carrot
On Mon, Feb 13, 2012 at 11:54 AM, Jakub Jelinek wrote:
>
> On Wed, Jan 04, 2012 at 05:21:38PM +, Marcus Shawcroft wrote:
> > Alias
Hi Jakub
I have run it on 4.6, it passes the following testing:
x86-64 bootstrap
x86-64 regression test
regression test on arm qemu
Is it OK for gcc4.6?
Ahmad, is it OK for google/gcc-4_6/ and google/gcc-4_6-mobile ?
thanks
Carrot
On Wed, Sep 12, 2012 at 2:01 PM, Carrot Wei wrote:
>
.
http://gcc.gnu.org/ml/gcc-patches/2012-06/msg00287.html
64bit ior with constants.
thanks
Carrot
duplicated the alternatives in normal cases.
thanks
Carrot
On Wed, Jun 20, 2012 at 9:58 AM, Michael Hope wrote:
> On 18 June 2012 22:17, Carrot Wei wrote:
>> Hi
>>
>> Could ARM maintainers review following patches?
>>
>> http://gcc.gnu.org/ml/gcc-patches/2012-06/msg0049
ping^2
thanks
Carrot
On Mon, Jun 18, 2012 at 6:17 PM, Carrot Wei wrote:
> Hi
>
> Could ARM maintainers review following patches?
>
> http://gcc.gnu.org/ml/gcc-patches/2012-06/msg00497.html
> 64bit add/sub constants.
>
> http://gcc.gnu.org/ml/gcc-patches/2012-05/msg018
Hi Ramana
Thanks for the review, please see my inlined comments.
On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan
wrote:
>
> On 8 June 2012 10:12, Carrot Wei wrote:
> > Hi
> >
> > In rtl expression, substract a constant c is expressed as add a value -c,
> &g
On Thu, Jun 28, 2012 at 5:37 PM, Ramana Radhakrishnan
wrote:
> On 28 June 2012 10:03, Carrot Wei wrote:
>> Hi Ramana
>>
>> Thanks for the review, please see my inlined comments.
>>
>> On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan
>> wrote:
&
Hi
So the following is updated patch. Tested on qemu with arm/thumb modes
without regression.
thanks
Carrot
2012-06-29 Wei Guozhi
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
* gcc.target/arm/pr53447-2.c: New testcase.
2012-06-29 Wei Guozhi
On Fri, Jun 29, 2012 at 9:57 PM, Ramana Radhakrishnan
wrote:
>
> On 29 June 2012 12:23, Carrot Wei wrote:
> > Hi
> >
> > So the following is updated patch. Tested on qemu with arm/thumb modes
>
> Assuming this testing was with and without neon ? Because the pa
On Thu, Jun 28, 2012 at 12:14 AM, Ramana Radhakrishnan
wrote:
> On 28 May 2012 11:08, Carrot Wei wrote:
>> Hi
>>
>> This is the second part of the patches that deals with 64bit and. It directly
>> extends the patterns anddi3, anddi3_insn and anddi3_neon to handle
://gcc.gnu.org/bugzilla/show_bug.cgi?id=53145, it also failed in
other arm configuration
http://gcc.gnu.org/ml/gcc-testresults/2012-06/msg00755.html, so it is
not a new regression.
thanks
Carrot
2012-07-05 Wei Guozhi
PR target/53189
* gcc.target/arm/pr53189-4.c: New testcase
Hi
I updated this patch to use const_ok_for_dimode_op to decide if a
const is legal for iordi3 insn. The special cases of all 0 and all 1
constant are also handled.
Tested on arm qemu with all thumb/arm neon/non-neon combination, no regression.
thanks
Carrot
2012-07-06 Wei Guozhi
://gcc.gnu.org/ml/gcc-patches/2012-07/msg00226.html
thanks
Carrot
On Tue, Jul 17, 2012 at 9:47 PM, Ramana Radhakrishnan
wrote:
> Carrot,
>
> Sorry about the delayed response.
>
> On 3 July 2012 12:28, Carrot Wei wrote:
>> On Thu, Jun 28, 2012 at 12:14 AM, Ramana Radhakrishnan
>> wrote:
>>> On 28 May 2012 11:08, Carrot Wei
On Wed, Jul 18, 2012 at 5:39 PM, Ramana Radhakrishnan
wrote:
> On 18 July 2012 09:20, Carrot Wei wrote:
>> On Tue, Jul 17, 2012 at 9:47 PM, Ramana Radhakrishnan
>> wrote:
>>> Carrot,
>>>
>>> Sorry about the delayed response.
>>>
>>>
OK for Google branches.
On Mon, May 7, 2012 at 12:21 PM, Jing Yu wrote:
> I would like to port this patch to google/gcc-4_6 and also
> google/gcc-4_6_2-mobile.
>
> From reading the patch, it does not change config for non-Android target.
>
> bootstrap,crosstool tests finished successfully on goog
constant
operands.
Tested on arm qemu without regression.
OK for trunk?
thanks
Carrot
2012-05-26 Wei Guozhi
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
2012-05-26 Wei Guozhi
PR target/53447
* config/arm/arm-protos.h (const_ok_for_adddi
Hi
This is the second part of the patches that deals with 64bit and. It directly
extends the patterns anddi3, anddi3_insn and anddi3_neon to handle 64bit
constant operands.
Tested on arm qemu without regression.
OK for trunk?
thanks
Carrot
2012-05-28 Wei Guozhi
PR target/53447
Hi
This is the third part of the patches that deals with 64bit xor. It extends
the patterns xordi3, xordi3_insn and xordi3_neon to handle 64bit constant
operands.
Tested on arm qemu without regression.
OK for trunk?
thanks
Carrot
2012-05-30 Wei Guozhi
PR target/53447
Hi
I updated the patch to correct the length of insn adddi3_neon.
thanks
Carrot
2012-06-04 Wei Guozhi
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
2012-06-04 Wei Guozhi
PR target/53447
* config/arm/arm-protos.h (const_ok_for_adddi): New
Hi
This is the fourth part of the patches that deals with 64bit ior. It directly
extends the patterns iordi3, iordi3_insn and iordi3_neon to handle 64bit
constant operands.
Tested on arm qemu without regression.
OK for trunk?
thanks
Carrot
2012-06-05 Wei Guozhi
PR target/53447
h to avoid using sub instruction.
Tested on arm qemu with both arm/thumb mode.
thanks
Carrot
2012-06-06 Wei Guozhi
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
2012-06-06 Wei Guozhi
PR target/53447
* config/arm/arm.md (adddi3): Extend it
keeping the add rtl
expression.
Tested on arm qemu with both arm/thumb modes. OK for trunk?
thanks
Carrot
2012-06-08 Wei Guozhi
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
* gcc.target/arm/pr53447-5.c: New testcase.
2012-06-08 Wei Guozhi
d regression test on arm qemu.
>
> OK for google/gcc-4_6 ?
>
> thanks
> Carrot
>
>
> 2011-08-08 Guozhi Wei
>
> Backport r174965 from trunk.
>
> 2011-06-12 Ira Rosen
>
> * tree-vect-data-refs.c (vect_peeling_hash_get_most_
Hi
We should not combine insns cross volatile insns. Combine.c already does this
check, postreload should also do so.
Bootstrapped and regtested on x86_64-unknown-linux-gnu.
Regtested on arm qemu.
thanks
Carrot
ChangeLog:
2011-09-19 Wei Guozhi
PR 49452
* postreload.c
Hi Tom
What's the behavior of your patch to the following case
typedef int int_unaligned __attribute__((aligned(1)));
int foo (int_unaligned *p)
{
return *p;
}
thanks
Carrot
On Tue, Sep 20, 2011 at 7:13 PM, Tom de Vries wrote:
> Hi Richard,
>
> I have a patch for PR43814. It
Since it also affects 4.6 branch, can this and r176270 also be ported to gcc4.6?
thanks
Carrot
On Wed, Jul 13, 2011 at 12:34 AM, Richard Sandiford
wrote:
> PR 48183 is caused by the fact that we don't really support integers
> (or least integer constants) wider than 2*HOST_BITS_P
On Fri, Dec 9, 2011 at 4:56 PM, Richard Sandiford
wrote:
> Carrot Wei writes:
>> Since it also affects 4.6 branch, can this and r176270 also be ported
>> to gcc4.6?
>
> Always worth asking, but in this case, I'm not sure it's appropriate.
> The patch is pretty i
}
str r4, [sp, #48]
...
thanks
Carrot
On Mon, Feb 6, 2012 at 9:01 PM, Jakub Jelinek wrote:
> Hi!
>
> The attached testcase is miscompiled on arm*, by doing a sibcall when setup
> of one argument overwrites incoming arguments used to setup parameters in
> later insn
Hi Richard and Jakub
Since 4.6 contains the same bug, I would like to back port it to 4.6
branch. Could you approve it for 4.6?
Jing and Doug
Could you approve it for google/gcc-4_6-mobile branch?
thanks
Carrot
On Mon, Feb 6, 2012 at 9:14 PM, Richard Guenther
wrote:
> On Mon, Feb 6, 2012
On Fri, Feb 10, 2012 at 2:13 PM, Jing Yu wrote:
> On Thu, Feb 9, 2012 at 12:54 AM, Carrot Wei wrote:
>> Hi Richard and Jakub
>>
>> Since 4.6 contains the same bug, I would like to back port it to 4.6
>> branch. Could you approve it for 4.6?
>>
>> Jing
bit instructions in thumb2
thanks
Carrot
Hi
I've tested the
#ifndef __ANDROID__
on arm qemu without regression. And also built Android toolchain
without this error.
thanks
Carrot
2011-05-26 Jing Yu
* ChangeLog.google-main: New file.
* getpagesize.c(getpagesize): Disable it for bionic.
Index: ChangeLog.g
Hi H.J.
This patch is also important to ChromeOS toolchain. Could you also try
to update and test it for google/main?
thanks
Carrot
On Wed, May 18, 2011 at 11:57 PM, H.J. Lu wrote:
> On Tue, Apr 26, 2011 at 6:05 AM, H.J. Lu wrote:
>> On Thu, Mar 31, 2011 at 7:57 AM, H.J. Lu wrote:
&
OK for google/main.
thanks
Carrot
On Thu, Jun 2, 2011 at 12:51 PM, Jing Yu wrote:
> http://gcc.gnu.org/ml/gcc-patches/2010-10/msg00134.html
> Backport r174549 to fix three testcases that are specific to ARM mode
> and therefore should be skipped when compiling for thumb.
>
>
Hi ARM maintainers
Could you help to review the following patches?
thanks
Carrot
On Tue, May 24, 2011 at 9:31 AM, Carrot Wei wrote:
> Hi
>
> http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01973.html
> Use ldrd and strd to access two consecutive words
>
> http://gcc.gnu.org/ml/g
OK.
thanks
Carrot
On Tue, Jun 7, 2011 at 1:09 AM, wrote:
> The trunk version has been approved and committed as r174710. Backport
> it to google/main. The google/main version has the same logic but is
> slightly different since trunk has a different code structure here. OK
> for
It also breaks arm backend.
../trunk/configure '--build=x86_64-build_pc-linux-gnu'
'--host=x86_64-build_pc-linux-gnu'
'--target=arm-unknown-linux-gnueabi'
'--with-sysroot=/home/carrot/x-tools/arm-unknown-linux-gnueabi/arm-unknown-linux-gnueabi/sys-root'
Thanks for the review.
Richard, what's the situation of unaligned memory access and how does
it conflict with this patch?
thanks
Carrot
On Tue, Jun 7, 2011 at 6:42 PM, Nick Clifton wrote:
> Hi Carrot,
>
>> 2011-05-06 Guozhi Wei
>>
>> PR target/47855
>
unexpected property changes after merge, I don't
how did they come out and how should I deal with them?
thanks
Carrot
2011-07-14 Guozhi Wei
Backport r175881 from gcc-4_6-branch
2011-07-05 Jason Merrill
PR testsuite/49643
* g++.dg/rtti/a
rd=arm-sim/thumb/arch=armv7-a
arm.exp=vfp-1.c"
OK for trunk and 4.6 branch?
thanks
Carrot
2011-07-20 Wei Guozhi
* gcc.target/arm/vfp-1.c (test_ldst): Adjust negative offset.
Index: gcc.target/arm/vfp-1.c
===
---
Oops, the ChangeLog should be
2011-07-20 Wei Guozhi
* gcc.target/arm/vfp-1.c (test_ldst): Adjust negative offset.
thanks
Carrot
On Wed, Jul 20, 2011 at 4:30 PM, Carrot Wei wrote:
> Hi
>
> The patch r169271 conservatively limits the offset of fp memory access to
> (-256
ield extraction instruction(sbfx).
Add a check to ensure the bit field is valid before applying the change, so the
wrong sbfx will not be generated.
Bootstrapped and regtested on x86_64-unknown-linux-gnu.
Regtested on arm qemu.
OK for trunk and 4.6?
thanks
Carrot
ChangeLog:
2011-07
and 4.6 now?
thanks
Carrot
ChangeLog:
2011-07-28 Wei Guozhi
PR rtl-optimization/49799
* combine.c (make_compound_operation): Check if the bit field is valid
before change it to bit field extraction.
ChangeLog:
2011-07-28 Wei Guozhi
PR rtl-optimization/49799
&& GET_CODE (lhs) == ASHIFT
&& CONST_INT_P (XEXP (lhs, 1))
&& INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
+ && INTVAL (XEXP (lhs, 1)) >= 0
&& INTVAL (rhs) < mode_width)
{
new_rtx = make_compound_operation (XEXP
Ping
On Wed, Jul 20, 2011 at 4:33 PM, Carrot Wei wrote:
> Oops, the ChangeLog should be
>
> 2011-07-20 Wei Guozhi
>
> * gcc.target/arm/vfp-1.c (test_ldst): Adjust negative offset.
>
>
> thanks
> Carrot
>
> On Wed, Jul 20, 2011 at 4:30 PM, Carrot
On Fri, Apr 8, 2011 at 6:51 PM, Ramana Radhakrishnan
wrote:
> On 08/04/11 10:57, Carrot Wei wrote:
>>
>> Hi
>>
>> This is the second part of the fixing for
>>
>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47855
>>
>> This patc
Hi Richard
Thank you for the detailed explanation. It sounds like an inherent
difficulty of rtl passes. Then the only opportunity is ldrb/strb
instructions because they never affect cc registers.
thanks
Carrot
On Fri, Apr 15, 2011 at 9:34 PM, Richard Earnshaw wrote:
>
> On Thu, 2011-04
On Mon, Apr 18, 2011 at 9:33 PM, Richard Earnshaw wrote:
>
> On Sat, 2011-04-16 at 12:34 +0800, Carrot Wei wrote:
>> Hi Richard
>>
>> Thank you for the detailed explanation. It sounds like an inherent
>> difficulty of rtl passes. Then the only opportunity is ldrb/str
gt;
> What about hot/cold partitioning? That might cause jumps to different
> sections.
>
> Richard.
>
The hot/cold partitioning is disabled in arm backend.
http://gcc.gnu.org/ml/gcc-cvs/2009-10/msg00671.html.
thanks
Carrot
mpiler.
>
> A slightly less optimistic approach, but one that is much safer is to
> scan the function after reload has completed and see if we can avoid
> having to push LR. We can do this if:
>
I guess "less optimistic" is relative to the ideal optimization
situation, I believe it is still much better than current result. Do
you think if arm_reorg() is appropriate place to do this?
thanks
Carrot
I will try this method for trunk later.
thanks
Carrot
On Wed, Apr 20, 2011 at 4:48 PM, Richard Earnshaw wrote:
>
> On Wed, 2011-04-20 at 16:26 +0800, Carrot Wei wrote:
>> On Tue, Apr 19, 2011 at 8:55 PM, Richard Earnshaw wrote:
>> >
>> > On Tue, 2011-04-19 at
= pic_reg)))
> + /* If an insn both set and use pic_reg, it is in the process of
> + constructing the value of pic_reg. We should also ignore it.
> */
> + rtx set = single_set (insn);
> + if (!(set && (SET_DEST (set) == pic_reg)))
>
>
Yes, after porting it to google/main.
Carrot
On Thu, Apr 28, 2011 at 10:26 PM, Diego Novillo wrote:
> Will you be proposing this patch for trunk as well?
>
>
> Diego.
>
On Fri, Apr 29, 2011 at 11:17 AM, Carrot Wei wrote:
> On Thu, Apr 28, 2011 at 10:08 PM, wrote:
>> I only have some stylistic comments for this patch. The new pass looks
>> OK to me, but I do not know this area well enough to do a good review.
>>
>> In your ChangeLog
126, but it is 128 in patterns "*thumb2_cbz" and
> > "*thumb2_cbnz". The second is that only 2-register form of shift
> > instructions
> > can be 16 bit, but 3-register form is allowed in "*thumb2_shiftsi3_short"
> > and
> >
Hi
http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01973.html
Use ldrd and strd to access two consecutive words
http://gcc.gnu.org/ml/gcc-patches/2011-05/msg00490.html
Compute attr length for thumb2 insns
thanks
Carrot
On Fri, Dec 17, 2010 at 8:18 PM, Richard Earnshaw wrote:
>
> On Thu, 2010-12-16 at 14:45 -0800, Carrot Wei wrote:
>> Hi
>>
>> Compile the following c code with options -march=armv7-a -mthumb -Os
>>
>> int foo (int s)
>> {
>> return s ==
The trunk is opened again, could any maintainers continue to review this patch?
thanks
Carrot
On Tue, Jan 18, 2011 at 10:59 PM, Carrot Wei wrote:
> Ramana's method is to put the instruction output and counting in on place.
> So it's easy to keep them synchronized.
>
> My l
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