[PATCH PR95696] regrename creates overlapping register allocations for vliw

Hi， In most target, it is limited to issue two insns with change the same register. So a register is not realy unused if there is another insn, which set the register in the save VLIW. For example, The insn 73 start with insn:TI, so it will be issued together with others insns until a new insn

答复: [PATCH PR95696] regrename creates overlapping register allocations for vliw

rm.com] 发送时间: 2020年7月21日 0:05 收件人: Zhongyunde 抄送: gcc-patches@gcc.gnu.org; Yangfei (A) 主题: Re: [PATCH PR95696] regrename creates overlapping register allocations for vliw Hi, Zhongyunde writes: > Hi， > > In most target, it is limited to issue two insns with change the same > regi

RE: RE: [PATCH PR95696] regrename creates overlapping register allocations for vliw

> -Original Message- > From: Richard Sandiford [mailto:richard.sandif...@arm.com] > Sent: Wednesday, July 22, 2020 12:12 AM > To: Zhongyunde > Cc: gcc-patches@gcc.gnu.org; Yangfei (A) > Subject: Re: 答复: [PATCH PR95696] regrename creates overlapping > register

RE: [PATCH PR95696] regrename creates overlapping register allocations for vliw

> >> It's interesting that this is for a testcase using SMS. One of the > >> traditional problems with the GCC implementation of SMS has been > >> ensuring that later passes don't mess up the scheduled loop. So in > >> your testcase, does register allocation succeed for the SMS loop > >> without

RE: [PATCH PR95696] regrename creates overlapping register allocations for vliw

I reconsider the issue and update patch attached. Yes, If the kernel loop bb's information doesn't use in regrename, it also need not be collected to save compile time. > -Original Message- > From: Zhongyunde > Sent: Sunday, July 26, 2020 3:29 PM > To: 'Ri

RE: [PATCH PR95696] regrename creates overlapping register allocations for vliw

> -Original Message- > From: Richard Sandiford [mailto:richard.sandif...@arm.com] > Sent: Tuesday, July 28, 2020 1:33 AM > To: Zhongyunde > Cc: gcc-patches@gcc.gnu.org; Yangfei (Felix) > Subject: Re: [PATCH PR95696] regrename creates overlapping register >

Support to check vliw overlapping register constraint created by regrename, please help to review, thanks

In some target, it is limited to issue two insns with change the same register.(The insn 73 start with insn:TI, so it will be issued together with others insns until a new insn start with insn:TI, such as insn 71) The regrename can known the mode V2VF in insn 73 need two successive registers, i

[PATCH PR95696] regrename creates overlapping register allocations for vliw

hi,   Insometarget,itislimitedtoissuetwoinsnstogetherwithchangethesameregister,so Imakeapatchtoextendtheliverangeuntiltheendofvliwtoavoidit.(Theinsn73startwithinsn:TI,soitwillbeissuedtogetherwithothersinsnsuntilanewinsnstartwithinsn:TI,suchasinsn71)TheregrenamecanknownthemodeV2VFininsn73needtwosucc

[PATCH] [PHIOPT] Add A ? B + CST : B match and simplify optimizations

hi, This patch is try to fix the issue https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107190, would you like to give me some suggestion, thanks. ~/source/gccUpstreamDir/gcc/testsuite(cfg) » git format-patch -1 --start-number=00 HEAD -o ~/patch /home/zhongyunde/patch/-PHIOPT-Add-A-B-CST-B

RE: [PATCH] [PHIOPT] Add A ? B + CST : B match and simplify optimizations

> -Original Message- > From: Andrew Pinski [mailto:pins...@gcc.gnu.org] > Sent: Saturday, November 5, 2022 2:34 PM > To: Zhongyunde > Cc: hongtao@intel.com; gcc-patches@gcc.gnu.org; Zhangwen(Esan) > ; Weiwei (weiwei, Compiler) > ; zhong_1985...@163.com > Subj