[PATCH] RISC-V: Libitm add RISC-V support.

libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- libitm/config/riscv/asm.h| 52 + libitm/config/riscv/sjlj.S | 144 ++

[PATCH v2] RISC-V: Libitm add RISC-V support.

libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see https://github.com/riscv/riscv-

[PATCH v3] RISC-V: Libitm add RISC-V support.

Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- v2: Change HW_CACHELINE_SIZE to 64 (in accordance wi

[PATCH v4] RISC-V: Libitm add RISC-V support.

Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- v2: Change HW_CACHELINE_SIZE to 64 (in accordance wi

[PATCH v5] RISC-V: Libitm add RISC-V support.

Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- v2: Change HW_CACHELINE_SIZE to 64 (in accordance wi

Re: [PATCH v4] RISC-V: Libitm add RISC-V support.

On Saturday, 29 October 2022 12:33:50 CST Jeff Law wrote: > > +#ifdef __riscv_e > > +# error "rv32e unsupported" > > +#endif > > error "rv32e and rv64e unsupported" would probably be a better error > here. But it's probably not a big deal. Fixed in v5. > Do you have commit access? If so, go