arious bugs in aarch64_final_eh_return_addr, which does not work with
-fomit-frame-pointer, alloca or outgoing arguments.
Bootstrap OK, GCC Regression OK, OK for trunk? Would it be useful to backport
this to GCC6.x?
ChangeLog:
2016-09-02 Wilco Dijkstra
PR77455
gcc/
* config/aarc
version using simple wrapper functions and no
default parameters:
ChangeLog:
2016-08-10 Wilco Dijkstra
gcc/
* config/aarch64/aarch64.c (aarch64_add_constant_internal):
Add extra argument to allow emitting the move immediate.
Use add/sub with positive immediate.
(a
]
ldr w0, [x0, 3424]
add w0, w1, w0
ret
OK for trunk?
ChangeLog:
2016-09-06 Wilco Dijkstra
gcc/
* config/aarch64/aarch64.c (aarch64_legitimize_address):
Avoid use of base_offset if offset already in range.
--
diff --git a/gcc/config/aarch64/aarch64.c b
James Greenhalgh wrote:
> I really don't like [1][2][3] this technique of attempting to work around
> register allocator issues using the disparaging mechanisms.
I don't see the issue as it is a standard mechanism to describe higher cost
to the register allocator. On the other had the use of '*' i
he other fixes in that bug.
Sure.
>
> ChangeLog:
> 2016-05-19 Wilco Dijkstra
>
> * gcc/config/aarch64/aarch64.h
> (CANNOT_CHANGE_MODE_CLASS): Remove.
> * gcc/config/aarch64/aarch64.c
> (aarch64_cannot_change_mode_class): Remove function.
>
The Cortex-A57 scheduler is missing fcsel, so add it.
OK for commit?
ChangeLog:
2016-06-02 Wilco Dijkstra
* config/arm/cortex-a57.md (cortex_a57_fp_cpys): Add fcsel.
---
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index
ping
From: Wilco Dijkstra
Sent: 17 May 2016 17:08
To: James Greenhalgh
Cc: gcc-patches@gcc.gnu.org; nd
Subject: Re: [PATCH][AArch64] Improve aarch64_modes_tieable_p
James Greenhalgh wrote:
> It would be handy if you could raise something in bugzilla
agree on alignment of
16 for function, and 8 for loops and branches, so we should change
-mcpu=generic as well if there is no disagreement - feedback welcome.
OK for commit?
ChangeLog:
2016-05-03 Wilco Dijkstra
* gcc/config/aarch64/aarch64.c (cortexa53_tunings):
Increase loop
This patch cleans up the -mpc-relative-loads option processing. Rename to
avoid the
"no*" name and confusing !no* expressions. Fix the option processing code to
implement
-mno-pc-relative-loads rather than ignore it.
OK for commit?
ChangeLog:
2016-06-03 Wilco Dijkstra
ping
From: Wilco Dijkstra
Sent: 03 June 2016 11:51
To: GCC Patches
Cc: nd; philipp.toms...@theobroma-systems.com; pins...@gmail.com;
jim.wil...@linaro.org; benedikt.hu...@theobroma-systems.com; Evandro Menezes
Subject: [PATCH][AArch64] Increase code alignment
Increase loop alignment on
Due to recent improvements to the vectorizer, the number of vectorized
loops needs to be increased to 21 in gfortran.dg/vect/vect-8.f90.
Confirmed this test now passes on AArch64.
Commited as trivial patch in r237650.
ChangeLog:
2016-06-21 Wilco Dijkstra
* gfortran.dg/vect/vect-8
Fix tree-ssa/attr-hotcold-2.c failures now that the test runs.
GCC dumps the blocks 3 times so update count to 3 and the test passes.
ChangeLog:
2016-06-21 Wilco Dijkstra
gcc/testsuite/
* gcc.dg/tree-ssa/attr-hotcold-2.c (scan-tree-dump-times):
Set to 3 so test passes.
--
diff
return
true for AArch64 so these tests are run on AArch64 too.
Committed as trivial patch in r237653.
ChangeLog:
2016-06-21 Wilco Dijkstra
gcc/testsuite/
* gcc.target/aarch64/advsimd-intrinsics/vrnd.c
(dg-require-effective-target): Use arm_v8_neon_hw.
* gcc.target
bolic
number
never matches in big-endian.
The test gcc.dg/optimize-bswapsi-4.c now passes on AArch64, no other changes.
OK for commit?
ChangeLog:
2016-06-23 Wilco Dijkstra
* gcc/tree-ssa-math-opts.c (find_bswap_or_nop_1): Adjust bitnumbering
for big-endian BIT_FIELD_REF.
--
code is now more similar as well as more
optimal
across Cortex cores.
Regress passes, OK for commit?
ChangeLog:
2016-06-29 Wilco Dijkstra
* config/aarch64/aarch64.c (cortexa35_tunings):
Enable AES fusion. Use cortexa57_branch_cost.
(cortexa53_tunings): Use
Hi,
Sorry for the delay - I finally had a chance to look at this again.
I'll start with alloca:
@@ -15245,6 +15455,28 @@ aarch64_sched_can_speculate_insn (rtx_insn *insn)
}
}
+/* It has been decided that to allow up to 1kb of outgoing argument
+ space to be allocated w/o probing. If m
Jeff Law wrote:
>> Btw reminds me a little bit of
>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=28417
> I wouldn't expect 28417
> to move forward without something other than Tege and Denys pushing on it.
Hmm that doesn't look optimal. You can typically do a multiply with the magic
constant
Hi,
To continue the review of the AArch64 frame code I tried a few examples
to figure out what it does now. For initial_adjust <= 63*1024 and final_adjust <
1024 there are no probes inserted as expected, ie. the vast majority of
functions are unaffected. So that works perfectly.
For larger frames
Qing Zhao wrote:
> Is my patch Okay?
Given it's a mid-end patch this shouldn't be marked as AArch64 specific.
Similarly the PR needs to be updated to say middle-end. So resending
it making it clear it's not a target bug should help getting a review.
Wilco
Hi,
Here is the list of my AArch64 patches for review:
* https://gcc.gnu.org/ml/gcc-patches/2017-01/msg01216.html (Fix symbol offset
limit)
* https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00396.html (PR60580: Fix frame
pointer option magic)
* https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00359
dress, but it now defines a total
sorting order. More work will be required to improve the sorting so
that only loads/stores with the same base are affected.
AArch64 bootstrap completes.
OK for commit?
ChangeLog:
2017-10-03 Wilco Dijkstra
PR rtl-optimization/82396
* gcc/
ping
Kyrill Tkachov wrote:
> On 14/12/16 16:37, Wilco Dijkstra wrote:
>
> > Merge the movdi_vfp_cortexa8 pattern into movdi_vfp and remove it to avoid
> > unnecessary duplication and repeating bugs like PR78439 due to changes being
> > applied only to one of the dupli
ping
From: Wilco Dijkstra
Sent: 17 January 2017 19:23
To: GCC Patches
Cc: nd; Kyrill Tkachov; Richard Earnshaw
Subject: [PATCH][ARM] Remove DImode expansions for 1-bit shifts
A left shift of 1 can always be done using an add, so slightly adjust rtx
cost for DImode left shift by 1 so
Recently the gcc.dg/vect/pr31699.c was modified to check for
vect_float effective target instead for vect_double. As a
result it now fails on armhf. Fix by avoiding double.
Tested on armhf, aarch64 and x64.
Committed as trivial.
ChangeLog:
2017-10-16 Wilco Dijkstra
gcc/testsuite
Wilco Dijkstra wrote:
>
> Yes STACK_BOUNDARY applies to virtual_stack_dynamic_rtx and all other
> virtual frame registers. It appears it's main purpose is to enable alignment
> optimizations since PREFERRED_STACK_BOUNDARY is used to align
> local and outgoing argument area
is reversed.
Both transformations are only done with -funsafe-math-optimizations,
the constant is non-zero, and not a NaN.
OK for commit?
ChangeLog
2017-10-17 Wilco Dijkstra
Jackson Woodruff
gcc/
PR 71026/tree-optimization
* match.pd: Simplify floating point
?
ChangeLog
2017-10-17 Wilco Dijkstra
Jackson Woodruff
gcc/
PR 71026/tree-optimization
* match.pd: Canonicalize negate in division.
gcc/testsuite/
PR 71026/tree-optimization
* gcc.dg/div_neg: New test.
--
diff --git a/gcc/match.pd b/gcc
(C3 * x) / y) and to enable more reciprocal CSEs.
OK for commit?
ChangeLog
2017-10-17 Wilco Dijkstra
Jackson Woodruff
gcc/
PR 71026/tree-optimization
* match.pd: Canonicalize constant multiplies in division.
gcc/testsuite/
PR 71026/tree-optimizat
Vladimir wrote:
+# Disable floating-point expression contraction
+LIBGCC2_FFP_CONTRAST_CFLAGS = -ffp-contract=off
+
It looks like this disables fp-contract in all of libgcc...
What is the the number of FMAs in libgcc before/after?
If it disables anything other than the ones in complex division,
Vladimir Mezentsev
> On 10/19/2017 06:37 AM, Richard Earnshaw (lists) wrote:
>> On 19/10/17 14:07, Wilco Dijkstra wrote:
>>> Vladimir wrote:
>>>
>>> +# Disable floating-point expression contraction
>>> +LIBGCC2_FFP_CONTRAST_CFLAGS = -ffp-contract=off
James Greenhalgh wrote:
>
> This code is a mess, would macroing your magic number 2 help at all? All the
> double negatives give me a massive headache!
Well we really need to rename flag_omit_frame_pointer to flag_use_frame_pointer
or similar (omit and emit are too similar!). That removes most dou
cases, and leaf frame pointer
emission can't be supported).
OK for commit?
2017-10-25 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_use_frame_pointer):
Add new boolean.
(aarch64_needs_frame_chain): New function.
(aarch64_parse_override_st
s for fast compilation, but
also produces code that is efficient, readable as well as debuggable.
Therefore -Og makes for a much better default setting.
Any comments?
2017-10-26 Wilco Dijkstra
* opts.c (default_options_optimization): Set default to -Og.
doc/
* invoke.texi (-O0) R
Andrew Pinski wrote:
> I think this goes against what most folks are used to. I know you are
> saying most folks are used to a compiler defaulting to optimizations
> on but I don't think that is true. In fact GCC has been this way
> since day one.
Well it may depend which part of the industry y
x0, x0, 1
ret
OK for commit?
2017-10-27 Wilco Dijkstra
* common.opt (fmath-errno): Change default to 0.
* opts.c (set_fast_math_flags): Force -fno-math-errno with -ffast-math.
doc/
* invoke.texi (-fmath-errno) Update documentation.
--
diff --git a/gcc/commo
Kyrill Tkachov wrote:
> On 16/10/17 12:30, Wilco Dijkstra wrote:
> > DImode right shifts of 1 are rarely used (6 in total in the GCC binary),
> > so there is little benefit of the arm_ashrdi3_1bit and arm_lshrdi3_1bit
> > patterns.
>
> ... but it's still used, and
Richard Biener wrote:
> Should we also get the __ieee764_ entries used if the compiler sets
> __NO_MATH_ERRNO__? That is, if the librari advertises not setting errno
> via math_errhandling is it still allowed to set/clobber errno anyways?
That's a good question! I checked and the math wrappers cu
Dominik wrote:
> Could you please also commit the patch? I don’t have commit rights.
I've committed it as r254236.
Wilco
The AArch64 backend currently doesn't set MALLOC_ABI_ALIGNMENT, so
add this to enable alignment optimizations on malloc pointers.
OK for commit?
2017-10-31 Wilco Dijkstra
* config/aarch64/aarch64.h (MALLOC_ABI_ALIGNMENT): New define.
--
diff --git a/gcc/config/aarch64/aarch64.h
handles the constant addresses,
and the remaining ones are LABEL_REFs, which is also handled. So I don't see
what case could be missing...
I've tweaked the code to use split_const like elsewhere:
2017-10-31 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_legitimate_constant_p
Richard Earnshaw wrote:
> On 01/11/17 17:40, James Greenhalgh wrote:
>> As far as I understand it, because we have 128-bit types, a malloc of
>> anything greater than 16 bytes would require 16-byte alignment. So, assuming
>> this macro isn't required to desribe possibly unaligned smaller allocatio
?
2017-11-02 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_override_options_internal):
Set PARAM_SCHED_PRESSURE_ALGORITHM to SCHED_PRESSURE_MODEL.
--
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index
34456e96497ac7b6d2f9931187ff05619e1934a4
Richard Biener wrote:
> On Fri, Nov 3, 2017 at 6:38 AM, Andrew Pinski wrote:
> > On Fri, Nov 3, 2017 at 12:11 AM, Wilco Dijkstra
> > wrote:
> >> The Arm backend sets the default sched-pressure algorithm to
> >> SCHED_PRESSURE_MODEL. Benchmarking on AArch64 s
sult there are far fewer
patterns that need the attribute, and omitting predicable_short_it is no longer
causing issues.
This fixes 4 tests that failed after r254233, OK for commit?
ChangeLog:
2017-11-03 Wilco Dijkstra
* config/arm/arm.md (predicable_short_it): Change defa
ve reverted part of the patch that caused
this.
The tests are definitely too picky but they also uncovered a real code
generation
inefficiency, so I need to look into that further.
I've committed this:
2017-11-03 Wilco Dijkstra
PR target/82786
* config/aarch64/aarch64.c (a
, reducing
the amount of target code.
Verified all targets built by buildmanyglibcs script do still build.
OK for commit?
ChangeLog:
2017-11-03 Wilco Dijkstra
* opts.c (default_options_table): Add OPT_fomit_frame_pointer entry.
* common/config/alpha/alpha-common.c
Maxim Kuvyrkov wrote:
> > On Nov 2, 2017, at 9:41 PM, Wilco Dijkstra wrote:
> >
> > The Arm backend sets the default sched-pressure algorithm to
> > SCHED_PRESSURE_MODEL. Benchmarking on AArch64 shows this
> > speeds up floating point performance on SPEC - eg.
Richard Sandiford wrote:
>
> Yeah, I'd hit this too. I think it's a latent bug that just
> happened to be exposed by Wilco's patch: although the *movti_aarch64
> predicate disallows const_wide_int, the constraints allow it via "n",
> which means that the RA can rematerialise a const_wide_int that
Sudi Das wrote:
> Thanks, I have made the changes to the patch.
> Also can someone please apply it for me. I do not have commit access.
>
> 2017-10-10 Sudakshina Das
>
> PR middle-end/80131
> * match.pd: Simplify 1 << (C - x) where C = precision (x) - 1.
>
> 2017-10-10 Sudakshina
Christophe Lyon wrote:
> This causes my builds (all arm and aarch64 targets) to fail:
Richard Biener already committed a fix in r254498 (thanks).
It seems constants in match.pd now need wi::to_wide.
Wilco
Joseph Myers wrote:
On Mon, 30 Oct 2017, Wilco Dijkstra wrote:
> The semantics of __*_finite definitely include finite-math-only, as they
> aren't all just disabling the wrappers (e.g. sysdeps/i386/i686/fpu/e_log.S
> has __log_finite separate from __ieee754_log).
I only see a f
Andrew Pinski wrote:
>
> This looks related to PR 80266 in that one was crashing due to the
> store pair instruction like what was reported.
Yes it's the same bug. I've now finally reproduced it, it seems many stack
addresses in Ada are SImode which is incorrect (and ultimately can trigger
the LD
codesize reduces by 0.08%, SPEC2017 by 0.13%.
Bootstrap OK, OK for commit?
ChangeLog:
2017-07-07 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_legitimate_constant_p):
Return true for more constants, symbols and label references.
(aarch64_valid_floating_const
Michael Collison wrote:
>
> The subtract instruction only reliably sets the N and Z flags. We convey this
> information in
> aarch64_seelct_cc_mode.
The SUBS and CMP set the N and Z flags identically - although they also set C
and V, they
are different if there is overflow. CC_NZmode is used af
Jeff Law wrote:
> aarch64 is the first target that does not have any implicit probes in
> the caller. Thus at prologue entry it must make conservative
> assumptions about the offset of the most recent probed address relative
> to the stack pointer.
No - like I mentioned before that's not correct
Jakub Jelinek wrote:
> On Wed, Jul 12, 2017 at 12:20:32AM +0000, Wilco Dijkstra wrote:
> > Therefore even when using a tiny 4K probe size we can safely adjust SP by
> > 3KB
> > before needing an explicit probe - now only 0.6% of functions need a probe.
> > If we ch
backport?
ChangeLog:
2017-06-27 Wilco Dijkstra
PR target/79041
* config/aarch64/aarch64.c (aarch64_classify_symbol):
Avoid SYMBOL_SMALL_ABSOLUTE .
* testsuite/gcc.target/aarch64/pr79041-2.c: New test.
--
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64
.
SPEC2006 codesize reduces by 0.08%, SPEC2017 by 0.13%.
Bootstrap OK, OK for commit?
ChangeLog:
2017-07-07 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_legitimate_constant_p):
Return true for more constants, symbols and label references
ping
From: Wilco Dijkstra
Sent: 17 January 2017 15:14
To: Richard Earnshaw; GCC Patches; James Greenhalgh
Cc: nd
Subject: Re: [PATCH v3][AArch64] Fix symbol offset limit
Here is v3 of the patch - tree_fits_uhwi_p was necessary to ensure the size of a
declaration is an integer. So the
ping
Wilco Dijkstra wrote:
> James Greenhalgh wrote:
>
> > I note this is still marked as an RFC, are you now proposing it as a
> > patch to be merged to trunk?
>
> Absolutely. It was marked as an RFC to get some comments - I thought it
> may be controve
Jeff Law wrote:
> So would a half-half (2k caller/2k callee) split like Florian has
> proposed work for you? ie, we simply declare a caller that pushes the
> stack pointer 2k or more into the guard as broken?
My results show using a 4KB guard size is not ideal. 2KB of outgoing
args is too large
Jeff Law wrote:
> On 07/17/2017 05:27 AM, Wilco Dijkstra wrote:
> > A minimum guard size of 64KB seems reasonable even on systems with
> > 4KB pages. However whatever the chosen guard size, you cannot defend
> > against hostile code. An OS can of course increas
Hi Jeff,
There is an issue with your AArch64 patch, it fails to apply properly and does
so silently using 'patch'. I also noticed some odd control characters in the
other
patches, but they didn't appear to fail (or at least everything builds).
Anyway with -Ofast -static the overall codesize incr
, [x1]
OK for commit?
ChangeLog:
2017-06-20 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_legitimize_address_displacement):
Improve unaligned TImode/TFmode base/offset split.
testsuite
* gcc.target/aarch64/ldp_stp_unaligned_2.c: New file.
--
diff --git a/gcc/config
bl foo3
ldr x30, [sp], 32
ret
On SPEC2017 codesize improves uniformly across the board.
ChangeLog:
2017-07-20 Wilco Dijkstra
PR middle-end/46932
* auto-inc-dec.c (parse_add_or_inc): Block autoinc on sfp.
gcc/testsuite/
* gcc.dg/pr46932.c: New
/GCC7 backport?
ChangeLog:
2017-06-27 Wilco Dijkstra
PR target/79041
* config/aarch64/aarch64.c (aarch64_classify_symbol):
Avoid SYMBOL_SMALL_ABSOLUTE .
* testsuite/gcc.target/aarch64/pr79041-2.c: New test.
--
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config
spills.
SPEC2006 codesize reduces by 0.08%, SPEC2017 by 0.13%.
Bootstrap OK, OK for commit?
ChangeLog:
2017-07-07 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_legitimate_constant_p):
Return true for more constants, symbols and label references
ping
From: Wilco Dijkstra
Sent: 17 January 2017 15:14
To: Richard Earnshaw; GCC Patches; James Greenhalgh
Cc: nd
Subject: Re: [PATCH v3][AArch64] Fix symbol offset limit
Here is v3 of the patch - tree_fits_uhwi_p was necessary to ensure the size of a
declaration is an integer. So the
ping
Wilco Dijkstra wrote:
> James Greenhalgh wrote:
>
> > I note this is still marked as an RFC, are you now proposing it as a
> > patch to be merged to trunk?
>
> Absolutely. It was marked as an RFC to get some comments - I thought it
> may be controve
Jeff Law wrote:
> Examples please? We should be probing the outgoing args at the probe
> interval once the total static frame is greater than 3k. The dynamic
> space should be probed by generic code.
OK, here are a few simple examples that enable a successful jump of the stack
guard despit
James Greenhalgh wrote:
>
> OK. Either like this, or with the conditions swapped around as Yvan
> suggested to make backporting easier.
I swapped the conditions around, not sure whether it helps...
Also I needed an additional scan-assembler, this was committed to
trunk and GCC7:
diff --git a/gcc/
Ramana Radhakrishnan
>
> BZ suggests that this affects GCC 6 but GCC 7 is fixed ? Should there
> be a backport to GCC 6 as well ?
>
> Can you please keep BZ up to date please ?
GCC7 was affected as well, the example in PR79041 didn't trigger in GCC7,
my patch has a better example that does show t
bottom of the callee-saves even with -fomit-frame-pointer.
Also remove a rarely used frame layout that saves the callee-saves first
with -fomit-frame-pointer.
OK for commit (and backport to GCC7)?
ChangeLog:
2017-07-25 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_layout_frame
Jeff Law wrote:
> My only concern here would be cases where we don't end up eliminating FP
> to SP. But I'd think it's unlikely that we'd have enough auto-inc
> opportunities on the frame pointer for it to matter much anyway.
What kind of case are you thinking of? Whether it is SP or FP doesn't
Andreas Schwab wrote:
> That fails in ILP32 mode.
Well -mabi-ilp32 and -mcmodel=large make no sense at all,
that should really give an error... I've committed a patch to
trunk and GCC7 to disable this test with ILP32.
Wilco
t moves, for
example gcc.target/aarch64/pr62178.c no longer generates a redundant fmov
since the w = m variant is now allowed.
Passes regress & bootstrap, OK for commit?
ChangeLog:
2017-07-26 Wilco Dijkstra
* gcc/config/aarch64/aarch64.md (movsi_aarch64): Remove all '*'.
, -16
sub sp, sp, x0
add x0, sp, 63
and x0, x0, -64
ChangeLog:
2017-07-26 Wilco Dijkstra
* explow.c (get_dynamic_stack_size): Improve dynamic alignment.
--
diff --git a/gcc/explow.c b/gcc/explow.c
index
50074e281edd5270c76d29feac6b7a92f598d11d
Jeff Law wrote:
> + if (required_align > MAX_SUPPORTED_STACK_ALIGNMENT)
> + {
> + extra = (required_align - MAX_SUPPORTED_STACK_ALIGNMENT)
> + / BITS_PER_UNIT;
> + size = plus_constant (Pmode, size, extra);
> + size = force_operand (size, NULL_RTX);
>
> - if (extra && siz
GCC6/7?
ChangeLog:
2017-07-31 Wilco Dijkstra
PR target/71951
* config/aarch64/aarch64.h (LIBGCC2_UNWIND_ATTRIBUTE): Define.
--
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index
7f91edb5713d7e8eda2f0a024a0f97b4e111c4b0
ping
From: Wilco Dijkstra
Sent: 26 July 2017 14:46
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] Remove '*' from movsi/di/ti patterns
Remove the remaining uses of '*' from the movsi/di/ti patterns.
Using '*' in alternatives is typic
ping
From: Wilco Dijkstra
Sent: 25 July 2017 14:58
To: GCC Patches; James Greenhalgh; Jeff Law
Cc: nd
Subject: [PATCH][AArch64] Simplify frame layout for stack probing
This patch makes some changes to the frame layout in order to simplify
stack probing. We want to use the save of LR as a
ping
Wilco Dijkstra wrote:
> James Greenhalgh wrote:
>
> > I note this is still marked as an RFC, are you now proposing it as a
> > patch to be merged to trunk?
>
> Absolutely. It was marked as an RFC to get some comments - I thought it
> may be controve
ping
From: Wilco Dijkstra
Sent: 17 January 2017 15:14
To: Richard Earnshaw; GCC Patches; James Greenhalgh
Cc: nd
Subject: Re: [PATCH v3][AArch64] Fix symbol offset limit
Here is v3 of the patch - tree_fits_uhwi_p was necessary to ensure the size of a
declaration is an integer. So
spills.
SPEC2006 codesize reduces by 0.08%, SPEC2017 by 0.13%.
Bootstrap OK, OK for commit?
ChangeLog:
2017-07-07 Wilco Dijkstra
* config/aarch64/aarch64.c (aarch64_legitimate_constant_p):
Return true for more constants, symbols and label references
ping
From: Wilco Dijkstra
Sent: 20 July 2017 13:49
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] Improve addressing of TI/TFmode
In https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01125.html Jiong
pointed out some addressing inefficiencies due to a recent change in
This patch simplifies pow (C, x) into exp (x * C1), where C1 = log (C).
Do this only for fast-math as accuracy is reduced. This is much faster
since pow is more complex than exp - with a current GLIBC the speedup
is more than 7 times for this transformation.
ChangeLog:
2017-08-04 Wilco Dijkstra
The frame code uses a mixture of gen_rtx_MEM and gen_frame_mem for
callee-saves. Callee-saves never alias with local variables, so using
gen_frame_mem is correct. Minor cleanup - no change in code.
OK for commit?
ChangeLog:
2017-08-04 Wilco Dijkstra
gcc/
* config/aarch64/aarch64
before, so generated code is identical.
Also correctly set EXIT_IGNORE_STACK. The current AArch64 epilog code
restores SP from FP if alloca is used. If a frame pointer is used but
there is no alloca, SP must remain valid for the epilog to work correctly.
ChangeLog:
2017-08-03 Wilco Dijkstra
frame_pointer_needed via aarch64_frame_pointer_required, but enable the
frame chain in aarch64_layout_frame. Now aarch64_frame_pointer_required
can be removed and aarch64_can_eliminate is simplified.
OK for commit?
ChangeLog:
2017-08-03 Wilco Dijkstra
gcc/
* config/aarch64/aarch64.c
Richard Biener wrote:
> On Fri, Aug 4, 2017 at 2:26 PM, Alexander Monakov wrote:
> > On Fri, 4 Aug 2017, Wilco Dijkstra wrote:
> >> This patch simplifies pow (C, x) into exp (x * C1), where C1 = log (C).
> >
> > I don't think you can do that for non-po
to be
independently set and changed in each function with the expected behaviour.
OK for commit and backport to GCC7/GCC6?
ChangeLog:
2017-08-04 Wilco Dijkstra
gcc/
PR middle-end/60580
* config/aarch64/aarch64.c (aarch64_frame_pointer_required)
Check special val
Build only if pre-increment is supported. Given there is no config test,
add a list of targets which have HAVE_PRE_INCREMENT set.
Committed as obvious.
2017-08-07 Wilco Dijkstra
PR middle-end/46932
* gcc.dg/pr46932.c: Compile on targets with pre-increment.
--
diff --git a
Simplify aarch64_can_eliminate - if we need a frame pointer, we must
eliminate to HARD_FRAME_POINTER_REGNUM. Rather than hardcoding all
combinations from the ELIMINABLE_REGS list, just do the correct check.
ChangeLog:
2017-08-07 Wilco Dijkstra
gcc/
* config/aarch64/aarch64.c
Richard Earnshaw wrote:
>
> Except that I think this would be better done as an 'effective target'
> test; something like
>
> dg-require-effective-target autoincdec
>
> that way new ports will be more likely to pick up relevant tests like this.
Sure but what would be a correct implementation of
Richard Kenner wrote:
>Michael Collison wrote:
> > On Aarc64 SHIFT_COUNT_TRUNCATED is only true if SIMD code generation
> > is disabled. This is because the simd instructions can be used for
> > shifting but they do not truncate the shift count.
>
> In that case, the change isn't safe! Consider if
a better way of doing this I'd like to know!
Add check_effective_target_autoincdec that returns true if a target
runs the auto_inc_dec optimization pass.
OK for commit?
ChangeLog:
2017-08-08 Wilco Dijkstra
gcc/testsuite/
* gcc.dg/pr46932.c: Use effective_target autoi
Kugan wrote:
> Ping^2?
Could you make sure to either include the patch or provide a link to it?
(https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01967.html)
I think the patch is fine since avoiding adrp/ldr on literals doesn't really
help when global variables still use adrp. If you really want to
Fix longbranch test so it still generates long tbz branches.
Committed as obvious.
ChangeLog:
2017-08-14 Wilco Dijkstra
gcc/testsuite/
PR target/81643
* gcc.target/aarch64/long_branch_1.c: Improve testcase.
--
diff --git a/gcc/testsuite/gcc.target/aarch64/long_branch_1.c
Richard Biener wrote:
> > We also change the association of
> >
> > x / (y * C) -> (x / C) / y
> >
> > If C is a constant.
>
> Why's that profitable?
It enables (x * C1) / (y * C2) -> (x * C1/C2) / y for example.
Also 1/y is now available to the reciprocal optimization, see
https://gcc.gnu.o
ping
From: Wilco Dijkstra
Sent: 04 August 2017 16:46
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] PR60580: Fix frame pointer option magic
To fix PR60580 simplify the logic in aarch64_override_options_after_change_1 ().
If the frame pointer is enabled, set it to a
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