On 2023/12/13 22:45, Mark Rutland wrote:
> On Wed, Dec 13, 2023 at 05:01:07PM +0800, Wang wrote:
>> On 2023/12/13 16:48, Dan Li wrote:
>>> + Likun
>>>
>>> On Tue, 28 Mar 2023 at 06:18, Sami Tolvanen wrote:
>>>> On Mon, Mar 27, 2023 at 2:30 AM Peter
On 2023/12/14 03:35, Kees Cook wrote:
> On Wed, Dec 13, 2023 at 05:01:07PM +0800, Wang wrote:
>> On 2023/12/13 16:48, Dan Li wrote:
>>> + Likun
>>>
>>> On Tue, 28 Mar 2023 at 06:18, Sami Tolvanen wrote:
>>>> On Mon, Mar 27, 2023 at 2:30 AM Peter Z
ich requires a deep understanding of the compiler and
language processing parts.
And for the kernel cfi, I suggest separating type compatibility from CFI
basic functions. Type compatibility is independent from CFI basic
funcitons and should be dealt with under another topic. Should we focus
on
lems.
Thank you again!
--
Feng Wang
>Proposed fix, and verified with "mawk" and "gawk -P" (gawk with posix
>mode) on my linux also some other report it work on freebsd, just wait
>review :)
>
>https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631785
> It would be nice to add to the documentation that INSN_BASE_REG_CLASS,
> INSN_INDEX_REG_CLASS, and REGNO_OK_FOR_INSN_BASE_P if defined have
> priority over older corresponding macros as it is already documented for
> REGNO_MODE_CODE_OK_FOR_BASE_P relating to REGNO_OK_FOR_BASE_P. But this
> small
From: Yanzhang Wang
We only need to pass options to the linker when static-pie is passed.
There's another patch to enable static-pie in glibc. And we need to
enable in GCC first.
gcc/ChangeLog:
* config/riscv/linux.h: Pass the static-pie specific options to
the l
Since -mapxf works similar as -muintr that will emit error for 32bit
target, add !ia32 target guard for apx related tests.
Committed as obvious fix after test.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-egprs-names.c: Compile for non-ia32.
* gcc.target/i386/apx-inline-gpr-nor
For vec_concatv2di, m constraint in alternative 0 and 1 could result in
egpr allocated on operand 2 under -mapxf. Should use jm instead.
Bootstrapped/regtested on x86-64-linux-gnu.
Ok for trunk?
gcc/ChangeLog:
* config/i386/sse.md (vec_concatv2di): Replace constraint "m"
with "j
Thanks, also there is another pattern missed that should use "ja" instead
of Bm. Will commit below changes.
gcc/ChangeLog:
* config/i386/sse.md (vec_concatv2di): Replace constraint "m"
with "jm" for alternative 0 and 1 of operand 2.
(sse4_1_3): Replace constraint "Bm" with
: New test.
* gcc.target/i386/apx-push2pop2_force_drap-1.c: Likewise.
* gcc.target/i386/apx-push2pop2_interrupt-1.c: Likewise.
Co-authored-by: Hu Lin1
Co-authored-by: Hongyu Wang
---
gcc/config/i386/i386.cc | 252 --
gcc/config/i3
On 10/17/23 22:06, Xi Ruoyao wrote:
During the review of a LLVM change [1], on LA464 we found that zeroing
"an" LLVM change (because the word LLVM is pronounced letter-by-letter)
a fcc with fcmp.caf.s is much faster than a movgr2cf from $r0.
Similarly, "an" fcc
[1]: https://github.com/llvm
On 2023-03-01 09:46 Feng Wang wrote:
>
>The Mask flag in the single TargetVariable is not enough due to more
>and more extensions were added.So I optimize the defination of Mask
>flag, please refer to the below case:
>There are some new MASK flags for 'v' extension(ZV
Ping, I will rebase if the change is fine to you, thanks!
On 2023-03-01 09:46 Feng Wang wrote:
>
>The Mask flag in the single TargetVariable is not enough due to more
>and more extensions were added.So I optimize the defination of Mask
>flag, please refer to the below case:
>The
Hi,
On 2023/6/7 10:31, Lulu Cheng wrote:
If the $ra register is modified during the jump to the jump table, the hardware
branch prediction function will be broken, resulting in a significant increase
in the branch false prediction rate and affecting performance.
Thanks for the insight! This is
On 2023/6/7 11:36, Lulu Cheng wrote:
在 2023/6/7 上午11:26, WANG Xuerui 写道:
Hi,
On 2023/6/7 10:31, Lulu Cheng wrote:
If the $ra register is modified during the jump to the jump table,
the hardware
branch prediction function will be broken, resulting in a significant
increase
in the branch
On 2023/6/8 10:27, Lulu Cheng wrote:
Micro-architecture unconditionally treats a "jr $ra" as "return from
subroutine",
hence doing "jr $ra" would interfere with both subroutine return prediction and
the more general indirect branch prediction.
Therefore, a problem like PR110136 can cause a sign
Hi,
On 2022/7/7 16:04, Lulu Cheng wrote:
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_compute_frame_info):
Modify fp_sp_offset and gp_sp_offset's calculation method,
when frame->mask or frame->fmask is zero, don't minus UNITS_PER_WORD
or UNITS_PER_FP
Hi,
On 2022/7/27 15:06, Xi Ruoyao wrote:
Document newly introduced -m[no-]explicit-relocs options. Ok for trunk?
-- >8 --
gcc/ChangeLog:
* doc/invoke.texi: Document -m[no-]explicit-relocs for
LoongArch.
---
gcc/doc/invoke.texi | 12
1 file changed, 12 insertio
On 2022/7/27 17:28, Lulu Cheng wrote:
在 2022/7/27 下午5:15, Xi Ruoyao 写道:
On Wed, 2022-07-27 at 16:47 +0800, Lulu Cheng wrote:
"Use or do not use assembler relocation operators when dealing with
symbolic addresses. The alternative is to use assembler macros
instead, which may limit optimizat
On 2022/8/3 09:36, Xi Ruoyao wrote:
Is it OK for trunk or I need to change something?
By the way, I'm seeking a possibility to include this into 12.2. Then
we leaves only 12.1 without this attribute, and we can just say
"building the kernel needs GCC 12.2 or later".
On Mon, 2022-08-01 at 18:07
On 2022/8/5 15:19, Lulu Cheng wrote:
在 2022/8/5 下午2:03, Xi Ruoyao 写道:
On Fri, 2022-08-05 at 12:01 +0800, Lulu Cheng wrote:
在 2022/8/5 上午11:45, Xi Ruoyao 写道:
On Fri, 2022-08-05 at 11:34 +0800, Xi Ruoyao via Gcc-patches wrote:
Or maybe we should just use a PC-relative addressing with 4 inst
Hi,
On 6/15/23 17:03, Xi Ruoyao wrote:
Xuerui: I guess this makes it sensible to show "ret" instead of "jirl
$zero, $ra, 0" in objdump -d output, but I don't know how to implement
it. Do you have some idea?
Thanks for the suggestion! Actually I have previously made this patch
series [1] whic
On 2023/6/30 10:16, Chenghui Pan wrote:
[snip]
---
gcc/config/loongarch/constraints.md| 128 +-
gcc/config/loongarch/loongarch-builtins.cc | 10 +
gcc/config/loongarch/loongarch-modes.def | 38 +
gcc/config/loongarch/loongarch-protos.h| 31 +
gcc/config/loongarch/loo
Thanks for the fix and refinement!
I think the addr attr looks more reasonable, just one small issue that
EGPR was not only encoded with REX2 prefix, there are several
instructions that encode EGPR using evex prefix. So I think
addr_rex2/addr_rex may be a misleading note. I'd prefer still using
gp
Hi,
On 2023/2/13 18:38, Xi Ruoyao wrote:
Multiarch tuple will be coded in file or directory names in
multiarch-aware distros, so one ABI should have only one multiarch
tuple. For example, "--target=loongarch64-linux-gnu --with-abi=lp64s"
and "--target=loongarch64-linux-gnusf" should both set mu
Hi,
On 2023/2/21 21:03, Lulu Cheng wrote:
在 2023/2/21 下午3:41, Xi Ruoyao 写道:
On Tue, 2023-02-21 at 15:20 +0800, Lulu Cheng wrote:
Like la264 only has 40 effective bits of virtual address space.
I'm OK with the change. But the VA length is configurable building the
kernel. Is there any speci
On 2023/2/22 17:30, Lulu Cheng wrote:
在 2023/2/21 下午9:56, WANG Xuerui 写道:
Hi,
On 2023/2/21 21:03, Lulu Cheng wrote:
在 2023/2/21 下午3:41, Xi Ruoyao 写道:
On Tue, 2023-02-21 at 15:20 +0800, Lulu Cheng wrote:
Like la264 only has 40 effective bits of virtual address space.
I'm OK with the c
The Mask flag in the single TargetVariable is not enough due to more
and more extensions were added.So I optimize the defination of Mask
flag, please refer to the below case:
There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B),
but these MASK flags can't store into x_target
t_args("TargetVariable", $1)
>+ var_index = find_index(target_var, target_vars, n_target_vars)
>+ if (var_index == n_target_vars)
>+ {
>+ target_vars[n_target_vars++] = target_var
>+ }
>+ other_masks[var_index][n_other_mask[var_index]++] = name
>+ }
>+ else
>+ {
>+ extra_masks[n_extra_masks++] = name
>+ }
> }
> }
> }
>diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
>index 8bba8ec4549..247a9fb8944 100644
>--- a/gcc/opth-gen.awk
>+++ b/gcc/opth-gen.awk
>@@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
> }
>
>+for (i = 0; i < n_target_vars; i++)
>+{
>+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars)
>== n_extra_target_vars)
>+ continue
>+ for (j = 0; j < n_other_mask[i]; j++)
>+ {
>+ print "#define MASK_" other_masks[i][j] " (1U << "
>other_masknum[i][""]++ ")"
>+ }
>+ if (other_masknum[i][""] > 32)
>+ print "#error too many target masks for" extra_target_vars[i]
>+}
>+
> for (var in masknum) {
> if (var != "" && host_wide_int[var] == "yes") {
> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " >
> HOST_BITS_PER_WIDE_INT"
>@@ -457,6 +469,16 @@ for (i = 0; i < n_extra_masks; i++) {
> print "#define TARGET_" extra_masks[i] \
> " ((target_flags & MASK_" extra_masks[i] ") != 0)"
> }
>+for (i = 0; i < n_target_vars; i++)
>+{
>+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars)
>== n_extra_target_vars)
>+ continue
>+ for (j = 0; j < n_other_mask[i]; j++)
>+ {
>+ print "#define TARGET_" other_masks[i][j] \
>+ " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
>+ }
>+}
> print ""
>
> for (i = 0; i < n_opts; i++) {
>--
>2.17.1
Hi Jiawei,
Thanks for your replay, I will try to optimize the generation code to eliminate
the redundant codes.
Wang Feng
Best regards
On 2023-03-03 17:12 Feng Wang wrote:
>
>On 2023-03-03 16:54 jiawei wrote:
>>
>>The Mask flag in the single TargetVariable is not enough due to more
>>and more extensions were added.So I optimize the defination of Mask
>>flag, please refer to the below case:
>>
On 2023/3/13 11:52, Lulu Cheng wrote:
LoongArch 32-bit instruction set does not support crc* and crcc* instructions.
gcc/ChangeLog:
* config/loongarch/larchintrin.h (__crc_w_b_w): Add macros for control.
(__crc_w_h_w): Likewise.
(__crc_w_w_w): Likewise.
(__crcc
On 2023/3/13 13:14, Xi Ruoyao wrote:
On Mon, 2023-03-13 at 12:58 +0800, Lulu Cheng wrote:
在 2023/3/13 下午12:54, Xi Ruoyao 写道:
On Mon, 2023-03-13 at 12:40 +0800, WANG Xuerui wrote:
This is ugly. The fact all current LA32 models don't support CRC
ops is
just a coincidence; it's entirel
On 2023/5/25 10:46, Lulu Cheng wrote:
在 2023/5/25 上午4:15, Jason Merrill 写道:
On Wed, May 24, 2023 at 5:00 AM Jonathan Wakely via Gcc-patches
mailto:gcc-patches@gcc.gnu.org>> wrote:
On Wed, 24 May 2023 at 09:41, Xi Ruoyao wrote:
> Wang Lei raised some concerns about Itaniu
On 2022/9/27 11:16, Lulu Cheng wrote:
r13-967 add ARRIF output format. However libvtv does not add support.
"SARIF support was added in r13-967 but libvtv wasn't updated."
(Tip: always remember that English, unlike Chinese, isn't a
"topic-prominent" language, meaning you should almo
Hi,
The code change seems good but a few grammatical nits.
Patch subject should be a verb phrase, something like "libvtv: add
LoongArch support" could be better.
On 2022/10/28 16:01, Lulu Cheng wrote:
After several considerations, I decided to set VTV_PAGE_SIZE to 16KB under
loongarch64.
On 4/25/22 13:57, Xi Ruoyao wrote:
Ping.
Normally we shouldn't ping a patch after only a few days, but we're
running out of time to catch GCC 12 milestone. And once GCC 12 is
released the patch will become far more complicated for a psABI warning.
And please note that the ABI difference betwee
For sure.
Jeff Law 于2020年1月15日周三 上午4:48写道：
>
> On Tue, 2019-12-24 at 13:31 +0800, Hongyu Wang wrote:
> > Hi:
> > For avx512f scalar instructions, current builtin function like
> > __builtin_ia32_*{sd,ss}_round can be replaced by
> > __builtin_ia32_*{sd,ss}_mask_ro
,
__builtin_ia32_vfmaddsd3_round,
__builtin_ia32_vfmaddss3_round): Remove.
*gcc.target/i386/sse-13.c: Ditto.
*gcc.target/i386/sse-23.c: Ditto.
Regards,
Hongyu Wang
From 9cc4928aad5770c53ff580f5c996092cdaf2f9ba Mon Sep 17 00:00:00 2001
From: hongyuw1
Date: Wed, 18 Dec 2019 14:52:54 +
Subject
The latest APX spec announced removal of SHA/KEYLOCKER evex promotion [1],
which means the SHA/KEYLOCKER insn does not support EGPR when APX
enabled. Update the corresponding constraints to their EGPR-disabled
counterparts.
Bootstrapped and regtested on x86-64-pc-linux-gnu.
Ok for trunk?
[1].htt
Thanks for fixing this! Didn't notice that the pointer conversion can
cause this issue...
Was it possible to use local array like
char a[64] = (char *)p
__asm__ volatile ("ldtilecfg\t%X0" :: "m" (a)));
If not, for the two patterns we can use "m" instead of "jm" as APX
supports EGPR extension for
Thanks, this is the patch I'm going to check-in
Hongtao Liu 于2024年1月10日周三 16:02写道：
>
> On Tue, Jan 9, 2024 at 3:09 PM Hongyu Wang wrote:
> >
> > Hi,
> >
> > For APX, the inline asm behavior was not mentioned in any document
> > before. Add description
The length of vfloat16m8_t ABI-name should be 17.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vfloat16m8_t):Modify ABI-name
length of vfloat16m8_t
---
gcc/config/riscv/riscv-vector-builtins.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/r
Committed, thanks.
From: juzhe.zh...@rivai.ai
Date: 2024-01-12 09:38
To: wangfeng; gcc-patches
CC: kito.cheng; jeffreyalaw; wangfeng
Subject: Re: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t
Good catch. LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-12 09:35
To: gcc
From: Yanzhang Wang
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete
From: Yanzhang Wang
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-call-args-1-run.c: Delete the
-Wno-psabi.
* gcc.target/riscv/rvv/base/abi-call-args-1.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-2-run.c: Ditto.
* gcc.target/riscv/rvv
I'm going to check-in this if no objection
Hongyu Wang 于2024年1月9日周二 15:14写道：
>
> Hi,
>
> This patch adds missing description for inline asm behavior and related
> compiler switch for APX.
>
> Ok for gcc-wwwdocs?
>
> ---
> htdocs/gcc-14/changes.html | 6 +++
From: Yanzhang Wang
Ran a full test to adjust some of the tests for scan-assembly. The
behavior is the same as --param=riscv-vector-abi before.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
(riscv_fntype_abi): Ditto.
* config/riscv
From: Yanzhang Wang
Also adjust some of the tests for scan-assembly. The behavior is the
same as --param=riscv-vector-abi before.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
(riscv_fntype_abi): Ditto.
* config/riscv/riscv.opt: Ditto
From: Yanzhang Wang
Also adjust some of the tests for scan-assembly. The behavior is the
same as --param=riscv-vector-abi before.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
(riscv_fntype_abi): Ditto.
* config/riscv/riscv.opt: Ditto
tions.def"
>+};
>Why do you add this ? I think it should belong to function_groups.
The original intention of this modification was to make the processing flow of
the crypto vector more clearer.
If you think it should merge into V extension, I will do it.
Thanks.
Feng Wang
>
>+ /*
Due to the crypto vector entension is depend on the Vector extension,
so add the implied ISA info with the corresponding crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Modify implied ISA info.
* config/riscv/arch-canonicalize: Add crypto vector impl
Hi,
Currently move_max follows the tuning feature first, but ideally it
should sync with prefer-vector-width when it is explicitly set to keep
vector move and operation with same vector size.
Bootstrapped/regtested on x86-64-pc-linux-gnu{-m32,}
OK for trunk?
gcc/ChangeLog:
PR target/11
This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc.
Will refactor this part in the same way as aarch64 sve.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
Revert changes.
This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc.
Will refactor this part in the same way as aarch64 sve.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
Revert changes.
Hi,
As Coudert points out, this test fails on darwin as it does not
support _Decimal64, so require dfp for it.
Pushed as obvious fix.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr112943.c: Require dfp.
---
gcc/testsuite/gcc.target/i386/pr112943.c | 2 +-
1 file changed, 1 insertion(+)
In order to add other vector related extensions in the future, this
patch add one more parameter in the function_group_info, it will be
used to determine whether intrinsic registration processing is required.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXT
In order to add other vector related extensions in the future, this
patch add one more parameter in the function_group_info, it will be
used to determine whether intrinsic registration processing is required.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXT
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
in
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destination register.
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto
2023-12-20 15:12 juzhe.zhong wrote:
>+ (and:VI
>+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr")
>+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")))
>Swap the order:
>
>(not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")
>
From: wangpc
The condition is RISCV_FUSE_ZEXTH, which is a mistake.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition.
---
gcc/config/riscv/riscv.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/ris
Patch v5: Add vec_duplicate operator. Make report riscv.exp with
"riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destinatio
On 2023/12/21 1:08, Jeff Law wrote:
>
>
> On 12/20/23 01:39, Wang Pengcheng wrote:
>> From: wangpc
>>
>> The condition is RISCV_FUSE_ZEXTH, which is a mistake.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix c
Patch v6: Swap the operator order of vandn.vv.Make report riscv.exp with
"riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed.
Patch v5: Add vec_duplicate operator.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vecto
Patch v7: Remove mode of const_int_operand and typo. Add
newline at the end and comment at the beginning.
Patch v6: Swap the operator order of vandn.vv
Patch v5: Add vec_duplicate operator.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patc
Patch v8: Remove unused iterator and add newline at the end.
Patch v7: Remove mode of const_int_operand and typo. Add
newline at the end and comment at the beginning.
Patch v6: Swap the operator order of vandn.vv
Patch v5: Add vec_duplicate operator.
Patch v4: Add process of SEW=64 in RV3
2023-12-22 09:59 Feng Wang wrote:
Sorry for forgetting to add the patch version number. It should be [PATCH v8
2/3]
>Patch v8: Remove unused iterator and add newline at the end.
>Patch v7: Remove mode of const_int_operand and typo. Add
> newline at the end and comme
/predef-align-8.c: New test.
* gcc.target/riscv/predef-align-9.c: New test.
Signed-off-by: Wang Pengcheng
---
gcc/config/riscv/riscv.opt | 4
gcc/testsuite/gcc.target/riscv/predef-align-10.c | 16
gcc/testsuite/gcc.target/riscv/predef-align-7.c | 15 +++
gcc/testsuite
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/iterators.md: Add rotate insn name.
* config/riscv/riscv.md: Add new insns name for crypto vector.
* config/riscv/vector-iterators.md: Add new iterators for crypto vector.
* config/
gcc/ChangeLog:
* config/riscv/vector-crypto.md: Modify copyright year.
---
gcc/config/riscv/vector-crypto.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector-crypto.md
b/gcc/config/riscv/vector-crypto.md
index e40b1543954..9625014e45e 100755
---
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vecto
Patch v5: Rebase.
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing case s.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
int (*avail) (void);
>+};
>
>What is this used for ?
Will delete it.
>
>
>juzhe.zh...@rivai.ai
>
>From: Feng Wang
>Date: 2024-01-02 15:47
>To: gcc-patches
>CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
>Subject: [PATCH v5 1/2] RISC-V: Add crypto vector
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intri
2024-01-03 00:32 Jeff Law wrote:
>
>
>On 1/1/24 19:25, Feng Wang wrote:
>> gcc/ChangeLog:
>> * config/riscv/vector-crypto.md: Modify copyright year.
>> ---
>> gcc/config/riscv/vector-crypto.md | 2 +-
>> 1 file changed, 1 insertion(+),
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://git
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vec
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/ri
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx
; Kito.cheng
Subject: Re: Re: [committed] RISC-V: Add crypto vector builtin function.
We (me and kito) has reviewed vector-crypto.
I believe Wang Feng has done && passed the regression (with no RTL check), but
he just didn't enable RTL check I guessed.
(By default, RTL check is disabled
Patch v7:Fix avl_type operand index of zvbc ins.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape c
s
>of vclmul and vclmulh instructions".
>
>
>
>juzhe.zh...@rivai.ai
>
OK. Will separate it.
>From: Feng Wang
>Date: 2024-01-05 16:51
>To: gcc-patches
>CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
>Subject: [PATCH v7 1/2] RISC-
This patch fix the rtl-checking error for crypto vector. The root
cause is the avl-type index of zvbc ins is error,it should be operand[8]
not operand[5].
gcc/ChangeLog:
* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
---
gcc/config/riscv/vector.md | 4 ++--
1 file ch
This patch fix the rtl-checking error for crypto vector. The root
cause is the avl-type index of zvbc ins is error,it should be operand[8]
not operand[5].
gcc/ChangeLog:
* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
---
gcc/config/riscv/vector.md | 4 ++--
1 file ch
Hi,
The supported sub-features for APX was missing in option document and
target attribute section. Add those missing ones.
Ok for trunk?
gcc/ChangeLog:
* config/i386/i386.opt: Add supported sub-features.
* doc/extend.texi: Add description for target attribute.
---
gcc/config/i
Patch v8: Resubmit after fix the rtl-checking issue. Passed all the riscv
regression test.
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patc
Patch v7:Resubmit after fix trl-checking issue. Passed all the riscv regression
test.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.d
Committed, thanks Juzhe.
发件人： 钟居哲
发送时间： 2024-01-09 07:02
收件人： wangfeng; gcc-patches
抄送： kito.cheng; Jeff Law; wangfeng
主题： Re: [PATCH v8 2/2] RISC-V: Add crypto vector api-testing cases.
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-08 17:12
To: gcc-patches
CC: kito.cheng
Committed, thanks Juzhe.
发件人： 钟居哲
发送时间： 2024-01-09 07:02
收件人： wangfeng; gcc-patches
抄送： kito.cheng; Jeff Law; wangfeng
主题： Re: [PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-08 17:12
To: gcc-patches
CC: kito.cheng
Hi,
For APX, the inline asm behavior was not mentioned in any document
before. Add description for it.
Ok for trunk?
gcc/ChangeLog:
* config/i386/i386.opt: Adjust document.
* doc/invoke.texi: Add description for
-mapx-inline-asm-use-gpr32.
---
gcc/config/i386/i386.opt |
Hi,
This patch adds missing description for inline asm behavior and related
compiler switch for APX.
Ok for gcc-wwwdocs?
---
htdocs/gcc-14/changes.html | 6 ++
1 file changed, 6 insertions(+)
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index e3a68998..73a90d30 1006
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvbc extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gcc/Cha
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvkg extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
Co-Autho
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvkned extension. And all
the test cases are added for api-testing.
gcc/ChangeLog:
* common/c
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvksed extension. And all
the test cases are added for api-testing.
gcc/ChangeLog:
* common/c
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvknh[ab] extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gc
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvksh extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gcc/Ch
2023-12-04 11:37 juzhe.zhong wrote:
Will split again as you mentioned. Thanks.
Feng Wang
>Hi, eswin.
>
>Thanks for contributing vector crypto support.
>
>It seems patches mess up. Could you rebase your patch to the trunk GCC cleanly
>and send it again.
>
Rebase and resend this patch due to it was not added into patchwork
before. Kito had already reviewed it. Please refer to
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327499.html
This patch add the Zvkb subset of crypto vector extension. The
corresponding test cases have aslo been modif
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