I've got a lot of complaints about my recent patch to improve equiv cost
calculation. So I am reverting the patch.
commit 8552dcd8e4448c02fe230662093756b75dd94399
Author: Vladimir N. Makarov
Date: Thu Sep 28 11:53:51 2023 -0400
Revert "[RA]: Improve cost calculation of pseudos with equiva
On 10/3/23 10:07, Surya Kumari Jangala wrote:
ira: Scale save/restore costs of callee save registers with block frequency
In assign_hard_reg(), when computing the costs of the hard registers, the
cost of saving/restoring a callee-save hard register in prolog/epilog is
taken into consideration.
On 10/18/23 09:37, Richard Sandiford wrote:
Vlad, is it OK if I backport the patch below to fix
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111528 ? Jakub has
given a conditional OK on irc.
Ok. It should be safe. I don't expect any issues because of this.
On 07/23/2018 05:14 AM, Ilya Leoshkevich wrote:
FIRST_PSEUDO_REGISTER is not a hard regno, so comparisons should use
"<" instead of "<=", and ">=" instread of ">".
Thank you for finding these typos. LRA parts of the patch are ok for me.
This is the second attempt to improve RA cost calculation for pseudos
with equivalences. The patch explanation is in the log message.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le. The patch was also benchmarked on x86-64 spec2017.
specfp2017 performance
On 10/27/23 09:56, Christophe Lyon wrote:
Hi Vladimir,
On Thu, 26 Oct 2023 at 16:00, Vladimir Makarov wrote:
This is the second attempt to improve RA cost calculation for pseudos
with equivalences. The patch explanation is in the log message.
The patch was successfully bootstrapped and
The following patch fixes one aarch64 GCC test failure resulted from my
previous patch dealing with reg equivalences.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
ppc64le.
commit 9b03e1d20c00dca215b787a5e959db473325b660
Author: Vladimir N. Makarov
Date: Fri Oct 27
The following patch fixes i686 bootstrap failure because of my recent
patch:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112107
commit 7361b49d7fa3624cb3f1f825a22607d9d31986e5
Author: Vladimir N. Makarov
Date: Fri Oct 27 14:50:40 2023 -0400
[RA]: Fixing i686 bootstrap failure because o
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111971
Successfully bootstrapped and tested on x86-64, aarch64, pp64le.
commit df111406b4ea1fe2890e94d51655e571cf260d29
Author: Vladimir N. Makarov
Date: Tue Oct 31 10:54:43 2023 -0400
[RA]: Fixing LRA cycling for mu
On 10/31/23 18:51, Edwin Lu wrote:
genattr.cc currently generates insn-attr.h with the following structure:
#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool insn_has_dfa_reservation_p (rtx_insn *);
however ge
On 2019-11-02 1:28 p.m., Kwok Cheung Yeung wrote:
The AMD GCN architecture uses 64-bit pointers, but the scalar
registers are 32-bit wide, so pointers must reside in a pair of
registers.
The two hard registers holding the frame pointer are currently fixed,
but if they are changed to unfixed
On 2019-11-07 12:28 p.m., Kwok Cheung Yeung wrote:
Hello
On AMD GCN, I encountered the following situation in the following
testcases using the compilation flags '-O2 -ftracer -fsplit-paths':
libgomp.oacc-fortran/reduction-1.f90
libgomp.oacc-fortran/reduction-2.f90
libgomp.oacc-fortran/redu
(working copy)
@@ -1,3 +1,10 @@
+2020-01-10 Vladimir Makarov
+
+ PR inline-asm/93207
+ * lra-constraints.c (match_reload): Permit input operands have the
+ same mode as output while other input operands have a different
+ mode.
+
2020-01-10 Wilco Dijkstra
PR tree-optimization/90838
Index: lra
Sorry, I found that the test will not work on x86 for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93027
So I committed additionally the following patch
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=280135
Also I did a typo in PR # in ChangeLogs and the test name so I fixed
this too.
On 1/21/20 12:20 PM, Joel Hutton wrote:
Hi all,
A previous change to simplify LRA introduced in 11b809 (From-SVN:
r279550) disabled hard register splitting for -O0. This causes a problem
on aarch64 in cases where parameters are passed in multiple registers
(in the bug report an OI passed in 2 V4
On 1/28/20 4:30 AM, Joel Hutton wrote:
On 28/01/2020 09:07, Eric Botcazou wrote:
Ping! Eric, do you have any objections to reverting?
See my comment posted in the audit trail of the TN on 01/20...
Probably missing live range splitting or somesuch, as envisioned by
Vladimir in its approval messa
-> master, origin/master, origin/HEAD)
Author: Vladimir N. Makarov
Date: Tue Jan 28 15:43:44 2020 -0500
Fix for PR93272 - LRA: EH reg allocated to hold local variable
2020-01-28 Vladimir Makarov
PR rtl-optimization/93272
* ira-live
inline asm
2020-01-31 Vladimir Makarov
PR rtl-optimization/91333
* ira-color.c (bucket_allocno_compare_func): Move conflict hard
reg preferences comparison up.
2020-01-31 Vladimir Makarov
PR rtl
SPEC2000.
commit 897a73086b2d63a5a6ae79f4276422272eca534d (HEAD -> master, origin/master, origin/HEAD)
Author: Vladimir N. Makarov
Date: Sun Feb 2 11:23:25 2020 -0500
One more fix for PR 91333 - suboptimal register allocation for inline asm
2020-02-02 Vladimir Maka
gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2020-02-06
+ Vladimir Makarov
+
+ PR rtl-optimization/93561
+ * lra-assigns.c (spill_for): Check that tested hard regno is not out of
+ hard register range.
+
2020-02-06 Richard Sandiford
* config/aarch64/aarch64.md (aarch64_movk): Add a t
On 2/11/20 3:01 AM, Kewen.Lin wrote:
Hi,
As PR91052's comments show, commit r272731 exposed one issue in function
combine_and_move_insns. Function combine_and_move_insns perform the
below unexpected transformation.
** Before: **
67: NOTE_INSN_BASIC_BLOCK 8
...
59: {r184:SF=[sfp:SI-0x1
On 2/11/20 9:54 AM, Hans-Peter Nilsson wrote:
I was using ira-conflicts.c:print_hard_reg_set with a local
patch to gdbinit.in in a debug-session, and noticed the
erroneous output. I see there's an almost identical function in
ira-color.c and on top of that, there's another function by the
same n
)
@@ -1,3 +1,10 @@
+2019-12-06 Andreas Krebbel
+ Vladimir Makarov
+
+ PR rtl-optimization/92176
+ * lra.c (simplify_subreg_regno): Don't permit unconditional
+ changing mode for LRA too.
+
2019-12-06 Richard Sandiford
* target.h (TCTX_ALLOCATION, TCTX_DEALLOCATION, TCTX_EXCEP
(working copy)
@@ -1,3 +1,18 @@
+2019-12-10 Vladimir Makarov
+
+ PR rtl-optimization/92796
+ * lra-int.h (lra_risky_transformations_p): Rename to
+ check_and_force_assignment_correctness_p.
+ * lra-assigns.c: Ditto.
+ (lra_assign): Reset check_and_force_assignment_correctness_p.
+ * lra
On 2019-12-17 1:02 p.m., Eric Botcazou wrote:
Hi,
LRA is getting measurably slower since GCC 8, at least on x86, and things are
worsening since GCC 9. While this might be legitimate when optimization is
enabled, it's a pure waste of cycles at -O0 so the attached patch switches LRA
over to usi
On 12/19/19 6:29 AM, Eric Botcazou wrote:
Simple LRA algorithms switch off hard register splitting, so there might
a slightly bigger chance for occurring "can find reload register" error
(e.g. when -O0 -fschedule-insns is used). But this error is still not
solved in general case and in my experie
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113790
The patch was successfully bootstrapped and tested on x86-64,ppc64le,
and aarch64.
commit cebbaa2a84586a7345837f74a53b7a0263bf29ee
Author: Vladimir N. Makarov
Date: Fri Mar 8 14:48:33 2024 -0500
[PR113790][L
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99829
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
and aarch64.
commit 9c91f8a88b2db50c8faf70786d3cef27b39ac9fc
Author: Vladimir N. Makarov
Date: Tue Mar 19 16:57:11 2024 -0400
[PR99829][L
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114415
The patch was successfully tested and bootstrapped on x86_64, ppc64le,
aarch64.
commit fe305ca39930afc301cdd1f1143d540d1bfa2a48
Author: Vladimir N. Makarov
Date: Thu Apr 4 16:04:04 2024 -0400
[PR114415][sche
On 2/5/24 11:10, Jeff Law wrote:
On 2/5/24 00:01, Lehua Ding wrote:
For SPEC INT 2017, when using upstream GCC (whitout these patches),
I get a
coredump when training the peak case, so no data yet. The cause of
the core
dump still needs to be investigated.
Typo, SPEC INT 2017 -> SPEC FP
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le
commit 902a5931a1fbb04c65b48ca8b0f3827f6ff3b43e
Author: Vladimir N. Makarov
Date: Thu Jan 11 08:46:26 2024 -0500
[PR112918][LRA]:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113354
The patch was tested on building MIPS target.
The patch was successfully tested and bootstrapped on x86-64, ppc64le,
aarch64.
commit 5f662bce28618ea5417f68a17d5c2d34b052ecb2
Author: Vladimir N. Makarov
Date: Mon
On 1/15/24 07:56, Maxim Kuvyrkov wrote:
Hi Vladimir,
Hi Jeff,
Richard and Alexander have reviewed this patch and [I assume] have no
further comments. OK to merge?
I trust Richard and Alexander therefore I did not do additional review
of the patches and have no any comment. Richard's or
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113526
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
and aarch64.
commit 5c617df410602d0e51d61c84d1ae7e9b3f51efa4
Author: Vladimir N. Makarov
Date: Thu Jan 25 14:41:17 2024 -0500
[PR113526]
On 12/13/23 16:00, Alex Coplan wrote:
Hi,
In PR112906 we ICE because we try to use force_reg to reload an
auto-increment address, but force_reg can't do this.
With the aim of fixing the PR by supporting reloading arbitrary
addresses in pre-RA splitters, this patch generalizes
lra-constraints.
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64.
The patch affects a sensitive part of LRA. So I will monitor that the
commit does not create serious failures on other targets. If
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112445
The patch was successfully bootstrapped and tested on x86-64, aarch64,
ppc64le.
commit 1390bf52c17a71834a1766c0222e4f8a74efb162
Author: Vladimir N. Makarov
Date: Fri Dec 1 11:46:37 2023 -0500
[PR112445][LRA]:
On 12/3/23 05:13, Richard Sandiford wrote:
[Gah. In my head I'd sent this a few weeks ago, but it turns out
that I hadn't even got to the stage of writing the changlog...]
LRA keeps track of the biggest mode for both hard registers and
pseudos. The updates assume that the modes are ordered
On 12/7/23 03:39, Jakub Jelinek wrote:
On Thu, Dec 07, 2023 at 09:36:22AM +0100, Jakub Jelinek wrote:
So, one way to fix the LRA issue would be just to use
lra_insn_recog_data_len = index * 3U / 2;
if (lra_insn_recog_data_len <= index)
lra_insn_recog_data_len = index + 1;
basically
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112875
The patch was successfully tested and bootstrapped on x86-64 and ppc64le.
commit 48cb51827c9eb991b92014a3f59d31eb237ce03f
Author: Vladimir N. Makarov
Date: Fri Dec 8 15:37:42 2023 -0500
[PR112875][LRA]: Fix an
This is one more patch for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110215
The patch was successfully tested and bootstrapped on x86-64, aarch64,
ppc64le.
commit df14f1c0582cd6742a37abf3a97f4c4bf0caf864
Author: Vladimir N. Makarov
Date: Thu Nov 9 08:51:15 2023 -0500
[IRA]: Fixing
On 11/7/23 22:47, Lehua Ding wrote:
Lehua Ding (7):
ira: Refactor the handling of register conflicts to make it more
general
ira: Add live_subreg problem and apply to ira pass
ira: Support subreg live range track
ira: Support subreg copy
ira: Add all nregs >= 2 pseudos to t
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337
The patch was successfully bootstrapped an tested on x86-64, ppc64le,
and aarch64.
commit b3d1d30eeed67c78e223c146a464d2fdd1dde894
Author: Vladimir N. Makarov
Date: Fri Nov 10 11:14:46 2023 -0500
[IRA]: Check
On 11/12/23 07:01, Lehua Ding wrote:
Thanks for the specint performance data. I'll do my best to get the
compile time and memory issues fixed. I'm very curious to know if the
way used to solve the subreg coalesce problem makes sense to you?
If it works, it is ok for me. There is always a r
On 11/12/23 07:08, Lehua Ding wrote:
V3 Changes:
1. fix three ICE.
2. rebase
Hi,
These patchs try to support subreg coalesce feature in
register allocation passes (ira and lra).
I've started review of v3 patches and here is my initial general
criticism of your patches:
* Absence o
On 11/12/23 07:08, Lehua Ding wrote:
This patch adds a live_subreg problem to extend the original live_reg to
track the liveness of subreg. We will only try to trace speudo registers
who's mode size is a multiple of nature size and eventually a small portion
of the inside will appear to use sub
On 11/12/23 09:52, Richard Sandiford wrote:
SME has various instructions that require aligned register tuples.
However, the associated tuple modes are already widely used and do
not need to be aligned in other contexts. It therefore isn't
appropriate to force alignment in TARGET_HARD_REGNO_MOD
On 11/14/23 04:03, Richard Biener wrote:
I suggest you farm bugzilla for the compile-time-hog / memory-hog testcases.
I do have a set of "large" testcases. Scanning results points at
PRs 36262, 37448, 39326, 69609 all having RA in the 20% area at
-O0 -g.
It's also a good idea to take say cc1
On 11/14/23 03:38, Lehua Ding wrote:
This is perfectly fine, the code inside the live_subreg problem has a
branch that goes through similar logic to live_reg if it finds no
subreg inside the program. Then when the optimization level is less
than 2, it doesn't track the subreg. By the way,
On 11/14/23 12:18, Vladimir Makarov wrote:
On 11/14/23 03:38, Lehua Ding wrote:
This is perfectly fine, the code inside the live_subreg problem has a
branch that goes through similar logic to live_reg if it finds no
subreg inside the program. Then when the optimization level is less
On 11/12/23 07:08, Lehua Ding wrote:
This patch switch the use of live_reg data to live_subreg data.
gcc/ChangeLog:
* ira-build.cc (create_bb_allocnos): Switch.
Switch to what? Although from the patch itself someone can figure it
out, you should write it in the changelog entry.
On 11/12/23 07:08, Lehua Ding wrote:
gcc/ChangeLog:
* hard-reg-set.h (struct HARD_REG_SET): New shift operator.
* ira-build.cc (ira_create_object): Adjust.
(find_object): New.
(find_object_anyway): New.
(ira_create_allocno): Adjust.
(get_range):
On 11/12/23 07:08, Lehua Ding wrote:
This patch changes the previous way of creating a copy between allocnos to
objects.
gcc/ChangeLog:
* ira-build.cc (find_allocno_copy): Removed.
(find_object): New.
(ira_create_copy): Adjust.
(add_allocno_copy_to_list): Adju
On 11/12/23 07:08, Lehua Ding wrote:
This patch relax the subreg track capability to all subreg registers.
The patch is ok for me when general issues I mentioned in my first email
and the issue given below are fixed.
gcc/ChangeLog:
* ira-build.cc (get_reg_unit_size): New.
(ha
On 11/16/23 21:06, Lehua Ding wrote:
Hi Vladimir,
Thank you so much for your review. Based on your comments, I feel like
there are a lot of issues, especially the long compile time issue. So
I'm going to reorganize and refactor the patches so that as many of
them as possible can be reviewed
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112610
The patch was successfully tested and bootstrapped on x86-64.
commit 95f61de95bbcc2e4fb7020e27698140abea23788
Author: Vladimir N. Makarov
Date: Wed Nov 22 09:01:02 2023 -0500
[IRA]: Fix using undefined dump fi
On 11/22/23 06:14, Maxim Kuvyrkov wrote:
We currently have 3 implementations of print_hard_reg_set()
(all with the same name!) in ira-color.cc, ira-conflicts.cc, and
sel-sched-dump.cc. This patch generalizes implementation in
ira-color.cc, and uses it in all other places. The declaration
is a
On 9/22/23 06:56, Hongyu Wang wrote:
From: Kong Lingling
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add new macros with insn parameters to base_reg_class
for lra/reload usage.
gcc/ChangeLog:
* addresses.h (base_reg_class): Add insn argu
On 9/22/23 06:56, Hongyu Wang wrote:
Like base_reg_class, INDEX_REG_CLASS also does not support backend insn.
Add index_reg_class with insn argument for lra/reload usage.
gcc/ChangeLog:
* addresses.h (index_reg_class): New wrapper function like
base_reg_class.
* doc/tm
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111497
The patch was successfully tested and bootstrapped on x86-64 and aarch64.
commit 3c23defed384cf17518ad6c817d94463a445d21b
Author: Vladimir N. Makarov
Date: Mon Sep 25 16:19:50 2023 -0400
[PR111497][LRA]: Copy
I've pushed the following patch. The explanation is in commit message.
The patch was successfully bootstrapped on x86-64.
commit 0c8ecbcd3cf7d7187d2017ad02b663a57123b417
Author: Vladimir N. Makarov
Date: Thu Sep 28 09:41:18 2023 -0400
[RA]: Add flag for checking IRA in progress
R
On 6/14/24 07:10, user202...@protonmail.com wrote:
This patch was inspired from PR 110137. It reduces the amount of stack spilling
by ensuring that more values are constant across a pure function call.
It does not add any new flag; rather, it makes the optimizer generate more
optimal code.
On 5/30/24 03:59, Richard Sandiford wrote:
Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install?
Yes. Thank you, Richard.
gcc/
PR rtl-optimization/115281
* ira-conflicts.cc (go_through_subreg): Use the natural size of
the inner mode rather than the outer m
On 8/9/24 08:58, Surya Kumari Jangala wrote:
I am looking into this failure.
Sorry for delay with this email. I was on vacation.
I believe your should reverse the original patch and all the patches you
submitted to fix the issues with the original patch.
This is a standard procedure in s
On 8/9/24 05:49, Kewen.Lin wrote:
Hi,
Commit r15-2084 exposes one ICE in LRA. Firstly, before
r15-2084 KFmode has 126 bit precision while V1TImode has 128
bit precision, so the subreg (subreg:V1TI (reg:KF 131) 0) is
paradoxical_subreg_p, which stops some passes from doing
some optimization.
On 8/9/24 17:00, Peter Bergner wrote:
On 8/9/24 12:02 PM, Vladimir Makarov wrote:
I believe your should reverse the original patch and all the patches you
submitted to fix the issues with the original patch.
I agree this commit should be reverted and Kyrill has pushed that already,
so
On 8/11/24 21:50, Kewen.Lin wrote:
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 92b343fa99a..f355c6c6168 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -4742,7 +4742,9 @@ curr_insn_transform (bool check_only_p)
}
*loc = new_reg
On 8/22/24 04:44, Richard Sandiford wrote:
The sequence of events in this PR is that:
- the function has many addresses in which only a single hard base
register is acceptable. Let's call the hard register H.
- IRA allocates that register to one of the pseudo base registers.
Let's call
On 4/29/24 08:59, Wilco Dijkstra wrote:
According to documentation, '^' should only have an effect during reload.
However ira-costs.cc treats it in the same way as '?' during early costing.
As a result using '^' can accidentally disable valid alternatives and cause
significant regressions (see
I am resending this message as the previous one had one wrong response
email address "gcc-pat...@gcc.gnu.org"
Forwarded Message
Subject: Re: [PATCH V2 0/4] Add DF_LIVE_SUBREG data and apply to IRA
and LRA
Date: Wed, 1 May 2024 08:35:27 -0400
From: Vladimir M
On 2/3/24 05:50, Lehua Ding wrote:
This patch simple replace df_get_live_in to df_get_subreg_live_in
and replace df_get_live_out to df_get_subreg_live_out.
gcc/ChangeLog:
* ira-build.cc (create_bb_allocnos): Switch to DF_LIVE_SUBREG df data.
(create_loop_allocnos): Ditto.
On 2/3/24 05:50, Lehua Ding wrote:
This patch apply the DF_LIVE_SUBREG to LRA pass. More changes were made
to the LRA than the IRA since the LRA will modify the DF data directly.
The main big changes are centered on the lra-lives.cc file.
gcc/ChangeLog:
* lra-coalesce.cc (update_live_i
On 5/7/24 23:01, Lehua Ding wrote:
Hi Vladimir,
I'll send V3 patchs based on these comments. Note that these four
patches only support subreg liveness tracking and apply to IRA and LRA
pass. Therefore, no performance changes are expected before we support
subreg coalesce. There will be new
The following patch is a fix for PR114810 from LRA side.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le.
commit dc859c1fcb6f3ad95022fb078c040907ef361e4c
Author: Vladimir N. Makarov
Date: Wed May 8 10:39:04
On 5/8/24 23:25, Li, Pan2 wrote:
Hi Vladimir,
Looks this patch results in some ICE in the rvv.exp of RISC-V backend,
feel free to ping me if more information is needed for reproducing.
= Summary of gcc testsuite =
| # of unexpected case / # of unique unexpected case
|gcc |
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114942
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
aarch64.
commit 9585317f0715699197b1313bbf939c6ea3c1ace6
Author: Vladimir N. Makarov
Date: Fri May 10 09:15:50 2024 -0400
[PR114942][LRA]
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013
Successfully tested and bootstrapped on x86-64.
commit 44430ef3d8ba75692efff5f6969d5610134566d3
Author: Vladimir N. Makarov
Date: Mon May 13 10:12:11 2024 -0400
[PR115013][LRA]: Modify register starvation recog
On 08/27/2013 02:00 PM, Peter Bergner wrote:
> I'd like to ping the following patch which fixes a wrong code bug
> on powerpc64-linux due to a lost dependency within the scheduler:
>
> Fix PR58139 by correctly initializing reg_raw_mode[]
>
> http://gcc.gnu.org/ml/gcc-patches/2013-08/msg0091
On 13-09-07 9:01 AM, Richard Sandiford wrote:
Jakub Jelinek writes:
On Sat, Sep 07, 2013 at 12:37:14PM +0100, Richard Sandiford wrote:
Steven Bosscher writes:
Can you please add a test case?
What kind of test would you suggest? Do we have a harness for testing
that -O2 and -O2 -g .text out
On 13-08-30 9:09 AM, Yvan Roux wrote:
Hi,
here is a request for comments on the 2 attached patches which enable
the build of GCC on ARM with LRA. The patches introduce a new
undocumented option -mlra to use LRA instead of reload, as what was
done on previous LRA support, which is here to ease t
On 13-09-08 2:04 PM, Richard Sandiford wrote:
Yvan Roux writes:
@@ -5786,7 +5796,11 @@ get_index_scale (const struct address_info *info)
&& info->index_term == &XEXP (index, 0))
return INTVAL (XEXP (index, 1));
- if (GET_CODE (index) == ASHIFT
+ if ((GET_CODE (index) == ASHI
On 13-08-22 9:37 AM, Andrey Turetskiy wrote:
Hi Vladimir,
I'm trying to apply KNF and KNC changes for GCC 4.9 (they have been
applied for 4.7 before), but I have some problems with LRA.
I've tried to build cross compiler for KNC. During the compiling of
libgcc/libgcc2.c the compiler becomes lock
itted as rev. 202468.
2013-09-10 Vladimir Makarov
* lra.c (lra): Clear lra_optional_reload_pseudos before every
constraint pass.
* lra-constraints.c (curr_insn_transform): Switch on optional
reloads. Check destination too to check move
and makes LRA more portable.
The patch was successfully bootstrapped and tested on x86/x86-64 and s390.
Committed as rev. 202536.
2013-09-12 Vladimir Makarov
PR middle-end/58335
* lra-eliminations.c (remove_reg_equal_offset_note): New.
(eliminate_regs_in_insn): Rewrite
The following patch fixes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58418
The patch also fixes a duplicated bug PR58419.
The patch was successfully tested and bootstrapped on x86/x86-64.
Committed as rev. 202630.
2013-09-16 Vladimir Makarov
PR middle-end/58418
* lra
On 13-09-16 11:39 AM, H.J. Lu wrote:
On Mon, Sep 16, 2013 at 8:12 AM, Vladimir Makarov wrote:
The following patch fixes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58418
The patch also fixes a duplicated bug PR58419.
Shouldn't we also add a testcase from PR58419?
I've checked th
The following patch fixes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58438
The patch was successfully bootstrapped and tested on x86/x86-64.
Committed as rev. 202714.
2013-09-18 Vladimir Makarov
PR rtl-optimization/58438
* lra.c (lra): Clear lra_optional_reload_pseudos in
On 09/12/2013 02:27 PM, Vladimir Makarov wrote:
> The following patch fixes
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58335
>
> It required to implement a new approach for elimination updates for
> insn frame_pointer = hard_frame_pointer + offset. The previous
>
.
Committed as rev. 202721.
2013-09-18 Vladimir Makarov
* lra-constraints.c (need_for_all_save_p): Use macro
HARD_REGNO_CALL_PART_CLOBBERED.
* lra-lives.c (check_pseudos_live_through_calls): Use the macro to
set up pseudo conflict hard regs.
Index: lra-constraints.c
On 09/24/2013 10:40 AM, Yvan Roux wrote:
> Hi,
>
> This patch removes REG_DEAD and REG_UNUSED notes in update_inc_notes,
> as it is what the function is supposed to do (see the comments) and as
> keeping these notes produce some failures, at least on ARM.
>
> Thanks,
> Yvan
>
> 2013-09-24 Yvan Rou
On 09/24/2013 03:40 PM, Mike Stump wrote:
> On Sep 24, 2013, at 12:23 PM, Steven Bosscher wrote:
>> On Tue, Sep 24, 2013 at 5:03 PM, Eric Botcazou wrote:
This patch removes REG_DEAD and REG_UNUSED notes
>>> DF framework is supposed to do it for you.
>> Unfortunately LRA uses its own DF framew
On 09/24/2013 07:57 PM, Wei Mi wrote:
> Hi,
>
> This patch is to address the problem described here:
> http://gcc.gnu.org/ml/gcc/2013-09/msg00187.html
>
> The patch changes ALLOCNO_MODE of a pseudo reg to be outermode if the
> pseudo reg is used in a paradoxical subreg, so IRA will not mistakenly
>
On 09/25/2013 12:42 PM, Wei Mi wrote:
>> performance. For example, we have code
>>
>> ... (reg:DI) ...
>> ...
>> ... (subreg:TI (reg:DI))
>> ...
>> ...(reg:DI)
>>
>> We need two hard regs only for the second place by transforming
>>
>> p = (reg:DI)
>>
>> ...(subreg:TI p)
>>
>> With this patch we re
On 09/25/2013 02:00 PM, Wei Mi wrote:
>> To define for what occurrence of the pseudo we should do the
>> transformation, we need to create allocnos and calculate reg classes to
>> know what paradoxical subreg needs more hard regs (the transformations
>> can not be done for all paradoxical subregs
On 13-09-27 4:55 AM, Dodji Seketeli wrote:
Let's CC Vladimir on this easy one.
Cheers.
All targets I know have ELIMINABLE_REGS defined. Therefore it was not
caught before.
.
The patch is ok for me. Thanks.
Jan-Benedict Glaw a écrit:
On Fri, 2013-09-20 20:51:37 +0200, Jan-Benedict Glaw
On 12-09-28 4:21 AM, Steven Bosscher wrote:
On Fri, Sep 28, 2012 at 12:56 AM, Vladimir Makarov wrote:
Any comments and proposals are appreciated. Even if GCC community
decides that it is too late to submit it to gcc4.8, the earlier reviews
are always useful.
I would like to see some
On 12-09-28 4:43 AM, Steven Bosscher wrote:
On Fri, Sep 28, 2012 at 12:57 AM, Vladimir Makarov wrote:
LRA outputs a lot debug information about insns. I found that using slim
insn/rtl presentation helps a lot for LRA debuging. The following patch
makes slim presentation printing functions
On 12-09-28 4:07 PM, Jeff Law wrote:
On 09/27/2012 04:58 PM, Vladimir Makarov wrote:
The following patch modifies some code in the rest of compiler for
correct work of LRA. The code works the same way when LRA is not
used. It is achieved by checking a new variable lra_in_progress.
2012-09
On 12-09-28 11:36 AM, Jeff Law wrote:
On 09/28/2012 09:21 AM, Vladimir Makarov wrote:
On 12-09-28 4:43 AM, Steven Bosscher wrote:
I have patches in the works to use the slim RTL dumping format more,
too, and to use the pretty-printer code so that printing strings with
escaped characters can be
On 12-09-28 3:08 PM, Jeff Law wrote:
On 09/27/2012 04:57 PM, Vladimir Makarov wrote:
LRA creates a lot of new pseudos. So the following patch implements
ahead allocation reg info information which is important for LRA
compilation speed.
2012-09-27 Vladimir Makarov
* reginfo.c
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