On 9/2/22 14:05, Vineet Gupta wrote:
Came across this deprecated symbol when looking around for
-mexplicit-relocs handling in code
Signed-off-by: Vineet Gupta
No rush but looks like this got lost in the bigger thread about
LOAD_ADDRESS_MACRO.
Thx,
-Vineet
---
gcc/config/riscv/riscv
On 10/4/22 19:24, Kito Cheng wrote:
Committed, and added ChangeLog, remember to add that next time:)
Oops sorry, I will.
Thx,
-Vineet
Hi Christoph, Kito,
On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
This series provides a cleanup of the current atomics implementation
of RISC-V:
* PR100265: Use proper fences for atomic load/store
* PR100266: Provide programmatic implementation of CAS
As both are very related, I
On 10/11/22 13:46, Christoph Müllner wrote:
On Tue, Oct 11, 2022 at 9:31 PM Palmer Dabbelt wrote:
On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
> Hi Christoph, Kito,
>
> On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
>> This se
605
|# of unsupported tests 2523
|
| === g++ Summary ===
|
|# of expected passes 172997
|# of unexpected failures 26
|# of expected failures 706
|# of unsupported tests 9566
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/predicates.md | 2
On 2/7/22 01:28, Philipp Tomsich wrote:
Vineet,
On Mon, 7 Feb 2022 at 07:06, Vineet Gupta wrote:
This is at par with other major arches such as aarch64, i386, s390 ...
No testsuite regressions: same numbers w/ w/o
Putting that check seems a good idea, but I haven't seen any cases
re
On 2/7/22 10:58, Palmer Dabbelt wrote:
On Mon, 07 Feb 2022 09:41:10 PST (-0800), Vineet Gupta wrote:
On 2/7/22 01:28, Philipp Tomsich wrote:
Vineet,
On Mon, 7 Feb 2022 at 07:06, Vineet Gupta wrote:
This is at par with other major arches such as aarch64, i386, s390 ...
No testsuite
On 2/7/22 13:24, Vineet Gupta wrote:
On 2/7/22 10:58, Palmer Dabbelt wrote:
On Mon, 07 Feb 2022 09:41:10 PST (-0800), Vineet Gupta wrote:
On 2/7/22 01:28, Philipp Tomsich wrote:
Vineet,
On Mon, 7 Feb 2022 at 07:06, Vineet Gupta
wrote:
This is at par with other major arches such as
On 10/13/22 15:39, Jeff Law via Gcc-patches wrote:
On 10/11/22 17:31, Vineet Gupta wrote:
I expect that the pressure for a proper fix upstream (instead of a
backward compatible compromise) will increase over time (once people
start building big iron based on RISC-V and start hunting
/ medlow |9 / 7 |10959 / 2764 |0 / 0 |
rv32imac/ ilp32/ medlow |9 / 7 |10959 / 2764 |0 / 0 |
rv64imac/ lp64/ medlow | 13 /11 |11016 / 2776 |0 / 0 |
Thx,
-Vineet
Vineet Gupta (2):
RISC-V: remove deprecate pic code model macro
RISC-V
Came across this deprecated symbol when looking around for
-mexplicit-relocs handling in code
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-c.cc | 3 ---
1 file changed, 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index eb7ef09297e9
CM_PIC is no longer doing anything directly. Removing it might
potentially affect USE_LOAD_ADDRESS_MACRO() but seems unlikely.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-c.cc | 4
gcc/config/riscv/riscv-opts.h | 3 +--
gcc/config/riscv/riscv.cc | 2 +-
3 files changed
On 8/31/22 07:57, Palmer Dabbelt wrote:
On Tue, 30 Aug 2022 10:48:29 PDT (-0700), Vineet Gupta wrote:
Came across this deprecated symbol when looking around for
-mexplicit-relocs handling in code
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-c.cc | 3 ---
1 file changed, 3 deletions
On 8/31/22 07:57, Palmer Dabbelt wrote:
if (flag_pic)
- riscv_cmodel = CM_PIC;
+ riscv_cmodel = CM_MEDANY;
/* We get better code with explicit relocs for CM_MEDLOW, but
worse code for the others (for now). Pick the best default. */
I'm fine either way on this one: having
Came across this deprecated symbol when looking around for
-mexplicit-relocs handling in code
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-c.cc | 3 ---
gcc/testsuite/gcc.target/riscv/predef-1.c | 3 ---
gcc/testsuite/gcc.target/riscv/predef-2.c | 3 ---
gcc/testsuite
On 8/31/22 13:39, Vineet Gupta wrote:
On 8/31/22 07:57, Palmer Dabbelt wrote:
if (flag_pic)
- riscv_cmodel = CM_PIC;
+ riscv_cmodel = CM_MEDANY;
/* We get better code with explicit relocs for CM_MEDLOW, but
worse code for the others (for now). Pick the best default
Came across this deprecated symbol when looking around for
-mexplicit-relocs handling in code
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-c.cc | 5 -
gcc/testsuite/gcc.target/riscv/predef-1.c | 3 ---
gcc/testsuite/gcc.target/riscv/predef-2.c | 3 ---
gcc/testsuite
The current macro has several && and || making it really hard to understand
the first time.
Signed-off-by: Vineet Gupta
---
Since we are on this topic, perhaps get this simplification too.
But I'm not sure if the current checking of local symbol can be simplified
a bit. Isn
Ditto.
(thead_c906_tune_info): Ditto.
(optimize_size_tune_info): Ditto.
(riscv_register_move_cost): Use fmv_cost for int<->fp moves.
gcc/testsuite/Changelog:
* gcc.target/riscv/pr105666.c: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc
Ping ! With commit restrictions relaxed now, can this be added to trunk
now ?
Thx,
-Vineet
On 2/6/22 22:06, Vineet Gupta wrote:
This is at par with other major arches such as aarch64, i386, s390 ...
No testsuite regressions: same numbers w/ w/o
| === gcc Summary ===
|
|# of
On 5/24/22 00:59, Kito Cheng wrote:
Committed, thanks!
Thx for the quick action Kito,
Can this be backported to gcc 12 as well ?
Thx,
-Vineet
On Tue, May 24, 2022 at 3:40 AM Philipp Tomsich
wrote:
Good catch!
On Mon, 23 May 2022 at 20:12, Vineet Gupta wrote:
Under extreme register
On 7/22/21 15:41, Christoph Muellner via Gcc-patches wrote:
This patch enables the overlap-by-pieces feature of the by-pieces
infrastructure for inlining builtins in case the target has set
riscv_slow_unaligned_access_p to false.
An example to demonstrate the effect for targets with fast unal
On 5/24/22 18:32, Palmer Dabbelt wrote:
Ping, IMO this needs to be (re)considered for trunk.
This goes really nicely with riscv_slow_unaligned_access_p==false, to
elide the unrolled tail copies for trailer word/sword/byte accesses.
@Kito, @Palmer ? Just from codegen pov this seems to be a no
Currently for hard float we need to check for
__ARC_FPU_SP__ || __ARC_FPU_DP__ and for soft float inverse of that.
So define single convenience macros for either cases
gcc/
-xx-xx Vineet Gupta
* config/arc/arc-c.c (arc_cpu_cpp_builtins): Add
__arc_hard_float__
On 12/9/19 1:52 AM, Claudiu Zissulescu wrote:
> Although the FDCMP (the double precision floating point compare instruction)
> is added to the compiler, it is not properly used via cstoredi pattern. Fix
> it.
>
> OK to apply?
> Claudidu
>
> -xx-xx Claudiu Zissulescu
>
> * config/arc/
On 12/9/19 11:02 AM, Vineet Gupta wrote:
> ARC gcc generates FDCMP instructions which raises Invalid operation for
> signaling NaN only. This causes glibc iseqsig() primitives to fail (in
> the current ongoing glibc port to ARC)
>
> So split up the hard float compares into two cat
On 1/14/20 3:49 PM, Vineet Gupta wrote:
> On 12/9/19 11:02 AM, Vineet Gupta wrote:
>> ARC gcc generates FDCMP instructions which raises Invalid operation for
>> signaling NaN only. This causes glibc iseqsig() primitives to fail (in
>> the current ongoing glibc port to ARC)
(vs. FDCMP) which raises exception
for either NaNs.
With this fix testsuite/gcc.dg/torture/pr52451.c passes for ARC.
Also passes 6 additional tests in glibc testsuite (test*iseqsig) and no
regressions
gcc/
-xx-xx Vineet Gupta
* config/arc/arc-modes.def (CC_FPUE): New Mode CC_FPUE
-Original Message-
>> From: Vineet Gupta [mailto:vgu...@synopsys.com]
>> Sent: Monday, December 09, 2019 8:02 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Claudiu Zissulescu ;
>> andrew.burg...@embecosm.com; linux-snps-...@lists.infradead.org;
>> Vineet Gupta
On 7/22/21 6:29 AM, Kito Cheng via Gcc-patches wrote:
Could you add a testcase? Otherwise LGTM.
Option: -O2 -mtune=thead-c906 -march=rv64gc -mabi=lp64
void foo(char *dst){
__builtin_memset(dst, 0, 15);
}
On Thu, Jul 22, 2021 at 8:53 PM Christoph Muellner via Gcc-patches
wrote:
This patch
On 11/2/21 1:09 PM, Christoph Müllner wrote:
Without overlap_op_by_pieces we get:
8e: 00053023sd zero,0(a0)
92: 00052423sw zero,8(a0)
96: 00051623sh zero,12(a0)
9a: 00050723sb zero,14(a0
On 11/2/21 2:18 PM, Christoph Müllner wrote:
On Tue, Nov 2, 2021 at 9:15 PM Vineet Gupta wrote:
On 11/2/21 1:09 PM, Christoph Müllner wrote:
Without overlap_op_by_pieces we get:
8e: 00053023sd zero,0(a0)
92: 00052423sw zero,8(a0
Hi Kito,
On 9/23/21 12:57 AM, Kito Cheng wrote:
Bit manipulation extension[1] is finishing the public review and waiting for
the rest of the ratification process, I believe that will become a ratified
extension soon, so I think it's time to submit to upstream for review now :)
As the title incl
Hi Pan,
On 2/28/24 17:23, Li, Pan2 wrote:
>
> Personally I prefer to remove --param=riscv-autovec-preference=none
> and only allow
>
> mrvv-vector-bits, to avoid tricky(maybe) sematic of none preference.
> However, let’s
>
> wait for a while in case there are some comments from others.
>
We are v
On 3/5/24 23:27, pan2...@intel.com wrote:
> From: Pan Li
>
> Update in v2:
> * Cleanup some unused code.
> * Fix some typo of commit log.
>
> Original log:
>
> This patch would like to introduce one new gcc attribute for RVV.
> This attribute is used to define fixed-length variants of one
> exi
/riscv_legitimize_address) but that is tripping up
and currently being debugged.
Thx,
-Vineet
Vineet Gupta (3):
RISC-V: avoid LUI based const materialization ... [part of PR/106265]
RISC-V: avoid LUI based const mat: keep stack offsets aligned
RISC-V: avoid LUI based const mat in prologue/epilogue
config/riscv/riscv.cc (riscv_reg_frame_related): New helper to
conditionalize the existing and new spitters.
* config/riscv/riscv-protos.h: Add new prototype.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/constraints.md | 6 ++
gcc/config/riscv/predicates.md | 8 ++-
gcc/
4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/risc
* gcc.target/riscv/sum-of-two-s12-const-1.c: New test: checks for
new patterns output.
* gcc.target/riscv/sum-of-two-s12-const-2.c: New test: should not
ICE.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/constraints.md | 6 +++
gcc/config/ri
On 3/16/24 13:28, Jeff Law wrote:
>> Implementation Details (for posterity)
>> --
>> - basic idea is to have a splitter selected via a new predicate for
>> constant
>> being possible sum of two S12 and provide the transform.
>> This is however a 2 -
On 3/16/24 13:21, Jeff Law wrote:
> | 59944:add s0,sp,2047 <
> | 59948:mv a2,a0
> | 5994c:mv a3,a1
> | 59950:mv a0,sp
> | 59954:li a4,1
> | 59958:lui a1,0x1
> | 5995c:add s0,s0,1 <---
> | 59960:jal 59a3c
On 3/19/24 06:10, Jeff Law wrote:
> On 3/19/24 12:48 AM, Andrew Waterman wrote:
>> On Mon, Mar 18, 2024 at 5:28 PM Vineet Gupta wrote:
>>> On 3/16/24 13:21, Jeff Law wrote:
>>>> | 59944:add s0,sp,2047 <
>>>> | 59948:m
On 3/18/24 21:41, Jeff Law wrote:
>> The first patch is the main change which improves SPEC cactu by 10%.
> Just to confirm. Yup, 10% reduction in icounts and about a 3.5%
> improvement in cycles on our target. Which is great!
Nice.
> This also makes me wonder if cactu is the benchmark that
On 3/18/24 21:41, Jeff Law wrote:
>
> On 3/16/24 11:35 AM, Vineet Gupta wrote:
>> Hi,
>>
>> This set of patches (for gcc-15) help improve stack/array accesses
>> by improving constant materialization. Details are in respective
>> patches.
>>
>> T
On 3/21/24 07:45, Jeff Law wrote:
The first patch is the main change which improves SPEC cactu by 10%.
>>> Just to confirm. Yup, 10% reduction in icounts and about a 3.5%
>>> improvement in cycles on our target. Which is great!
>>>
>>> This also makes me wonder if cactu is the benchmark t
On 3/21/24 12:56, Jeff Law wrote:
>
> On 3/21/24 11:19 AM, Vineet Gupta wrote:
>
>>> So if we go back to Robin's observation that scheduling dramatically
>>> increases the instruction count, perhaps we try a run with
>>> -fno-schedule-insns -fno-sc
On 3/22/24 05:29, Jeff Law wrote:
>> Another option is to enable -fsched-pressure which should help with
>> this issue.
> In theory we're already using that by default -- it's part of what makes
> me so curious to understand what's going on.
We are actually using it in practice :-)
Its the def
/rvv/vtype-call-clobbered.c: New Test.
Signed-off-by: Vineet Gupta
---
.../riscv/rvv/vtype-call-clobbered.c | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c
diff --git a/gcc/testsuite/gcc.target
/ChangeLog:
* gcc.target/riscv/rvv/vtype-call-clobbered.c: New Test.
Signed-off-by: Vineet Gupta
---
.../riscv/rvv/vtype-call-clobbered.c | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c
diff --git a
+CC Greg who might also have some bits in flight here.
On 2/23/24 01:23, Li, Pan2 wrote:
>
> > I would prefer to only keep zvl and scalable or zvl only, since I
>
> > don't see too much value in specifying a value which different from
>
> > zvl*b, that's a legacy option used before zvl*b option wa
pts.h: New enum vsetvl_strategy_enum.
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
(pass_vsetvl::execute): Use vsetvl_strategy.
Signed-off-by: Vineet Gupta
---
Changes since v1:
- Dropped OPTIM_NO_DEL
---
gcc/config/riscv/riscv-o
: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 78a2f7b38faf..41d4b80648f6 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc
: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 78a2f7b38faf..41d4b80648f6 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc
pts.h: New enum vsetvl_strategy_enum.
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
(pass_vsetvl::execute): Use vsetvl_strategy.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-opts.h| 9 +
gcc/config/riscv/
pts.h: New enum vsetvl_strategy_enum.
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
(pass_vsetvl::execute): Use vsetvl_strategy.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-opts.h| 11 +++
gcc/config/riscv/
On 12/6/23 08:22, Palmer Dabbelt wrote:
>> Ran the test case at 122e7b4f9d0c2d54d865272463a1d812002d0a5c where the xfail
> That's the original port submission, I'm actually kind of surprised it
> still builds/works at all.
Full toolchain build would have been a stretch (matching pairing
binutil
.
* gcc.target/riscv/predef-align-4.c: New test.
* gcc.target/riscv/predef-align-5.c: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-c.cc | 11 +++
gcc/config/riscv/riscv.cc | 9 +
gcc/config/riscv/riscv.h
... otherwise user has no clue what -param to actually change
gcc/ChangeLog:
* config/riscv/riscv.opt: Add --param names
riscv-autovec-preference and riscv-autovec-lmul
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.opt | 4 ++--
1 file changed, 2 insertions(+), 2
... otherwise user has no clue what -param to actually change
gcc/ChangeLog:
* config/riscv/riscv.opt: Add --param names
riscv-autovec-preference and riscv-autovec-lmul
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.opt | 4 ++--
1 file changed, 2 insertions(+), 2
On 8/22/23 11:07, Palmer Dabbelt wrote:
We should probably put them in invoke.texi as well (and anything else
we're missing that's been added recently).
Looks like I'd pushed the patch already.
A whole bunch of them are missing, so guess that can happen seperately.
-Vineet
On 8/23/23 13:04, Jeff Law wrote:
Thanks for your patience on this. I needed a bit of time to gather my
thoughts and review some code.
No worries at all.
index 8b7256108157..1802eef908fc 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2464,14 +2464,9 @@ riscv_rtx
Hi Jivan,
On 8/24/23 08:45, Jivan Hakobyan via Gcc-patches wrote:
This patch fixes failing stack_save_restore_1/2 test cases.
After 6619b3d4c15c commit size of the frame was changed.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/stack_save_restore_1.c: Update frame size
* gcc.t
o.
Signed-off-by: Vineet Gupta
---
Changes since v1
- Simplified code under case CONST.
- Added some comments for handling of CONST_INT in 2 places.
---
gcc/config/riscv/riscv.cc | 18 +-
gcc/testsuite/gcc.target/riscv/gcse-const.c| 13 +
...
o.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 18 +-
gcc/testsuite/gcc.target/riscv/gcse-const.c| 13 +
.../riscv/rvv/vsetvl/vlmax_conflict-7.c| 1 -
.../riscv/rvv/vsetvl/vlmax_conflict-8.c| 1 -
4 files c
a4,8(sp) lda5,8(sp)
czero.nez a0,a4,a5 czero.eqz a0,a5,a0
The issue only happens at -O1 as at higher optimization levels, the
whole conditional move gets optimized away.
gcc/ChangeLog:
* config/riscv/zicond.md: Remove incorrect op2 pattern.
Fixes: 1d5bc3285e8a ("[
On 8/31/23 06:51, Jeff Law wrote:
On 8/30/23 15:57, Vineet Gupta wrote:
This was tripping up gcc.c-torture/execute/pr60003.c at -O1 since the
pattern semantics can't be expressed by zicond instructions.
This involves test code snippet:
if (a == 0)
return 0;
On 9/1/23 06:13, Jeff Law wrote:
I could very well be mistaken, but define_insn is a pattern match and
opt2 has *ne* so the expression has to be in != form and thus needs
to work with that condition. No ?
My point was that
x = (a != 0) ? x : 0
is equivalent to
x = (a == 0) ? 0 : x
You ca
On 9/1/23 10:40, Palmer Dabbelt wrote:
Just working through this in email, as there's a lot of
double-negatives and I managed to screw up my Linux PR this morning so
I may not be thinking that well...
The docs say "(if_then_else test true-value false-value)". So in this
case it's
t
: gcc.dg/torture/stackalign/setjmp-3.c -O1 -fpic execution test
gcc/ChangeLog:
* config/riscv/zicond.md: Fix op2 pattern.
Fixes: 1d5bc3285e8a ("[committed][RISC-V] Fix 20010221-1.c with zicond")
Signed-off-by: Vineet Gupta
---
changes since v1
- instead of discarding opt2 pat
ture/stackalign/setjmp-3.c -O1 execution test
FAIL: gcc.dg/torture/stackalign/setjmp-3.c -O1 -fpic execution test
gcc/ChangeLog:
* config/riscv/zicond.md: Fix op2 pattern.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/zicond.md | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Do we have call tomorrow, given some folks are traveling for RV Summit ?
Thx,
-Vineet
_if_not_subreg_prom): New.
* (riscv_extend_comparands): Call New function on operands.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ecee7eb4
d insertion.
Commit contientent to pre-commit CI Testing feedback.
PR target/112447
Co-developed-by: Vineet Gupta
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Insert
local vsetvl info before LCM suggested one.
Signed-off-by: Vineet Gupta
---
gc
e-commit-CI #676
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e919850fc6cb..e466d4f168af 100644
--- a/gcc/config/riscv/riscv.cc
+
re LCM suggested one.
Tested-by: Patrick O'Neill # pre-commit-CI #679
Co-developed-by: Vineet Gupta
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc | 70
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git
On 8/29/23 08:40, Joern Rennecke wrote:
In the patch call we talked about sign extsnsion elimination, so I dug
up this patch set that I did a while ago. It is still lacking some
documentation and testing in a more recent base version;
I only adjusted the common.opt part context for the patch to
Hi Jeff, Andrew
I've been looking into redundant sign extension and while there are
things to be improved in REE, there's something I wanted to confirm
before heading off into the weeds.
Consider the test below:
int foo(int unused, int n, unsigned y, unsigned delta){
int s = 0;
unsigned
On 9/18/23 13:10, Andrew Waterman wrote:
Vineet,
Your understanding of the ABI is correct; both int and unsigned int
arguments must already be sign-extended. The sext.w is semantically
unnecessary; the bltu could correctly reference a1 instead of a6.
Good luck eliminating it!
Thanks for the
Hi Ajit,
On 9/17/23 22:59, Ajit Agarwal wrote:
This new version of patch 6 use improve ree pass for rs6000 target using
defined ABI interfaces.
Bootstrapped and regtested on power64-linux-gnu.
Review comments incorporated.
Thanks & Regards
Ajit
Nit: This seems to belong to "what changed in
On 9/18/23 09:11, Jeff Law wrote:
On 9/18/23 09:24, Kito Cheng wrote:
I may missed that one time too, not on plane yet, but need to go bed
earlier due to my flight is in next day early morning...
I'm unavailable as well, though I don't get on a plane until Wednesday
evening.
This is one mee
On 9/18/23 19:41, Jeff Law wrote:
On 9/18/23 13:45, Vineet Gupta wrote:
For the cases which do require sign extends, but not being eliminated
due to "missing definition(s)" I'm working on adapting Ajit's REE ABI
interfaces work [2] to work for RISC-V as well.
I wonder
On 9/18/23 19:41, Jeff Law wrote:
On 9/18/23 13:45, Vineet Gupta wrote:
For the cases which do require sign extends, but not being eliminated
due to "missing definition(s)" I'm working on adapting Ajit's REE ABI
interfaces work [2] to work for RISC-V as well.
I wonder
+CC Patrick who's been chasing similar issues.
On 9/23/23 00:18, Maciej W. Rozycki wrote:
In non-multilib installations system headers may not be available for
compilation options using a non-default model, causing build errors such
as:
In file included from .../include/features.h:527,
Hi Jeff,
On 9/19/23 07:59, Jeff Law wrote:
On 9/18/23 21:37, Vineet Gupta wrote:
On 9/18/23 19:41, Jeff Law wrote:
On 9/18/23 13:45, Vineet Gupta wrote:
For the cases which do require sign extends, but not being
eliminated due to "missing definition(s)" I'm working on a
On 9/27/23 13:14, Jeff Law wrote:
It would help to describe how these patterns were under specified so
that folks don't continue to make the same mistake as new tests get
added.
dg-final scan-assembler, scan-assembler-not, and scan-assembler-times
use a tcl regular expression (often referre
:
* config/riscv/riscv.md: Add UNSPEC_FCLASS, UNSPEC_ISFINITE,
USPEC_ISNORMAL.
define_insn for fclass.
define_expand for isfinite and isnormal.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fclass.c: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.md
On 6/28/24 17:53, Vineet Gupta wrote:
> Currently isfinite and isnormal use float compare instructions with fp
> flags save/restored around them. Our perf team complained this could be
> costly in uarch. RV Base ISA already has FCLASS.{d,s,h} instruction to
> do FP compares w/o d
On 6/29/24 06:44, Jeff Law wrote:
>> +;; fclass instruction output bitmap
>> +;; 0 negative infinity
>> +;; 1 negative normal number.
>> +;; 2 negative subnormal number.
>> +;; 3 -0
>> +;; 4 +0
>> +;; 5 positive subnormal number.
>> +;; 6 positive normal number.
>> +;; 7 positive in
On 6/30/24 00:41, Xi Ruoyao wrote:
> On Fri, 2024-06-28 at 17:53 -0700, Vineet Gupta wrote:
>> + UNSPEC_ISFINITE
>> + UNSPEC_ISNORMAL
> You don't really need them. The RTL pattern of define_expand has no use
> when you expand it via C code and DONE.
On 6/30/24 06:59, Jeff Law wrote:
>> Any ideas on how I can keep this and then adjust rest of patterns.
> Yea. Drop the "SImode" references from the RTL template of the
> expander. Then you'll need to verify the modes in the C fragment that
> generates code. You'd want to test the mode of
test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.md | 50 +
gcc/testsuite/gcc.target/riscv/fclass.c | 18 +
2 files changed, 68 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/fclass.c
diff --git a/gcc/config/riscv/riscv.md
On 7/8/24 14:03, Jeff Law wrote:
>
> On 6/30/24 6:47 PM, Vineet Gupta wrote:
>> Changes since v1:
>>- Removed UNSPEC_{INFINITE,ISNORMAL}
>>- Don't hardcode SI in patterns, try to keep X to avoid potential
>> sign extension pitfalls. Implementation w
On 7/1/24 06:42, Jeff Law wrote:
>>> This works because those expanders are allowed to use FAIL. Some
>>> expanders aren't allowed to do that (they're supposed to be documented
>>> appropriately in the internals manual).
>>>
>>> In the matching define_insns, you can use X and adjust their names.
>
On 7/3/24 12:08, Xi Ruoyao wrote:
> On Fri, 2024-06-28 at 17:53 -0700, Vineet Gupta wrote:
>> I was also hoping to get __builtin_inf() done but unforutnately it
>> requires little more rtl foo/bar to implement a tri-modal return.
> Hmm do we really need to care the sy
On 7/3/24 21:35, Xi Ruoyao wrote:
> On Sun, 2024-06-30 at 17:47 -0700, Vineet Gupta wrote:
>> - Don't hardcode SI in patterns, try to keep X to avoid potential
>> sign extension pitfalls. Implementation wise requires skipping
>> :MODE specifier in match_o
On 7/9/24 16:23, Jeff Law wrote:
>
> On 7/9/24 5:08 PM, Vineet Gupta wrote:
>> On 7/3/24 12:08, Xi Ruoyao wrote:
>>> On Fri, 2024-06-28 at 17:53 -0700, Vineet Gupta wrote:
>>>> I was also hoping to get __builtin_inf() done but unforutnately it
>>>>
On 6/30/24 06:59, Jeff Law wrote:
+;; TODO: isinf is a bit tricky as it require trimodal return
+;; 1 if 0x80, -1 if 0x1, 0 otherwise
>>> It shouldn't be terrible, but it's not trivial either.
>>>
>>> bext t0, a0, 0
>>> neg t0
>>> bext t1, a0, 7
>>> czero.nez res, t0, t1
>>> snez t1
+CC Hao Chen Gui
On 7/9/24 16:21, Jeff Law wrote:
- Don't hardcode SI in patterns, try to keep X to avoid potential
sign extension pitfalls. Implementation wise requires skipping
:MODE specifier in match_operand which is flagged as missing mode
warning.
>>> I'
On 7/9/24 21:36, Jeff Law wrote:
>> +;; TODO: isinf is a bit tricky as it require trimodal return
>> +;; 1 if 0x80, -1 if 0x1, 0 otherwise
[..]
>> + rtx tmp2 = gen_reg_rtx (word_mode);
>> + emit_insn (gen_ashldi3 (tmp2, rclass, GEN_INT (w)));
>> + emit_insn (gen_lshrdi3 (tmp2, tmp2
d UNSPEC_FCLASS.
define_insn and define_expand for fclass.
define_expand for isfinite, isnormal, isinf.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fclass.c: New tests.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.md | 134
101 - 200 of 381 matches
Mail list logo
