[PATCH][ARM][GCC][1/5x]: MVE store intrinsics.

for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise

[PATCH][ARM][GCC][2/5x]: MVE load intrinsics.

? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise

[PATCH][ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix.

. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni

[PATCH][ARM][GCC][8/5x]: Remaining MVE store intrinsics which stores an half word, word and double word to memory.

dre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro. (vstrdq_scatter_base_p_u64): Likewise. (vstrdq_scatter_base_s64): Likewise. (vstrdq_scatter_base_u64)

[PATCH][ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix.

tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin qualifier

[PATCH][ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads half word and word or double word from memory.

/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vldrdq_gather_base_s64): Define macro

[PATCH][ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic plus operator.

il Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vaddq_s8): Define macro. (vaddq_s16): Likewise. (vaddq_s32): Likewise. (vaddq_u8): Likewise. (vaddq_u16): Likewise. (vaddq_u32): Likewise. (vaddq_f16): Likewise. (vaddq_f32)

[PATCH][ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or word from memory.

/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16

[PATCH][ARM][GCC][7/5x]: MVE store intrinsics which stores byte,half word or word to memory.

, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vst1q_f32): Define macro. (vst1q_f16): Likewise. (vst1q_s8): Likewise. (vst1q_s32): Likewise. (vst1q_s16): Likewise

[PATCH][ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup intrinsics with writeback.

/testsuite/ChangeLog: 2019-11-07 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: New test. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics

[PATCH][ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics.

) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-14 Srinath Parvathaneni * config/arm

[PATCH][ARM][GCC][2/8x]: MVE ACLE gather load and scatter store intrinsics with writeback.

for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-07 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin qualifier. (LDRGBWBU_QUALIFIERS): Likewise. (LDRGBWBS_Z_QUALIFIERS

[PATCH][ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-care) variant.

? Thanks, Srinath. gcc/ChangeLog: 2019-11-14 Srinath Parvathaneni * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro. (vddupq_x_n_u16): Likewise. (vddupq_x_n_u32): Likewise. (vddupq_x_wb_u8): Likewise. (vddupq_x_wb_u16): Likewise. (vddupq_x_wb_u32

[PATCH][ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across beats" and "beat-wise substract".

k for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-08 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vadciq_s32): Define macro. (vadciq_u32): Likewise. (vadciq_m_s32): Likewise. (vadciq_m_u32): Likewise. (

[PATCH][ARM][GCC][14x]: MVE ACLE whole vector left shift with carry intrinsics.

/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-09 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h

[PATCH][ARM][GCC][13x]: MVE ACLE scalar shift intrinsics.

] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-08 Srinath Parvathaneni * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define

[PATCH][ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane.

tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-08 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vsetq_lane_f16): Define macro. (vsetq_lane_f32): Likewise

[PATCH][ARM][GCC][11x]: MVE ACLE vector interleaving store and deinterleaving load intrinsics and also aliases to vstr and vldr intrinsics.

found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-08 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vst1q_p_u8): Define macro. (vst1q_p_s8): Likewise. (vst2q_s8): Likewise. (vst2q_u8

[PATCH][ARM][GCC][0/x]: Support for MVE ACLE intrinsics.

s://gcc.gnu.org/ml/gcc-patches/2019-11/msg00641.html [6] https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01194.html Srinath Parvathaneni(38): [PATCH][ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. [PATCH][ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. [PATCH][ARM][GCC][3/x]: MVE ACLE intr

[GCC][ARM]: Fix the failing ACLE testcase with correct test directive.

19-11-21 Srinath Parvathaneni * gcc.target/arm/acle/crc_hf_1.c: Modify the compiler options directive from dg-options to dg-additional-options. ### Attachment also inlined for ease of reply### diff --git a/gcc/testsuite/gcc.target/arm/acle/crc

[ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions.

x27;t have commit rights. 2019-05-29 Srinath Parvathaneni Matthew Wahab * config/arm/iterators.md (fp16_rnd_str): Replace UNSPEC_VRND values with equivalent UNSPEC_VRINT values. Add UNSPEC_NVRINTZ, UNSPEC_NVRINTA, UNSPEC_NVRINTM, UNSPEC_NVRINTN, UNSP

[ARM][PATCH 2/2] Remove redundant constructs added for FP16 support.

emulator. Ok for trunk? If ok, could someone please commit the patch on my behalf, I don't have commit rights. 2019-05-29 Srinath Parvathaneni Matthew Wahab * config/arm/iterators.md (VCVT_HF_US_N): Remove. (VCVT_SI_US_N): Remove. (VCVT_HF_US): R

[PATCH][GCC][ARM] Add support for hint intrinsics: __yield, __wfe, __wfi, __sev and __sevl.

m/-march=armv4t acle.exp=hint-2.c" RUNTESTFLAGS="--target_board=arm-eabi-aem/-march=armv6t2 acle.exp=hint-3.c" Ok for trunk? If ok, could please someone commit the patch on my behalf, I don't have commit rights. Thanks, Srinath gcc/ChangeLog: 2019-05-29 Srinath Parva

[PATCH][GCC][AArch64] Add support for hint intrinsics: __yield, __wfe, __wfi, __sev and __sevl.

tested on aarch64-none-elf with no regressions. Ok for trunk? If ok, could someone please commit the patch on my behalf, I don't have commit rights. Thanks, Srinath gcc/ChangeLog: 2019-05-29 Srinath Parvathaneni * config/aarch64/aarch64.md (UNSPECV_YIELD): New volatile u

Re: [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions.

Hi, Pinging for review of https://gcc.gnu.org/ml/gcc-patches/2019-05/msg01921.html. Regards, SRI. From: gcc-patches-ow...@gcc.gnu.org<mailto:gcc-patches-ow...@gcc.gnu.org> <mailto:gcc-patches-ow...@gcc.gnu.org> on behalf of Srinath

Re: [ARM][PATCH 2/2] Remove redundant constructs added for FP16 support.

Hi, Pinging for review of https://gcc.gnu.org/ml/gcc-patches/2019-05/msg01922.html Regards, SRI. From: Srinath Parvathaneni <mailto:srinath.parvathan...@arm.com> Sent: 29 May 2019 15:48 To: gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>

[PATCH][GCC-8][AArch64] PR target/90075 Prefer bsl/bit/bif for copysignf. (backport GCC-8)

have commit rights. *** gcc/ChangeLog *** 2019-04-29 Srinath Parvathaneni Backport from mainline 2018-12-11 Richard Earnshaw PR target/37369 * config/aarch64/iterators.md (sizem1): Add sizes for SFmode and DFmode. (Vbtype): Add SFmode ma

[PATCH][GCC-7][AArch64] PR target/90075 Prefer bsl/bit/bif for copysignf. (backport GCC-7)

don't have commit rights. *** gcc/ChangeLog *** 2019-04-29 Srinath Parvathaneni PR target/90075 * config/aarch64/iterators.md (V_INT_EQUIV): Add mode for integer equivalent of floating point values. Backport from mainline 2018-12-11 Richard Ear

[PATCH 1/2][GCC][AArch64] Implement hint intrinsics for AArch64

patch on my behalf, I don't have commit rights. Thanks, Srinath gcc/ChangeLog: 2019-01-10 Srinath Parvathaneni * config/aarch64/aarch64.md (yield): New pattern name. (wfe): Likewise. (wfi): Likewise. (sev): Likewise. (sevl): Lik

[PATCH 2/2][GCC][ARM] Implement hint intrinsics for ARM

-linux-gnueabihf, regression tested on arm-none-eabi with no regressions and ran the added tests for arm, thumb-1 and thumb-2 modes. Ok for trunk? If ok, could someone commit the patch on my behalf, I don't have commit rights. Thanks, Srinath gcc/ChangeLog: 2019-01-10 Srinath Parvath

RE: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

Ping!! > -Original Message- > From: Gcc-patches bounces+srinath.parvathaneni=arm@gcc.gnu.org> On Behalf Of Srinath > Parvathaneni via Gcc-patches > Sent: 05 May 2022 12:02 > To: gcc-patches@gcc.gnu.org > Cc: Richard Earnshaw > Subject: [PATCH v2][GCC] ar

[GCC][PATCH] arm: Add support for Arm Cortex-M85 CPU.

-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-05 Srinath Parvathaneni * config/arm/arm-cpus.in (cortex-m85): Define new cpu. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * config/arm/t-rmprofile: Re-use

[GCC][PATCH] arm: Fix MVE intrinsics polymorphic variants wrongly generating __ARM_undef type (pr96795).

and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-09-30 Srinath Parvathaneni PR target/96795 * config/arm/arm_mve.h (__ARM_mve_coerce2): Define. (__arm_vaddq): Correct the scalar argument. (__arm_vaddq_m

[COMMITTED][GCC-10 backport] arm: Fix MVE intrinsics polymorphic variants wrongly generating __ARM_undef type (pr96795).

-linux-gnueabihf and regression tested on arm-none-eabi and found no regressions. Patch already approved in https://gcc.gnu.org/pipermail/gcc-patches/2020-September/555185.html , so committed this patch to releases/gcc-10 branch. Regards, Srinath. gcc/ChangeLog: 2020-09-30 Srinath

[PATCH][GCC] arm: Move iterators from mve.md to iterators.md to maintain consistency.

master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to iterators.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise

[PATCH][GCC-10 backport] arm: Remove coercion from scalar argument to vmin & vmax intrinsics.

Hello, Straight backport of Joe's patch with no changes. This patch fixes an issue with vmin* and vmax* intrinsics which accept a scalar argument. Previously when the scalar was of different width to the vector elements this would generate __ARM_undef. This change allows the scalar argument to be

RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md to maintain consistency.

Hi Kyrill, > -Original Message- > From: Kyrylo Tkachov > Sent: 06 October 2020 14:42 > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Subject: RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md > to maintain consistency. > > &

[GCC-10 backport][COMMITTED] arm: Move iterators from mve.md to iterators.md to maintain consistency.

unspecs.md file. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to iterators.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise. (MVE_3): Likewise. (MVE_2

[PATCH][GCC-10 backport] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55.

Backport of Joe's patch wit no changes. This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve:equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp: e

[PATCH][GCC] arm: Fix wrong code generated for mve scatter store with writeback intrinsics with -O2 (PR97271).

intrinsic where as fix generates only one vstrw assembly instruction (C). Bootstrapped on arm-none-linux-gnueabihf and regression tested on arm-none-eabi and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni

[GCC][PATCH] arm: Add cde feature support for Cortex-M55 CPU.

on arm-none-eabi target and found no regressions. [1] https://developer.arm.com/documentation/101051/0101/?lang=en (version: r1p1). Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-10-07 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde

Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

Ping!! From: Srinath Parvathaneni Sent: 12 November 2021 18:03 To: gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov ; Richard Earnshaw ; Tejas Belagod Subject: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature

RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.

Hi, > -Original Message- > From: Christophe Lyon > Sent: Monday, October 17, 2022 2:30 PM > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Earnshaw > Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55 > CPU. > > Hi S

[GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main.

one-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-10-28 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_branch_protection_option): Define new function. * config/arm/arm-cpus.in (armv8.1-m.main): Move dsp op

[Committed] arm: Document +no options for Cortex-M55 CPU.

floating point instructions) +nofp (disables floating point instructions) Committed as obvious to master. Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55 options. ### Attachment also inlined

[PATCH 13/15] arm: Add pacbti related multilib support for armv8.1-m.main.

-mfloat-abi=hard -mthumb $ -march=armv8.1-m.main+dsp+pacbti+fp.dp -mbranch-protection=standard -mfloat-abi=hard -mthumb Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni

RE: [GCC][PATCH v2] arm: Add support for Arm Cortex-M85 CPU.

-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni * config/arm/arm-cpus.in (cortex-m85): Define new CPU. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (Arm Options

[GCC 13/15][PATCH v3] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

movsr0, #0 aut ip, lr, sp bx lr .cfi_endproc ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-17 Srinath Parvathaneni * config/arm/aout.h (ra_auth_code): Add to enum.

[PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

aster? Regards, Srinath. gcc/ChangeLog: 2022-04-06 Srinath Parvathaneni * config/arm/aout.h (ra_auth_code): Add to enum. * config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE register to dwarf frame expression. (arm_emit_multi_reg_pop): Restore RA_AUT

[PATCH][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify. (IS_PAC_Pseudo_REGNUM): Define. (enum reg_class): Add PAC_REG entry. * config/arm/arm.md (RA_AUTH_CODE): Define. gcc/testsuite/ChangeLog: 2021-11-12 Srinath Parvathaneni * gcc.target/arm/pa

[PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify. (IS_PAC_Pseudo_REGNUM): Define. (enum reg_class): Add PAC_REG entry. * config/arm/arm.md (RA_AUTH_CODE): Define. gcc/testsuite/ChangeLog: 2021-11-12 Srinath Parvathaneni * g++.target/arm/pa

RE: [GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for -O0 (pr97205).

Ping!! > -Original Message- > From: Srinath Parvathaneni > Sent: 30 April 2021 16:24 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > > Subject: [GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for > -O0 (pr97205). > &g

[GCC][PATCH] arm: Fix multilib mapping for CDE extensions.

regressions. Ok for master? Regards, Srinath. gcc/ChangeLog: 2021-06-01 Srinath Parvathaneni PR target/100856 * common/config/arm/arm-common.c (arm_canon_arch_option): Modify function to generate canonical march string after removing cde related compiler extensions

RE: [GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

Hi Richard, > -Original Message- > From: Richard Earnshaw > Sent: 13 April 2021 14:55 > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Earnshaw > Subject: Re: [GCC][Patch] arm: Fix the mve multilib for the broken cmse > support (pr99939). >

[GCC][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.

_arm_vld2q): Likewise. (__arm_vld4q): Likewise. (__arm_vldrbq_gather_offset): Likewise. (__arm_vldrbq_gather_offset_z): Likewise. gcc/testsuite/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/101016 * gcc.target/arm/mve/intrinsics/pr101016.c

RE: [GCC][PATCH] arm: Fix multilib mapping for CDE extensions.

Hi Richard, I have all addressed all your review comments in the trailing in the patch attached. Please review and let me know if it ok for master? Regards, Srinath. > -Original Message- > From: Richard Earnshaw > Sent: 02 June 2021 15:20 > To: Srinath Parvathaneni ;

[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

9 and this patch fixes the issue. Regression tested on arm-none-eabi and found no regressions. Ok for master? and Ok for GCC-10 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler

[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

9 and this patch fixes the issue. Regression tested on arm-none-eabi and found no regressions. Ok for master? and Ok for GCC-10 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add sep

[GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for -O0 (pr97205).

Hi, This is a backport to GCC-10 to fix PR97205, patch applies cleanly on the branch. Regression tested and found no issues. Ok for GCC-10 backport? Regards, Srinath. This makes sure that stack allocated SSA_NAMEs are at least MODE_ALIGNED. Also increase the MEM_ALIGN for the corr

[GCC][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

-05-04 Srinath Parvathaneni PR target/100419 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. (__arm_vcmpneq): Remove duplicate definition. (__arm_vstrwq_scatter_offset_p): Likewise. (__arm_vmaxq_x): Likewise

RE: [GCC][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

Hi Richard, > -Original Message- > From: Richard Earnshaw > Sent: 05 May 2021 11:15 > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Earnshaw > Subject: Re: [GCC][PATCH] arm: Remove duplicate definitions from > arm_mve.h (pr100419). >

[GCC-10 backport][PATCH] arm: Fix testisms introduced with fix for pr target/95646.

Hi, This is a backport to gcc-10, cleanly applied on the branch. This patch changes the test to use the effective-target machinery disables the error message "ARMv8-M Security Extensions incompatible with selected FPU" when -mfloat-abi=soft. Further changes 'asm' to '__asm__' to avoid failures wi

[GCC-10 backport][PATCH] arm: PR target/95646: Do not clobber callee saved registers with CMSE.

Hi, This is a backport to gcc-10, cleanly applied on the branch. As reported in bugzilla when the -mcmse option is used while compiling for size (-Os) with a thumb-1 target the generated code will clear the registers r7-r10. These however are callee saved and should be preserved accross ABI bound

[GCC-11 backport][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

/ChangeLog: 2021-05-04 Srinath Parvathaneni PR target/100419 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. (__arm_vcmpneq): Remove duplicate definition. (__arm_vstrwq_scatter_offset_p): Likewise. (__arm_vmaxq_x): Likewise

[GCC-10 backport][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

/ChangeLog: 2021-05-04 Srinath Parvathaneni PR target/100419 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. (__arm_vcmpneq): Remove duplicate definition. (__arm_vstrwq_scatter_offset_p): Likewise. (__arm_vmaxq_x): Likewise

RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.

Ping!! - From: Srinath Parvathaneni Sent: Tuesday, December 6, 2022 11:32 AM To: gcc-patches@gcc.gnu.org; Richard Earnshaw Cc: Christophe Lyon Subject: Re: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU. Ping

[Committed] arm: Add cde feature support for Cortex-M55 CPU.

on arm-none-eabi target and found no regressions. [1] https://developer.arm.com/documentation/101051/0101/?lang=en (version: r1p1). Ok for master? Regards, Srinath. gcc/ChangeLog: 2023-01-13 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde

[GCC][PATCH 13/15, v5] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

12 push{r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. 2023-01-11 Srina

[GCC][PATCH v4] arm: Add pacbti related multilib support for armv8.1-m.main.

used in the multilib matching. Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2023-01-11 Srinath Parvathaneni * config.gcc ($tm_file): Update variable. * config/arm/arm-mlib.h: Create new header file.

[GCC][PATCH 13/15, v6] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

12 push{r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. 2023-01-18 Srina

RE: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

Hi Ramana, > -Original Message- > From: Ramana Radhakrishnan > Sent: Sunday, November 20, 2022 10:48 PM > To: Srinath Parvathaneni > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > ; Kyrylo Tkachov > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwindin

[PATCH][COMMITTED][GCC-10 backport] arm: Fix wrong code generated for mve scatter store with writeback intrinsics with -O2 (PR97271).

one vstrw assembly instruction (C). Patch backport approved here https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556373.html gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni PR target/97271 * config/arm/arm-builtins.c (arm_strsbwbs_qualifiers): Mod

[PATCH][GCC-10 backport] arm: [MVE] Add vqdmlashq intrinsics (PR target/96914)

Hello, Applied cleanly, Ok for backporting this patch to GCC-10? This patch adds: vqdmlashq_m_n_s16 vqdmlashq_m_n_s32 vqdmlashq_m_n_s8 vqdmlashq_n_s16 vqdmlashq_n_s32 vqdmlashq_n_s8 2020-10-08 Christophe Lyon gcc/ PR target/96914 * config/arm/arm_mve.h (vqdmlashq, vqd

[PATCH][GCC-10 backport] arm: [MVE] Add missing __arm_vcvtnq_u32_f32 intrinsic (PR 96914)

Hello, Applied cleanly, Ok for backporting this patch to GCC-10? __arm_vcvtnq_u32_f32 was missing from arm_mve.h, although the s32_f32 and [su]16_f16 versions were present. This patch adds the missing version and testcase, which are cut-and-paste from the other versions. 2020-10-08 Christophe

[PATCH][GCC-10 backport] arm: [MVE] Remove illegal intrinsics (PR target/96914)

Hello, Applied cleanly, Ok for backporting this patch to GCC-10? A few MVE intrinsics had an unsigned variant implement while they are supported by the hardware. This patch removes them: __arm_vqrdmlashq_n_u8 __arm_vqrdmlahq_n_u8 __arm_vqdmlahq_n_u8 __arm_vqrdmlashq_n_u16 __arm_vqrdmlahq_n_u16 _

[PATCH][GCC] arm: Fix the warning -mcpu=cortex-m55 conflicting with -march=armv8.1-m.main (pr97327).

bove combinations no warning/errors. Regression tested on arm-none-eabi and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-10-16 Srinath Parvathaneni PR target/97327 * config/arm/arm.c (fp_bitlist): Add isa_bit_mve_float to

[PATCH][GCC-10 backport][COMMITTED] arm: Fix the warning -mcpu=cortex-m55 conflicting with -march=armv8.1-m.main (pr97327).

: cc1: warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main' switch After this patch for above combinations no warning/errors. gcc/ChangeLog: 2020-10-16 Srinath Parvathaneni PR target/97327 * config/arm/arm.c (fp_bitlist): Add isa_bit_

[GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

12 push{r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/testsuite/Cha

[PATCH][GCC] arm: Add support for Cortex-X1C CPU.

Hi, This patch adds the -mcpu support for the Arm Cortex-X1C CPU. Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/arm/arm-cpus.in

[PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

;0xb5" instruction is not encountered then CFA will be used as modifier in pointer authentication. [1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/C

[PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.

Hi, This patch adds support for Cortex-A715 CPU. Bootstrapped on aarch64-none-linux-gnu and found no regressions. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715 CPU

[PATCH][GCC] aarch64: Add support for Cortex-X1C CPU.

Hi, This patch adds support for Cortex-X1C CPU. Bootstrapped on aarch64-none-linux-gnu and found no regressions. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X1C CPU

RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.

Hi, > -Original Message- > From: Kyrylo Tkachov > Sent: Friday, November 11, 2022 2:24 PM > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Sandiford > Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU. > > Hi Srinath, &

[PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.

Hi, This patch adds support for Cortex-X3 CPU. Bootstrapped on aarch64-none-linux-gnu and found no regressions. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X3 CPU

RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.

Hi, > -Original Message- > From: Kyrylo Tkachov > Sent: Monday, November 14, 2022 2:47 PM > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Sandiford > Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU. > > > > >

RE: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

Hi, > -Original Message- > From: Ramana Radhakrishnan > Sent: Thursday, November 17, 2022 8:27 PM > To: Srinath Parvathaneni > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > ; Kyrylo Tkachov > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwindin

[PATCH v2][GCC] arm: Add support for new frame unwinding instruction "0xb5".

;0xb5" instruction is not encountered then CFA will be used as modifier in pointer authentication. [1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/C

[Committed][GCC] arm: Documentation fix for -mbranch-protection option.

Hello, This patch fixes the documentation for -mbranch-protection command line option. Committed this patch to trunk as obvious fix. Regards, Srinath. gcc/ChangeLog: 2023-01-23 Srinath Parvathaneni * doc/invoke.texi (-mbranch-protection): Update documentation

[PATCH][GCC] arm: Fix inclusion of arm-mlib.h header more than once (pr108505).

found no regressions. Ok for master? Regards, Srinath. gcc/ChangeLog: 2023-01-24 Srinath Parvathaneni PR target/108505 * config.gcc (tm_file): Move the variable out of loop. ### Attachment also inlined for ease of reply### diff --git a/gcc

[PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).

-eabi target and found no regressions. Ok for master? [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610513.html Regards, Srinath. gcc/ChangeLog: 2023-01-27 Srinath Parvathaneni PR target/108505 * config.gcc (tm_mlib_file): Define new var

Re: [PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).

Ping!! From: Gcc-patches on behalf of Srinath Parvathaneni via Gcc-patches Sent: 27 January 2023 17:44 To: gcc-patches@gcc.gnu.org Cc: nd ; Richard Earnshaw ; Kyrylo Tkachov Subject: [PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505). Hello

[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-04-12 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-20.c: New test. libgcc/ChangeLog: 2021-04-12 Srinath Parvathaneni PR target/99939 * config/arm/t-arm: Make changes to use cmse.c f

[GCC-11 backport][PATCH] arm: Fix the mve multilib for the broken cmse support (pr99939).

-11 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler directives check for target is v8.1-m.main+mve or not before comparing the assem

[GCC-10 backport][PATCH] arm: Fix the mve multilib for the broken cmse support (pr99939).

-10 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler directives check for target is v8.1-m.main+mve or not before comparing the assem

[GCC-11 backport][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.

/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants matching code. (__arm_vld1q_z)

[GCC-10 backport][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.

s, Srinath. gcc/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants mat

[GCC][PATCH] arm: Fix multilib mapping for CDE extensions [PR100856].

/gcc-patches/2021-June/571731.html Regards, Srinath. gcc/ChangeLog: 2021-06-14 Srinath Parvathaneni PR target/100856 * common/config/arm/arm-common.c (arm_canon_arch_option_1): New function derived from arm_canon_arch. (arm_canon_arch_option): Call it

[PATCH][GCC-10] arm: Fix multilib mapping for CDE extensions [PR100856].

compiler options which are not required for multilib linking from march string and assign the new string to mlibarch option. This mlibarch string is used for multilib comparison. Ok for gcc-10 branch? Regards, Srinath. gcc/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/100856

[PATCH][GCC-11] arm: Fix multilib mapping for CDE extensions [PR100856].

compiler options which are not required for multilib linking from march string and assign the new string to mlibarch option. This mlibarch string is used for multilib comparison. Ok for gcc-11 branch? Regards, Srinath. gcc/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/100856

Re: [GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main.

Ping!! From: Gcc-patches on behalf of Srinath Parvathaneni via Gcc-patches Sent: 31 October 2022 15:36 To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main. Hi, This patch

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