Register pressure aware loop unrolling

ing parameter PARAM_LOOP_UNROLL_PRESSURE_INCREMENT. The equation become high_reg_pressure_p = true if (live_reg_num + PARAM_LOOP_UNROLL_PRESSURE_INCREMENT > available_hard_reg_num) Bootstrapped and tested on x86-64. Any suggestion ? Thanks, Shiva 2015-12-11 Shiva Chen * cfgloop.h (s

[libatomic PATCH] Fix libatomic behavior for big endian toolchain

it ok for trunk ? Shiva 2014-10-17 Shiva Chen Fix libatomic behavior for big endian toolchain * libatomic/cas_n.c: Fix shift amount for big endian toolchain * libatomic/config/arm/exch_n.c: Fix shift amount for big endian toolchain * libatomic/exch_n.c: Fix shift amount for big endian

Re: [libatomic PATCH] Fix libatomic behavior for big endian toolchain

Hi, Joseph I have been modify the patch as your suggestion use # if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ in architecture-independent files Is it ok for trunk ? And I don't have svn write access Could you help me to commit this patch? Shiva 2014-10-17 23:41 GMT+08:00 Joseph S. Myers : > Chang

aarch64 simd index out of range message not correct on 32 bit host

Hi, I notice that aarch64 simd index range message not correct on 32 bit host. The message print by the function aarch64_simd_lane_bounds in aarch64.c. The function print HOST_WIDE_INT variable by %ld which is correct on 64 bit host. However, on 32 bit host HOST_WIDE_INT would be long long. Th

Re: aarch64 simd index out of range message not correct on 32 bit host

Hi, Andrew You are right, it's much simpler. Could you give me a tip how %wd works on GCC ? Could you send a new patch to fix the message since you have better solution ? Thanks, Shiva 2015-05-29 15:13 GMT+08:00 Andrew Pinski : > On Fri, May 29, 2015 at 2:33 PM, Shiva Chen wrot

Re: aarch64 simd index out of range message not correct on 32 bit host

Hi, Andrew I modify the patch as you suggestion and testing on 32/64 bit host. Thanks your tips. I really appreciate for your help. Shiva 2015-05-29 15:57 GMT+08:00 Andrew Pinski : > On Fri, May 29, 2015 at 3:46 PM, Shiva Chen wrote: >> Hi, Andrew >> >> You are rig

[GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

Hi, I noticed that armv8(32 bit target) linux toolchain run asan testcase would get the following message: FAIL: c-c++-common/asan/heap-overflow-1.c -O0 output pattern test, is Executing on host: /home/gccbuilder-x86/test/mgcc5.0/testsuite/../tools/x86_64/install/bin/qemu-arm -E LD_LIBRARY_PAT

Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

Hi, Ramana I'm not sure what copyright assignment means ? Does it mean the patch have copyright assignment or not ? I update the patch to add "predicable" and "predicable_short_it" attribute as suggestion. However, I don't have svn write access yet. Shiva 2015-06-03 16:36 GMT+08:00 Kyrill Tk

Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

03 17:29 GMT+08:00 Shiva Chen : > Hi, Ramana > > I'm not sure what copyright assignment means ? > > Does it mean the patch have copyright assignment or not ? > > I update the patch to add "predicable" and "predicable_short_it" > attribute as sugg

RE: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

mething. Thanks, Shiva -Original Message- From: Richard Earnshaw [mailto:richard.earns...@foss.arm.com] Sent: Thursday, June 04, 2015 4:42 PM To: Kyrill Tkachov; Shiva Chen Cc: Ramana Radhakrishnan; GCC Patches; ni...@redhat.com; Shiva Chen Subject: Re: [GCC, ARM] armv8 linux toolchain asan tes

Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

assembly output format for strb with condition code on arm/thumb mode. Because arm/thumb mode use different syntax for strb, we output the assembly as str%(%) which will put the condition code in the right place according to TARGET_UNIFIED_ASM. Is there still missing something ? Thanks, Shiva

Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

Hi, Kyrill I add the testcase as stl-cond.c. Could you help to check the testcase ? If it's OK, Could you help me to apply the patch ? Thanks, Shiva 2015-06-05 16:34 GMT+08:00 Kyrill Tkachov : > Hi Shiva, > > On 05/06/15 09:29, Shiva Chen wrote: >> >> Hi, Kyrill &

Re: ira.c update_equiv_regs patch causes gcc/testsuite/gcc.target/arm/pr43920-2.c regression

? Thanks again. Shiva 2015-04-18 0:03 GMT+08:00 Jeff Law : > On 04/17/2015 03:57 AM, Shiva Chen wrote: >> >> Hi, >> >> I think the rtl dump in >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64916 >> is not jump2 phase rtl dump. >> >> Because jump2 i

Re: [wwwdocs] nds32 documentation - remove broken reference

Hi Gerald, The update link will be http://www.andestech.com/en/products-solutions/product-documentation/ Thanks for your kindly remind, Shiva Gerald Pfeifer 於 2019年7月28日 週日 下午4:54寫道： > I could not find an updated link on www.andestech.com, in fact the > reference I could find there was broken a

Re: [PATCH] [NDS32] Fix nds32_split_ashiftdi3 with large shift amount

Hi Kito, Thanks for the patch. Kito Cheng 於 2019年2月22日 週五 下午4:42寫道： > From: Kito Cheng > > ChangeLog: > gcc/ > * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): > Fix wrong code gen with large shift amount. > --- > gcc/config/nds32/nds32-md-auxiliary.c | 21 +

Re: [PATCH 2/7] [NDS32] Fix testsuite for nds32 target

LGTM. Kito Cheng 於 2019年3月26日 週二 下午1:29寫道： > From: Kito Cheng > > Chung-Ju Wu > Shiva Chen > > ChangeLog: > > gcc/testsuite/ > * gcc.c-torture/execute/20010122-1.c: Add -malways-save-lp for > nds32. > * gcc.c-torture/execute/pr6082

Re: [PATCH 1/7] [NDS32] Provide one valid nds32 assembly instruction to check assembler debugging options and features.

LGTM. Kito Cheng 於 2019年3月26日 週二 下午1:29寫道： > From: Chung-Ju Wu > > Chung-Ju Wu > > ChangeLog > gcc/ > * configure.ac: Add nds32 target for dwarf2 debug_line checking. > * configure: Regenerated. > --- > gcc/configure| 2 +- > gcc/configure.ac | 2 +- > 2 files changed, 2

Re: [PATCH 3/7] [NDS32] Rewrite PIC/TLS patterns.

LGTM. Kito Cheng 於 2019年3月26日 週二 下午1:29寫道： > From: Monk Chiang > > Monk Chiang > Kito Cheng > Shiva Chen > > ChangeLog > gcc/ > * config/nds32/nds32-md-auxiliary.c (nds32_legitimize_pic_address): > Use new PIC pattern. > (nds32_leg

Re: [PATCH 4/7] [NDS32] nds32*-linux target using init_array/finit_array for ctor/dtor.

LGTM. Kito Cheng 於 2019年3月26日 週二 下午1:29寫道： > From: Monk Chiang > > Monk Chiang > > ChangeLog > > * config.gcc (nds32*-*-linux*): Set gcc_cv_initfini_array to yes. > --- > gcc/config.gcc | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/gcc/config.gcc b/gcc/config.gcc > index 3

Re: [PATCH 6/7] [NDS32] Handle subreg correctly in wext_odd_dep_p.

LGTM. Kito Cheng 於 2019年3月26日 週二 下午1:29寫道： > From: Kito Cheng > > Kito Cheng > Shiva Chen > > ChangeLog: > gcc/ > * config/nds32/nds32-pipelines-auxiliary.c (wext_odd_dep_p): > Handle subreg. > > gcc/testsuite > * gcc.target

Re: [PATCH 5/7] [NDS32] Refine force unwind, linux kernel only using RT_SIGRETURN.

LGTM. Kito Cheng 於 2019年3月26日 週二 下午1:29寫道： > From: Monk Chiang > > Monk Chiang > > ChangeLog > libgcc/ > * config/nds32/linux-unwind.h (SIGRETURN): Remove. > (RT_SIGRETURN): Update. > (nds32_fallback_frame_state): Update. > --- > libgcc/config/nds32/linux-unwind.h | 9

Re: [PATCH 7/7] [NDS32] Fix nds32_split_ashiftdi3 with large shift amount

LGTM. Kito Cheng 於 2019年3月26日 週二 下午1:29寫道： > From: Kito Cheng > > Kito Cheng > Shiva Chen > > ChangeLog: > gcc/ > * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): > Fix wrong code gen with large shift amount. > > gcc/testsu

RE: [PATCH 1/7] SMS remove dependence on doloop: Use loop induction variable analysis in SMS pass

Hi, Jeff Thanks for the tips. I update the patches to pass regression test and x86 bootstrap when sms enabled as default. Shiva -Original Message- From: Jeff Law [mailto:l...@redhat.com] Sent: Thursday, June 23, 2016 12:43 AM To: Shiva Chen; GCC Patches; bschm...@redhat.com; Shiva

[PATCH][SMS] SMS use loop induction variable analysis instead of depending on doloop optimization

Hi, According to Richard's suggestion in https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01240.html I try to remove the SMS dependency on doloop pass. SMS would need to adjust kernel loop iteration count during the transformation. To adjust loop iteration count, SMS would need to find count_reg w

RE: [PATCH][SMS] SMS use loop induction variable analysis instead of depending on doloop optimization

Hi, I fixed some bug to pass testing on x86-64 and update the patch as 0001-SMS-use-loop-induction-variable-analysis-v1.patch. Thanks, Shiva -Original Message- From: Shiva Chen Sent: Thursday, April 28, 2016 2:07 PM To: GCC Patches ; Shiva Chen Subject: [PATCH][SMS] SMS use loop

[PATCH 1/7] SMS remove dependence on doloop: Use loop induction variable analysis in SMS pass

Hi, SMS transformation would change the kernel loop iteration count. To do this, SMS pass will find the register contain loop count and generate the instructions to adjust loop count. Currently, SMS will try to find count_reg by recognizing doloop_end pattern which means if the target didn't defi

[PATCH 3/7] SMS remove dependence on doloop: Update loop-versioning for the loop with step != 1

Hi, To avoid the loop with loop_count < stage_count execute the SMS version loop, SMS will try to get loop iteration count. If the loop iteration count can't get by compile time, SMS will do loop-versioning which will generate original loop and SMS version loop with runtime checking code. With do

[PATCH 2/7] SMS remove dependence on doloop: Use get_simple_loop_desc to get loop iteration count

Hi, The loop after SMS transformation would at least execute stage_count times (due to the duplication in prolog/epilog). To avoid the loop with loop_count < stage_count execute the sms version loop, SMS will try to get loop iteration count. Currently, SMS would get iteration count by finding the

[PATCH 5/7] SMS remove dependence on doloop: update generate_prolog_epilog for the case without doloop pass

Hi, SMS transformation will generate prolog/epilog which are part of the duplication of the instructions in the loop. Doloop optimization will generate a new register(count_reg) to hold iteration count. Therefore, there will no count_reg reference in the loop (except increment/decrement and compa

[PATCH 6/7] SMS remove dependence on doloop: skip the loop if the loop size too small

Hi, SMS loop versioning will generate extra condition code. If SMS could not find enough overlapping in the loop, it may drop performance. Adding parameter PARAM_SMS_LOOP_MIN_SIZE with default value 8 to skip small loops which may not find enough overlapping instructions. Thanks, Shiva 0006-s

[PATCH 7/7] SMS remove dependence on doloop: To identify read/write register as loop induction variable

Hi, We use loop induction variable analysis to find count_reg. Without doloop optimization, count_reg might be a READ_WRITE_REG. E.g. while (reg < 0x200) { MEM [++reg:SI] = 5} READ_WRITE_REG won't identify as loop induction variable and SMS will skip the loop. We modify loop-iv.c to identify th

[PATCH 4/7] SMS remove dependence on doloop: update kernel loop iteration adjustment instruction generation

Hi, SMS transformation would change kernel loop iteration count as new_loop_count = ori_loop_count - stage_count. With doloop optimization, loop_count will hold in count_reg in loop entry. The loop count adjustment instruction could generate as count_reg = count_reg - stage_count before en

[PATCH 0/7] SMS remove dependence on doloop

Hi, The patch try to remove SMS dependency on doloop pass. With the patch, backend don't have to define doloop_end pattern or activate doloop optimization for SMS pass. According the review comment from Bernd https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01960.html I rewrite some comments and sp

Re: [PATCH][SMS] SMS use loop induction variable analysis instead of depending on doloop optimization

Hi, Bernd Thanks for the review. > > You might want to split it up if there are several logically independent > pieces. I can't quite make sense of it all, and I'm not too familiar with SMS > anyway, so the following is not a complete review, just a selection of issues > I observed. Ok, I hav

Re: [PATCH 7/7] SMS remove dependence on doloop: To identify read/write register as loop induction variable

Hi, Bernd 2016-05-13 20:33 GMT+08:00 Bernd Schmidt : > On 05/05/2016 08:03 AM, Shiva Chen wrote: >> >> >> - /* We do not handle setting only part of the register. */ >> - if (DF_REF_FLAGS (adef) & DF_REF_READ_WRITE) >> -return GRD_INVALID; >>

[libatomic PATCH] [PING] Fix libatomic behavior for big endian toolchain

PING https://gcc.gnu.org/ml/gcc-patches/2014-10/msg01763.html 2014-10-17 Shiva Chen Fix libatomic behavior for big endian toolchain * cas_n.c: Fix shift amount for big endian toolchain * config/arm/exch_n.c: Fix shift amount for big endian toolchain * exch_n.c: Fix shift amount for big

Re: LRA assign same hard register with live range overlapped pseduos

t gcc/ChangeLog is as below: 2013-04-23 Shiva Chen * lra-assigns.c (find_hard_regno_for): Use lra_reg_val_equal_p to check the register content is equal or not. * lra-constraints.c (match_reload): Use lra_assign_reg_val to assign register content record.