Prathamesh Kulkarni via Gcc-patches writes:
> Hi,
> The attached patch adjusts vec_perm_const hook to accommodate the new
> parameter.
> For rationale, please see:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
> OK to commit if bootstrap+test passes ?
>
> Thanks,
> Prathamesh
>
David Malcolm via Gcc-patches writes:
> gcc/ChangeLog:
> * config/aarch64/aarch64-sve-builtins-base.cc: Replace uses of
> "FINAL" and "OVERRIDE" with "final" and "override".
> * config/aarch64/aarch64-sve-builtins-functions.h: Likewise.
> * config/aarch64/aarch64-sve-builti
Dimitar Dimitrov writes:
> On Sun, May 08, 2022 at 10:31:04AM +0300, Dimitar Dimitrov wrote:
>> This patch fixes a spurious warning for pru-unknown-elf target:
>> gcc/testsuite/gcc.dg/mallign.c:12:27: warning: ignoring return value of
>> 'malloc' declared with attribute 'warn_unused_result' [-W
Joel Brobecker via Gcc-patches writes:
> Hello,
>
> Gentle ping on this patch.
>
> Thank you!
>
> On Mon, Apr 25, 2022 at 09:04:51AM -0700, Joel Brobecker wrote:
>> Hello,
>>
>> We have noticed that, when running the GCC testsuite on AArch64
>> RTEMS 6, we have about 150 tests failing due to a li
Prathamesh Kulkarni writes:
> On Wed, 18 May 2022 at 17:27, Richard Sandiford
> wrote:
>>
>> Prathamesh Kulkarni writes:
>> > Hi,
>> > The attached patch adds another parameter machine_mode op_mode to
>> > vec_perm_const
>> > hook to specify mode of input operands. The motivation for doing this
Prathamesh Kulkarni writes:
> Hi Richard,
> The attached patch addresses formatting nits for affected targets.
> Tested with make all-gcc stage1 (except for gcn).
OK, thanks.
> Sorry if this sounds like a naive question, but what target triplet
> should I use to build gcn port ?
I think it's am
Prathamesh Kulkarni writes:
> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
> index c5006afc00d..0a3c733ada9 100644
> --- a/gcc/doc/tm.texi
> +++ b/gcc/doc/tm.texi
> @@ -6088,14 +6088,18 @@ for the given scalar type @var{type}.
> @var{is_packed} is false if the scalar
> access using @var{type}
Richard Biener writes:
> This is another place where we fail to pass down the mode of a
> CONST_INT.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, OK?
>
> Thanks,
> Richard.
>
> 2022-05-24 Richard Biener
>
> PR middle-end/105711
> * expmed.cc (extract_bit_field_as_subreg)
Wilco Dijkstra writes:
> Increase the priority of the init_have_lse_atomics constructor so it runs
> before other constructors. This improves chances that rr works when LSE
> atomics are supported.
Can you add a comment above the function explaining why we chose 90
in particular? I see 100 was o
"H.J. Lu via Gcc-patches" writes:
> On Mon, May 23, 2022 at 12:38:06PM +0200, Richard Biener wrote:
>> On Sat, May 21, 2022 at 5:02 AM H.J. Lu via Gcc-patches
>> wrote:
>> >
>> > When recording store for RTL dead store elimination, check if the source
>> > register is set only once to a constant.
Szabolcs Nagy writes:
> The 05/13/2022 16:35, Richard Sandiford wrote:
>> Szabolcs Nagy via Gcc-patches writes:
>> > The RA_SIGN_STATE dwarf pseudo-register is normally only set using the
>> > DW_CFA_AARCH64_negate_ra_state (== DW_CFA_window_save) operation which
>> > toggles the return address s
FX via Gcc-patches writes:
> Hi,
>
> Attached is a fix for https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57076
> Currently, we cannot build GCC when the source directory contains a @
> character (which is a problem for Homebrew, where we typically build in
> directories such as /tmp/gcc@10/src:
"Kewen.Lin" writes:
> diff --git a/gcc/function.c b/gcc/function.c
> index 2c8fa217f1f..3e92ee9c665 100644
> --- a/gcc/function.c
> +++ b/gcc/function.c
> @@ -4841,6 +4841,8 @@ allocate_struct_function (tree fndecl, bool abstract_p)
> binding annotations among them. */
>cfun->debug_nonb
Sudakshina Das writes:
> Hi
>
> Currently the testcase in the patch was failing to produce
> a 'bti c' at the beginning of the function. This was because
> in aarch64_pac_insn_p, we were wrongly returning at the first
> check. This patch fixes the return value.
>
> Bootstrap and regression tested
"yangyang (ET)" writes:
> Hi,
>
> I have revised the patch based on your suggestions, and the following are
> some points that I think is needed to be mentioned in the mail.
>
>> > @@ -502,17 +504,18 @@ simd_clone_adjust_return_type (struct
>> cgraph_node *node)
>> > veclen = node->simdclone
Alan Modra writes:
> On Fri, Oct 30, 2020 at 09:21:09AM +, Richard Sandiford wrote:
>> Alan Modra via Gcc-patches writes:
>> > This moves an #ifdef block of code from calls.c to
>> > targetm.function_ok_for_sibcall. Only two targets, x86 and rs6000,
>> > define REG_PARM_STACK_SPACE or OUTGOI
Eh, never mind the previous message, I managed to miss the follow-ups.
Alan Modra writes:
> On Sat, Oct 31, 2020 at 12:10:35AM +1030, Alan Modra wrote:
>> Would it be better if I post the patches again, restructuring them as
>> 1) completely no functional change just moving the existing condition
FX via Gcc-patches writes:
> Here is an updated patch, that quotes all three makeinfo special characters:
> @ { }
> Tested on a build with source directory /tmp/foo@bar{gee}qux
>
> OK to commit?
>
> diff --git a/gcc/Makefile.in b/gcc/Makefile.in
> index 7b94497b6f2..978a08f7b04 100644
> --- a/gcc
Hongtao Liu writes:
> On Fri, Oct 30, 2020 at 1:00 AM Richard Sandiford
> wrote:
>>
>> I guess my main objection is that we have a special memory constraint
>> that isn't in fact matching a MEM (at least not directly). That seems
>> odd and feels like it's going to come back to bite us.
>>
>> Fr
Dennis Zhang writes:
> Hi Richard,
>
> On 10/29/20 5:48 PM, Richard Sandiford wrote:
>> Dennis Zhang writes:
>>> diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
>>> b/gcc/config/aarch64/aarch64-simd-builtins.def
>>> index 5bc596dbffc..b68c3ca7f4b 100644
>>> --- a/gcc/config/aarch64/aar
Sudakshina Das writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: 30 October 2020 19:56
>> To: Sudakshina Das
>> Cc: Wilco Dijkstra ; gcc-patches@gcc.gnu.org;
>> Kyrylo Tkachov ; Richard Earnshaw
>>
>> Subject: Re: [PATCH] aarch64: Add backend support for expanding
>> __b
Vladimir Makarov via Gcc-patches writes:
> On 2020-10-27 2:53 a.m., Hongtao Liu wrote:
>> Hi:
>>For inline asm, there could be an operand like (not (mem:)), it's
>> not a valid operand for normal memory constraint.
>>Bootstrap is ok, regression test is ok for make check
>> RUNTESTFLAGS="--
xiezhiheng writes:
>> -Original Message-
>> From: Richard Sandiford [mailto:richard.sandif...@arm.com]
>> Sent: Friday, October 30, 2020 6:24 PM
>> To: xiezhiheng
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions
>> emitted at -O3
>>
Dennis Zhang writes:
> Hi Richard,
>
> On 10/30/20 2:07 PM, Richard Sandiford wrote:
>> Dennis Zhang writes:
>>> diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
>>> b/gcc/config/aarch64/aarch64-simd-builtins.def
>>> index 332a0b6b1ea..39ebb776d1d 100644
>>> --- a/gcc/config/aarch64/aar
"yangyang (ET)" writes:
> Hi,
>
> I have revised the patch based on your suggestions. I use multiple_p instead
> of !multiple_p if the eq situation is OK to make it easier to understand.
>
>> >> > if (n->simdclone->inbranch)
>> >> > this_badness += 2048;
>> >> > int target_badness =
Hongtao Liu writes:
> On Tue, Nov 3, 2020 at 9:51 PM Richard Sandiford
> wrote:
>>
>> Vladimir Makarov via Gcc-patches writes:
>> > On 2020-10-27 2:53 a.m., Hongtao Liu wrote:
>> >> Hi:
>> >>For inline asm, there could be an operand like (not (mem:)), it's
>> >> not a valid operand for norma
"yangyang (ET)" writes:
> Hi,
>
>> -Original Message-
>> From: Richard Sandiford [mailto:richard.sandif...@arm.com]
>> Sent: Wednesday, November 4, 2020 12:15 AM
>> To: yangyang (ET)
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH 1/5] [PR target/96342] Change field "simdlen" into
Jojo R writes:
> gcc/ChangeLog:
>
> * genemit.c (main): Print 'split line'.
> * Makefile.in (insn-emit.c): Define split count and file
Looks good, thanks. Will commit once the copyright situation is
sorted out.
Richard
>
> ---
> gcc/Makefile.in | 35 +++-
> gcc/genemi
Tobias Burnus writes:
> Three of the testcases fail on PowerPC:
> gcc.target/i386/zero-scratch-regs-{9,10,11}.c
>powerpc64le-linux-gnu/default/gcc.d/zero-scratch-regs-10.c:77:1: sorry,
> unimplemented: '-fzero-call-used_regs' not supported on this target
>
> Did you miss some dg-require-effe
Matthew Malcomson writes:
> Hi Richard,
>
> I'm sending up the revised patch 5 (introducing stack variable handling)
> without the other changes to other patches.
>
> I figure there's been quite a lot of changes to this patch and I wanted
> to give you time to review them while I worked on finishi
Thanks for the patch, looks good.
David Candler writes:
> diff --git a/gcc/config/aarch64/aarch64-builtins.c
> b/gcc/config/aarch64/aarch64-builtins.c
> index 4f33dd936c7..f93f4e29c89 100644
> --- a/gcc/config/aarch64/aarch64-builtins.c
> +++ b/gcc/config/aarch64/aarch64-builtins.c
> @@ -254,6 +
Olivier Hainque writes:
> Ping, please ?
>
> Patch re-attached for convenience.
Looks OK to me, and I assume Richard would have spoken up by now if
he didn't think the patch did what he wanted.
> +;; The pair of scratch registers used for stack probing with
> -fstack-check.
> +;; Leave
Olivier Hainque writes:
> Hello,
>
> This patch adds dg-require-effective-target fpic
> to an aarch64 specific gcc.dg test using -fPIC,
> which helps circumvent a failure we observed while
> testing the aarch64 port for VxWorks.
>
> ok to commit ?
OK, thanks. Also OK for any other current or fut
Sorry, going it over it again before committing, I spotted a couple
of things…
Jojo R writes:
> gcc/ChangeLog:
>
> * genemit.c (main): Print 'split line'.
> * Makefile.in (insn-emit.c): Define split count and file
>
> ---
> gcc/Makefile.in | 35 +++-
> gcc/genemit.c |
This patch adds support for permuting unpacked SVE vectors using:
- DUP
- EXT
- REV[BHW]
- REV
- TRN[12]
- UZP[12]
- ZIP[12]
This involves rewriting the REV[BHW] permute code so that the inputs
and outputs of the insn pattern have the same mode as the vectors
being permuted. This is different fr
David Candler writes:
> Hi Richard,
>
> Thanks for the feedback.
>
> Richard Sandiford writes:
>> > diff --git a/gcc/config/aarch64/aarch64-builtins.c
>> > b/gcc/config/aarch64/aarch64-builtins.c
>> > index 4f33dd936c7..f93f4e29c89 100644
>> > --- a/gcc/config/aarch64/aarch64-builtins.c
>> > +++
Olivier Hainque writes:
>> On 4 Nov 2020, at 20:16, Richard Sandiford wrote:
>>
>> Olivier Hainque writes:
>>> Hello,
>>>
>>> This patch adds dg-require-effective-target fpic
>>> to an aarch64 specific gcc.dg test using -fPIC,
>>> which helps circumvent a failure we observed while
>>> testing
David Candler writes:
> Hi,
>
> These tests should be skipped for arm targets as the instrinsics
> are only supported on aarch64.
>
> Tested on aarch64 and aarch32
>
> gcc/testsuite/ChangeLog
>
> 2020-11-09 David Candler
>
> * gcc.target/aarch64/advsimd-intrinsics/vqrshrn_high_n.c: Added skip
"Kewen.Lin" writes:
> Hi,
>
> As Lyon pointed out, the newly introduced test case
> gcc.dg/tree-ssa/pr96789.c fails on arm-none-linux-gnueabihf.
> Loop vectorizer is able to vectorize the two loops which
> operate on array tmp with load_lanes feature support. It
> makes dse3 get unexpected inputs
xiezhiheng writes:
>> -Original Message-
>> From: Richard Sandiford [mailto:richard.sandif...@arm.com]
>> Sent: Tuesday, November 3, 2020 9:57 PM
>> To: xiezhiheng
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions
>> emitted at -O3
>>
Aldy Hernandez writes:
>> (actually I can see 3245 ICEs on aarch64)
>>
>> Can you fix it?
>
> Sure can.
>
> Richard, I seem to have incorrectly removed the early exit for varying,
> and that affected the changes you made for poly ints. Is there any
> reason we can't just exit and set varying w
Aldy Hernandez writes:
> On 11/10/20 3:35 PM, Richard Sandiford wrote:
>> Aldy Hernandez writes:
(actually I can see 3245 ICEs on aarch64)
Can you fix it?
>>>
>>> Sure can.
>>>
>>> Richard, I seem to have incorrectly removed the early exit for varying,
>>> and that affected the cha
"Kewen.Lin" writes:
> Hi Richard,
>
> Thanks for the review!
>
> on 2020/11/10 锟斤拷锟斤拷7:31, Richard Sandiford wrote:
>> "Kewen.Lin" writes:
>>> Hi,
>>>
>>> As Lyon pointed out, the newly introduced test case
>>> gcc.dg/tree-ssa/pr96789.c fails on arm-none-linux-gnueabihf.
>>> Loop vectorizer is ab
xiezhiheng writes:
>> -Original Message-
>> From: Richard Sandiford [mailto:richard.sandif...@arm.com]
>> Sent: Tuesday, November 10, 2020 7:54 PM
>> To: xiezhiheng
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions
>> emitted at -O3
>>
[Andrew: cc:ing you in case this affects/helps GCN.]
The vcond code requires the compared vectors and the selected
vectors to have both the same size and the same number of elements
as each other. But the operation makes logical sense even for
different vector sizes. E.g. you could compare two V
This patch adds support for comparing unpacked SVE integer vectors,
such as byte elements stored in the bottom bytes of halfword
containers. It also adds support for selects between unpacked
SVE vectors (both integer and floating-point), since selects and
compares are closely tied via the vcond op
Sudakshina Das writes:
> Apologies for the delay. I have attached another version of the patch.
> I have disabled the test cases for ILP32. This is only because function body
> check
> fails because there is an addition unsigned extension instruction for src
> pointer in
> every test (uxtwx0
Wilco Dijkstra writes:
> Improve the inline memcpy expansion. Use integer load/store for copies <= 24
> bytes
> instead of SIMD. Set the maximum copy to expand to 256 by default, except
> that -Os or
> no Neon expands up to 128 bytes. When using LDP/STP of Q-registers, also use
> Q-register
Alex Coplan writes:
> Hello,
>
> This patch adds a missing not to the SVE2 BCAX (Bitwise clear and
> exclusive or) pattern,
Oops. Even worse is that I'd made the test match the bug in the code. :-(
> fixing the PR. Since SVE doesn't have an unpredicated not instruction,
> we need to use a (vacu
Just after GCC 10 stage 1 closed (oops), I posted a patch to add a new
combine pass. One of its main aims was to allow instructions to move
around where necessary in order to make a combination possible.
It also tried to parallelise instructions that use the same resource.
That pass contained its
I noticed during compatibility testing that clang warns that this
operator won't be implicitly const in C++14 onwards.
gcc/
* vec.h (vnull::operator vec): Make const.
---
gcc/vec.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/vec.h b/gcc/vec.h
index 14d77e87342.
A later patch wants to use the set of global registers as a HARD_REG_SET
rather than a bool/char array. Most other arrays already have a
HARD_REG_SET counterpart, but this one didn't.
gcc/
* hard-reg-set.h (global_reg_set): Declare.
* reginfo.c (global_reg_set): New variable.
noop_move_p currently keeps any instruction that has a REG_EQUAL
note, on the basis that the equality might be useful in future.
But this creates a perverse incentive not to add potentially-useful
REG_EQUAL notes, in case they prevent an instruction from later being
removed as dead.
The condition
A later patch will add more iterator-related utilities. Rather than
putting them all directly in coretypes.h, it seemed better to add a
new header file, here called "iterator-utils.h". This preliminary
patch moves the existing iterator_range class there too.
I used the same copyright date range
This patch adds some more iterator helper classes. They really fall
into two groups, but there didn't seem much value in separating them:
- A later patch has a class hierarchy of the form:
Base
+- Derived1
+- Derived2
A class wants to store an array A1 of Derived1 pointers an
This patch adds a pointer_mux class that provides similar
functionality to:
union { T1 *a; T2 *b; };
...
bool is_b_rather_than_a;
except that the is_b_rather_than_a tag is stored in the low bit
of the pointer. See the comments in the patch for a comparison
between the two approaches
This patch adds an RAII class for managing the lifetimes of objects
on an obstack. See the comments in the patch for more details and
example usage.
gcc/
* obstack-utils.h: New file.
---
gcc/obstack-utils.h | 86 +
1 file changed, 86 insertions
We already have two splay tree implementations: the old C one in
libiberty and a templated reimplementation of it in typed-splay-tree.h.
However, they have some drawbacks:
- They hard-code the assumption that nodes should have both a key and
a value, which isn't always true.
- They use the two-
A later patch wants to be able to pass around subarray views of an
existing array. The standard class to do that is std::span, but it's
a C++20 thing. This patch just adds a cut-down version of it.
The intention is just to provide what's currently needed.
gcc/
* vec.h (array_slice): New
Later patches want to reuse combine's update_cfg_for_uncondjump,
so this patch makes it a public cfgrtl.c function.
gcc/
* cfgrtl.h (update_cfg_for_uncondjump): Declare.
* combine.c (update_cfg_for_uncondjump): Move to...
* cfgrtl.c: ...here.
---
gcc/cfgrtl.c | 47 +++
At the moment, class hierarchies that use is_a are expected
to define specialisations like:
template <>
template <>
inline bool
is_a_helper ::test (symtab_node *p)
{
return p->type == SYMTAB_FUNCTION;
}
But this doesn't scale well to larger hierarchies, because it only
defines ::t
Later patches want to use print_insn_with_notes (printing to
a pretty_printer). This patch exports it from print-rtl.c.
The non-notes version is already public.
gcc/
* print-rtl.h (print_insn_with_notes): Declare.
* print-rtl.c (print_insn_with_notes): Make non-static
---
gcc/pr
verify_changes has a test for whether a particular hard register
is a user-defined register asm. A later patch needs to test the
same thing, so this patch splits it out into a helper.
gcc/
* rtl.h (register_asm_p): Declare.
* recog.c (verify_changes): Split out the test for whethe
One of the recurring warts of RTL is that multiplication by a power
of 2 is represented as a MULT inside a MEM but as an ASHIFT outside
a MEM. It would obviously be better if we didn't have this kind of
context sensitivity, but it would be difficult to remove.
Currently the simplify-rtx.c routine
A later patch wants to be able to use the validate_change machinery
to reduce the XVECLEN of a PARALLEL. This should be more efficient
than allocating a separate PARALLEL at a possibly distant memory
location, especially since the new PARALLEL would be garbage rtl if
the new pattern turns out not
In some cases, it can be convenient to roll back the changes that
have been made by validate_change to see how things looked before,
then reroll the changes. For example, this makes it possible
to defer calculating the cost of an instruction until we know that
the result is actually needed. It ca
This patch adds yet another way of propagating into an instruction and
simplifying the result. (The net effect of the series is to keep the
total number of propagation approaches the same though, since a later
patch removes the fwprop.c routines.)
One of the drawbacks of the validate_replace_* ro
When using validate_change to make a group of changes, you have
to remember to cancel them if something goes wrong. This patch
adds an RAII class to make that easier. See the comments in the
patch for details and examples.
gcc/
* recog.h (insn_change_watermark): New class.
---
gcc/recog
This patch adds some classes for gathering the list of registers
and memory that are read and written by an instruction, along
with various properties about the accesses. In some ways it's
similar to the information that DF collects for registers,
but extended to memory. The main reason for using
This patch adds some documentation to rtl.texi about the SSA form.
It only really describes the high-level structure -- I think for
API-level stuff it's better to rely on function comments instead.
gcc/
* doc/rtl.texi (RTL SSA): New node.
---
gcc/doc/rtl.texi | 787 +++
This patch adds a routine for finding a “simple” SET for a register
definition. See the comment in the patch for details.
gcc/
* rtl.h (simple_regno_set): Declare.
* rtlanal.c (simple_regno_set): New function.
---
gcc/rtl.h | 1 +
gcc/rtlanal.c | 33 +
This patch rewrites fwprop.c to use the RTL SSA framework. It tries
as far as possible to mimic the old behaviour, even in caes where
that doesn't fit naturally with the new framework. I've added ???
comments to mark those places, but I think “fixing” them should
be done separately to make bisect
Sebastian Pop writes:
> Hi,
>
> On Fri, Aug 7, 2020 at 6:18 AM Richard Sandiford wrote:
>>
>> https://gcc.gnu.org/g:5380912a17ea09a8996720fb62b1a70c16c8f9f2
>>
>> commit r9-8794-g5380912a17ea09a8996720fb62b1a70c16c8f9f2
>> Author: Richard Sandiford
>> Date: Fri Aug 7 12:17:37 2020 +0100
>
> co
Hi,
Sorry for the slow reply. Just one minor nit:
HAO CHEN GUI writes:
> diff --git a/gcc/varasm.c b/gcc/varasm.c
> index ea0b59cf44a..40502049b61 100644
> --- a/gcc/varasm.c
> +++ b/gcc/varasm.c
> @@ -727,12 +727,26 @@ switch_to_other_text_partition (void)
>switch_to_section (current_funct
Joel Hutton via Gcc-patches writes:
> Hi all,
>
> This patch adds backend patterns for vec_widen_add, vec_widen_sub on aarch64.
>
> All 3 patches together bootstrapped and regression tested on aarch64.
>
> Ok for stage 1?
>
> gcc/ChangeLog:
>
> 2020-11-12 Joel Hutton
>
> * config/aarch6
Joel Hutton via Gcc-patches writes:
> Hi all,
>
> This patch adds support in the aarch64 backend for the vec_widen_shift
> vect-pattern and makes a minor mid-end fix to support it.
>
> All 3 patches together bootstrapped and regression tested on aarch64.
>
> Ok for stage 1?
>
> gcc/ChangeLog:
>
>
Andrea Corallo via Gcc-patches writes:
> Hi all,
>
> I'd like to propose this patch to make use of RTL predicates into the
> AArch64 back-end where possible.
Nice cleanup :-)
> Bootstrapped and regtested on aarch64-unknown-linux-gnu.
>
> Okay for trunk?
OK, thanks.
Richard
[ There was a discussion on irc about how easy it would be to support
internal functions and tree codes at the same time, so the agreement
was to go for tree codes for now with a promise to convert the
widening-related code to use internal functions for GCC 12. ]
Like Richard said, the new p
Currently we have three vector cost models: cheap, dynamic and
unlimited. -O2 -ftree-vectorize uses “cheap” by default, but that's
still relatively aggressive about peeling and aliasing checks,
and can lead to significant code size growth.
This patch adds an even more conservative choice, which f
acsaw...@linux.ibm.com writes:
> From: Aaron Sawdey
>
> After discussion with Richard Sandiford on IRC, he suggested adding a
> new mode class MODE_OPAQUE to deal with the problems (PR 96791) we had
> been having with POImode/PXImode in powerpc target. This patch is the
> accumulation of changes I
Richard Biener writes:
> On Fri, Nov 13, 2020 at 7:35 PM Richard Sandiford via Gcc-patches
> wrote:
>>
>> Currently we have three vector cost models: cheap, dynamic and
>> unlimited. -O2 -ftree-vectorize uses “cheap” by default, but that's
>> still rela
> +;; A conjucate is a rotation of 180* around the argand plane, or * I.
Hmm, but a complex conjugate is a reflection around the real axis rather
than a rotation. Also, 180 degrees around the Argand plane is * -1
rather than * I. So…
> +(define_int_attr rot_op [(UNSPEC_FCMLS "")
> +
Tamar Christina writes:
>> > +(define_int_attr rot_op [(UNSPEC_FCMLS "")
>> > + (UNSPEC_FCMLS180 "_conj")
>> > + (UNSPEC_FCMLA "")
>> > + (UNSPEC_FCMLA180 "_conj")
>> > + (UNSPEC_FCMUL "")
>> > + (UNSPEC_FCMU
apinski--- via Gcc-patches writes:
> From: Andrew Pinski
>
> The problem here is the aarch64_expand_setmem code did not check
> STRICT_ALIGNMENT if it is creating an overlapping store.
> This patch adds that check and the testcase works.
>
> gcc/ChangeLog:
>
> PR target/101934
> * con
apinski--- via Gcc-patches writes:
> From: Andrew Pinski
>
> This adds MIPS Linux support to gcc.misc-tests/linkage.exp. Basically
> copying what was done for MIPS IRIX and changing the options to be correct.
>
> OK?
>
> gcc/testsuite/ChangeLog:
>
> PR testsuite/51748
> * gcc.misc-te
Richard Biener writes:
> On Tue, Aug 31, 2021 at 11:26 AM Richard Biener via Gcc-patches
> wrote:
>>
>> When doing whole-function SLP we have to make sure the recorded
>> base alignments we compute as the maximum alignment seen for a
>> base anywhere in the function is actually valid at the point
YunQiang Su writes:
> Currently, the enums from define_c_enum and define_enum can only
> has values one by one from 0.
>
> In fact we can support the behaviour just like C, aka like
> (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2]),
> then we can get
> enum mips_isa {
> MIP
Jakub Jelinek writes:
> Hi!
>
> The following testcase is miscompiled on aarch64-linux at -O3 since the
> introduction of WIDEN_MINUS_EXPR.
> The problem is if the inner type (half_type) is unsigned and the result
> type in which the subtraction is performed (type) has precision more than
> twice
Richard Biener writes:
> On Wed, 1 Sep 2021, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Tue, Aug 31, 2021 at 11:26 AM Richard Biener via Gcc-patches
>> > wrote:
>> >>
>> >> When doing whole-function SLP we have to make sure the recorded
>> >> base alignments we compute as the m
Richard Biener writes:
> On Wed, Sep 1, 2021 at 8:28 AM Hongtao Liu wrote:
>>
>> On Tue, Aug 31, 2021 at 7:56 PM Richard Biener
>> wrote:
>> >
>> > On Tue, Aug 31, 2021 at 12:18 PM Hongtao Liu wrote:
>> > >
>> > > On Mon, Aug 30, 2021 at 8:25 PM Richard Biener via Gcc-patches
>> > > wrote:
>>
Richard Biener writes:
> This performs local re-computation of participating scalar stmts
> in BB vectorization subgraphs to allow precise computation of
> liveness of scalar stmts after vectorization and thus precise
> costing. This treats all extern defs as live but continues
> to optimisticall
Hongtao Liu via Gcc-patches writes:
> On Wed, Sep 1, 2021 at 8:52 PM Richard Sandiford
> wrote:
>>
>> Richard Biener writes:
>> > On Wed, Sep 1, 2021 at 8:28 AM Hongtao Liu wrote:
>> >>
>> >> On Tue, Aug 31, 2021 at 7:56 PM Richard Biener
>> >> wrote:
>> >> >
>> >> > On Tue, Aug 31, 2021 at 12
apinski--- via Gcc-patches writes:
> From: Andrew Pinski
>
> After the recent r12-3278-823685221de986a change, the testcase
> gcc.target/aarch64/sve/acle/general-c/type_redef_1.c started
> to ICE as the code was not ready for error_mark_node in the
> type. This fixes that and the testcase now pa
apinski--- via Gcc-patches writes:
> From: Andrew Pinski
>
> This patch adds simple folding of __builtin_aarch64_im_lane_boundsi where
> we are not going to error out. It fixes the problem by the removal
> of the function from the IR.
>
> OK? Bootstrapped and tested on aarch64-linux-gnu with no r
apinski--- via Gcc-patches writes:
> From: Andrew Pinski
>
> I got some ICEs in my latest testsing while running the libstdc++ testsuite.
> I had noticed the problem was connected to types and had just touched the
> builtins code but nothing which could have caused this and I looked for
> some ty
Tamar Christina via Gcc-patches writes:
> diff --git a/gcc/cse.c b/gcc/cse.c
> index
> 330c1e90ce05b8f95b58f24576ec93e10ec55d89..d76e01b6478e22e9dd5760b7c78cecb536d7daef
> 100644
> --- a/gcc/cse.c
> +++ b/gcc/cse.c
> @@ -44,6 +44,7 @@ along with GCC; see the file COPYING3. If not see
> #includ
Tamar Christina writes:
> Hi All,
>
> The following example
>
> void f5(float * restrict z0, float * restrict z1, float *restrict x,
> float * restrict y, float c, int n)
> {
> for (int i = 0; i < n; i++) {
> float a = x[i];
> float b = y[i];
> if (a > b) {
>
Richard Earnshaw via Gcc-patches writes:
> gen_lowpart_general handles forming a lowpart of a MEM by using
> adjust_address to rework and validate a new version of the MEM.
> Do the same for gen_highpart rather than calling simplify_gen_subreg
> for this case.
Looks OK, but what went wrong with t
Richard Earnshaw writes:
> On 13/09/2021 10:38, Richard Sandiford via Gcc-patches wrote:
>> Richard Earnshaw via Gcc-patches writes:
>>> gen_lowpart_general handles forming a lowpart of a MEM by using
>>> adjust_address to rework and validate a new version of t
Kyrylo Tkachov writes:
> Hi all,
>
> In the testcase we generate invalid assembly for an SVE load predicate
> instruction.
> The RTL for the insn is:
> (insn 9 8 10 (set (reg:VNx16BI 68 p0)
> (mem:VNx16BI (plus:DI (mult:DI (reg:DI 1 x1 [93])
> (const_int 8 [0x8]))
>
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