Re: [PATCH] AArch64 SIMD: convert mvn+shrn into mvni+subhn

On 6/13/25 11:22, Alex Coplan wrote: > External email: Use caution opening links or attachments > > > Hi Remi, > > On 12/06/2025 17:02, Richard Sandiford wrote: >> Remi Machet writes: >>> Add an optimization to aarch64 SIMD converting mvn+shrn into mvni+subh

[PATCH v2] AArch64 SIMD: convert mvn+shrn into mvni+subhn

Add an optimization to aarch64 SIMD converting mvn+shrn into mvni+subhn which allows for better optimization when the code is inside a loop by using a constant. Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Remi Machet gcc/ChangeLog: * config/aarch64/aarch64-simd.md

[PATCH] AArch64 SIMD: convert mvn+shrn into mvni+subhn

Add an optimization to aarch64 SIMD converting mvn+shrn into mvni+subhn which allows for better optimization when the code is inside a loop by using a constant. Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Remi Machet gcc/ChangeLog:     * config/aarch64/aarch64-simd.md

Re: [PATCH] AArch64 SIMD: convert mvn+shrn into mvni+subhn

On 6/12/25 12:02, Richard Sandiford wrote: > External email: Use caution opening links or attachments > > > Remi Machet writes: >> Add an optimization to aarch64 SIMD converting mvn+shrn into mvni+subhn >> which >> allows for better optimization when the co

[PATCH v3] AArch64 SIMD: convert mvn+shrn into mvni+subhn

Richard and Alex's suggestions. Sorry for the delay in fixing all suggestions but I was traveling for the past 2 weeks. Remi From 102b7358be9d030f9f518c2accd329d14fe545a3 Mon Sep 17 00:00:00 2001 From: Remi Machet Date: Fri, 13 Jun 2025 18:44:53 + Subject: [PATCH v3] AArch64 SIMD: conver

Re: [PATCH 4/7] aarch64: Use EOR3 for DImode values

On 7/7/25 06:18, Kyrylo Tkachov wrote: > External email: Use caution opening links or attachments > > > Hi all, > > Similar to BCAX, we can use EOR3 for DImode, but we have to be careful > not to force GP<->SIMD moves unnecessarily, so add a splitter for that case. > > So for input: > uint64_t eor3

Re: [PATCH 5/7] aarch64: Use SVE2 NBSL for DImode arguments

On 7/7/25 06:19, Kyrylo Tkachov wrote: External email: Use caution opening links or attachments Hi all, Similar to the BCAX and EOR3 patterns from TARGET_SHA3 we can use the SVE2 NBSL instruction for DImode arugments when they come in SIMD registers. Minor nit: there is a typo in "arugments"

Re: [PATCH 6/7] aarch64: Use SVE2 BSL1N for DImode arguments

On 7/7/25 06:19, Kyrylo Tkachov wrote: > External email: Use caution opening links or attachments > > > Hi all, > > Similar to other patches in this series, this patch adds a splitter > for DImode BSL1N operations, taking care to generate the right code > in the GP regs case. > > Thus for the test

Re: [PATCH] aarch64: Extend HVLA permutations to big-endian

On 7/9/25 11:00, Richard Sandiford wrote: External email: Use caution opening links or attachments Richard Sandiford writes: TARGET_VECTORIZE_VEC_PERM_CONST has code to match the SVE2.1 "hybrid VLA" DUPQ, EXTQ, UZPQ{1,2}, and ZIPQ{1,2} instructions. This ma

Re: [PATCH 7/7] aarch64: Use BSL2N for DImode operands

On 7/7/25 06:20, Kyrylo Tkachov wrote: > External email: Use caution opening links or attachments > > > Hi all, > > The intent of the patch is similar to previous in the series. > Make more use of BSL2N when we have DImode operands in SIMD regs, > but still use the GP instructions when that's wher

Re: [PATCH] aarch64: Support unpacked SVE integer division

On 7/11/25 08:21, Spencer Abson wrote: External email: Use caution opening links or attachments This patch extends the existing patterns for SVE_INT_BINARY_SD to support partial SVE integer modes, including those implement the conditional form. gcc/ChangeLog: * config/aarch64/aarch64-

Re: [PATCH] aarch64: Support unpacked SVE integer division

On 7/14/25 06:35, Spencer Abson wrote: > External email: Use caution opening links or attachments > > > On Fri, Jul 11, 2025 at 02:40:46PM +, Remi Machet wrote: >> On 7/11/25 08:21, Spencer Abson wrote: >> >> External email: Use caution opening links or attachmen

Re: [PATCH] aarch64: Use SVE2 NBSL for vector NOR and NAND for Advanced SIMD modes

On 7/15/25 08:57, Kyrylo Tkachov wrote: > External email: Use caution opening links or attachments > > > Hi all, > > We already have patterns to use the NBSL instruction to implement vector > NOR and NAND operations for SVE types and modes. It is straightforward to > have similar patterns for the

Re: [PATCH 2/2] aarch64: Allow CPU tuning to avoid INS-(W|X)ZR instructions

On 7/18/25 05:39, Kyrylo Tkachov wrote: > External email: Use caution opening links or attachments > > > Hi all, > > For inserting zero into a vector lane we usually use an instruction like: > ins v0.h[2], wzr > > This, however, has not-so-great performance on some CPUs. > On Grace, f