On Thu, Nov 29, 2012 at 2:27 PM, Kyrylo Tkachov wrote:
> Hi all,
> This patch adds an effective target check to the testsuite for ARMv8 NEON
> support. A corresponding add_options procedure is added.
> This is used by the AArch32 NEON intrinsics tests. An entry in the
> documentation is added as w
On 11/29/12 14:27, Kyrylo Tkachov wrote:
Hi all,
This patch adds the intrinsics support for the vrnd intrinsics that are
implemented by the vrint instructions.
The .ml scripts contain the new information and should used to regenerate
the arm_neon.h header file, tests and documentation.
In particu
On 04/24/13 20:02, Lawrence Crowl wrote:
This patch is a consolodation of the hash_table patches to the
cxx-conversion branch for files under gcc/config.
Recipients:
config/arm/arm.c - ni...@redhat.com, ramana.radhakrish...@arm.com
config/ia64/ia64.c - wil...@tuliptree.org, sell...@mips.com
conf
OK for 4.7?
Ok - I did say ok if no fallout in my original review :)
regards
Ramana
Thanks,
Matt
2013-01-04 Matthew Gretton-Dann
Backport from mainline.
2012-11-29 Matthew Gretton-Dann
PR target/54974
* config/arm/arm.md (thumb2_pool_range, pool_r
On 05/13/13 04:15, Kugan wrote:
Hi,
Ping this patch by Chung-Lin.
http://gcc.gnu.org/ml/gcc-patches/2011-05/msg01179.html
This patch allows lr registers to be used in leaf functions for ARM.
There were some concerns about performance regression in thumb2 mode for
CoreMark. However, looking at
Sorry this had dropped off my list of patches to review somehow but
anyway here's a first cut review.
On Thu, Mar 21, 2013 at 6:58 AM, Zhenqiang Chen
wrote:
> Hi,
>
> When shrink-wrap is enabled, the "returns" from simple-return path and
> normal return path can be merged. The code is like:
>
>
What happens to the *arm_simple_return pattern that already exists in
the backend ? Can you rebase to trunk ?
Ramana
On Wed, Apr 3, 2013 at 7:50 AM, Zhenqiang Chen
wrote:
> On 2 April 2013 17:55, Ramana Radhakrishnan wrote:
>> On Thu, Mar 21, 2013 at 7:03 AM, Zhenqiang Chen
>>
> If so is the backport OK for 4.8?
I am happy for it to go to 4.8 provided it's tested on 4.8 and the
release managers don't object.
Ramana
>
> Thanks,
>
> Matt
>
>
> --
> Matthew Gretton-Dann
> Toolchain Working Group, Linaro
unction_ok_for_sibcall): Allow tailcalling
without decls.
2013-05-15 Ramana Radhakrishnan
PR target/19599
* gcc.target/arm/pr40887.c: Adjust testcase.
* gcc.target/arm/pr19599.c: New test.commit 5d0e570066009d361181be26e8ba858139ee5b8e
Author: Ramana Radhakrishnan
Da
My patch for PR19599 yesterday had a problem with arm-none-eabi builds.
I had missed a null pointer check of decl in an AAPCS only
configuration. Now applied as obvious.
regards
Ramana
2013-05-16 Ramana Radhakrishnan
PR target/19599
* config/arm/arm.c
On 05/16/13 07:27, Zhenqiang Chen wrote:
On 15 May 2013 06:31, Ramana Radhakrishnan wrote:
Sorry this had dropped off my list of patches to review somehow but
anyway here's a first cut review.
On Thu, Mar 21, 2013 at 6:58 AM, Zhenqiang Chen
wrote:
Hi,
When shrink-wrap is enabled
On 05/16/13 07:46, Zhenqiang Chen wrote:
On 15 May 2013 06:36, Ramana Radhakrishnan wrote:
What happens to the *arm_simple_return pattern that already exists in
the backend ? Can you rebase to trunk ?
The *arm_simple_return is the same as "simple_return" used by
shrink-wrap. *arm_
On Fri, May 17, 2013 at 9:12 PM, Richard Henderson wrote:
> On 05/15/2013 04:50 AM, Ramana Radhakrishnan wrote:
>>/* Cannot tail-call to long calls, since these are out of range of
>> a branch instruction. */
>> - if (arm_is_long_call_p (decl))
>> + if
On 05/22/13 11:31, Christian Bruel wrote:
Hello,
arm_dwarf_register_span converts regno to a dbx register number while
building the PARALLEL rtx. But since
http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01131.html this information
is centralized in DBX_REGISTER_NUMBER that will be called when
proc
This caused:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57372
A fix is forthcoming - this is a dup of PR57340.
Ramana
--
Roman
nfigurations with A9
where this problem was also observed on a version prior to breakages
from PR57351.
Applied.
regards
Ramana
2013-05-22 Ramana Radhakrishnan
PR target/19599
PR target/57340
* config/arm/arm.c (any_sibcall_uses_r3): Rename to ..
(any_sibcall
On 05/24/13 13:26, Greta Yorsh wrote:
This patch (trunk r198547)
http://gcc.gnu.org/ml/gcc-patches/2013-05/msg00061.html
fixes an ICE in gcc 4.8:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56732
Ok to backport to 4.8 branch?
Ok.
regards
Ramana
Thanks,
Greta
gcc/ChangeLog
2013-05-02 Gr
Hi,
This fixes up some of the fallout in the testsuite for ARM with the
DATA_ABI_ALIGNMENT changes recently.
Applied to trunk.
regards
Ramana
2013-06-12 Ramana Radhakrishnan
* gcc.target/arm/unaligned-memcpy-4.c (src, dst): Initialize
to ensure alignment
On Mon, Aug 25, 2014 at 11:32 AM, Tony Wang wrote:
> Hi all,
>
> The bug is reported at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56846,
> and it’s about the problem that
> when exception handler is involved in the function, then _Unwind_Backtrace
> function will run into deadloop on
> arm ta
On Thu, Sep 4, 2014 at 3:21 AM, Tony Wang wrote:
> Hi there,
>
> This is a test case clean up patch, because orr/eor instruction for thumb1
> has only two variant:
>
> ORRS ,
> ORR ,
> No is available for thumb1 encoding, so test case
> xordi3-opt.c/iordi3-opt.c is invalid for thumb1
> target
On Sun, Aug 31, 2014 at 4:45 PM, Gerald Pfeifer wrote:
> On Wed, 5 Feb 2014, James Greenhalgh wrote:
>> As far as I know the behaviour of this flag has always been this way.
>> So is this also OK to backport to release branches?
>
> 2014-02-05 James Greenhalgh
>
> PR target/59718
>
On Mon, Aug 18, 2014 at 11:31 AM, Jiong Wang wrote:
> this patch enable auto-vectorization for copysignf by using vector
> bit selection instruction on arm32 when neon available.
>
> for a simple testcase:
>
> for (i = 0; i < N; i++)
> r[i] = __builtin_copysignf (a[i], b[i]);
>
>
> assuming
On Tue, Aug 19, 2014 at 4:04 PM, Kyrill Tkachov wrote:
> Hi all,
>
> This patch series converts the arm backend to output unified assembly syntax
> for the VFP instructions.
> This makes it more readable since most UAL mnemonics also include various
> type suffixes such as .f32 and .f64 that quick
On Tue, Aug 19, 2014 at 4:22 PM, Kyrill Tkachov wrote:
> Hi all,
>
> In this patch the move patterns are updated.
> For the fconst case where the constant is encoded in a decimal
> representation before going into the immediate field of the assembly
> instruction UAL syntax allows for the real ope
On Tue, Aug 19, 2014 at 4:22 PM, Kyrill Tkachov wrote:
> Hi all,
>
> Nothing too controversial here, convert the concerned patterns to UAL.
> The size of the data types in the operation is expressed in the .f32 or
> .f64 suffix.
>
> Ok for trunk?
Ok - in an ideal world I'd have just done these wi
On Tue, Aug 19, 2014 at 4:04 PM, Kyrill Tkachov wrote:
> Hi all,
>
> This patch switches over the FP mul+add, mul+neg+add etc patterns. Mixing
> some of the mnemonics up is a danger but the ARM ARM has a handy section
> that maps each mnemonic to its UAL equivalent.
>
> Ok for trunk?
>
Ok this is
On Tue, Aug 19, 2014 at 4:04 PM, Kyrill Tkachov wrote:
> Hi all,
>
> These are the fp<->fp and int<->fp convert patterns. IMHO these are much
> more readable than the pre-UAL ones because they use two suffixes to
> indicate which data types are being converted to and from.
>
> Ok for trunk?
>
> Th
On Tue, Aug 19, 2014 at 4:04 PM, Kyrill Tkachov wrote:
> Hi all,
>
> The sqrt and floating point compare patterns.
> For the case when we compare with floating-point 0 the ARM ARM uses the
> syntax 'vcmp {s,d}, #0.0'
> but current gas has a bug and doesn't accept that form, only 'vcmp {s,d},
> #0'
On Tue, Aug 19, 2014 at 4:04 PM, Kyrill Tkachov wrote:
> Hi all,
>
> The ARM ARM explicitly says that fmstat is translated into 'vmrs APSR_nzcvm,
> FPSCR' in UAL syntax so this patch does that.
>
> Ok for trunk?
Ok
Ramana
>
> Thanks,
> Kyrill
>
> 2014-08-19 Kyrylo Tkachov
>
> * config/arm
On Tue, Aug 19, 2014 at 4:04 PM, Kyrill Tkachov wrote:
> Hi all,
>
> This patch updates some FP load/store multiple patterns and in the
> vfp_output_vstmd case when the instruction is used as a push to sp it now
> emits a vpush mnemonic instead of vstmdb.
>
> Ok for trunk?
Ok - thanks,
Ramana
>
On Mon, Sep 1, 2014 at 4:30 AM, Kito Cheng wrote:
> Hi all:
>
> In arm-*-elf target some variable will missing size directive,
>
> for example:
>
> foo.c:
>
> void foo (void) {
> static char bufbuf[8];
> }
>
> $ arm-none-eabi-gcc ./foo.c -S -o -
>
> ...
> .align 2
> bufbuf.4078:
> .space 8
Th
On Wed, Sep 10, 2014 at 9:16 AM, Bin.Cheng wrote:
> On Tue, Sep 9, 2014 at 6:49 PM, Richard Earnshaw wrote:
>> On 04/09/14 07:08, Bin Cheng wrote:
>>> @@ -1872,7 +1892,9 @@ const struct tune_params arm_cortex_a53_tune =
>>>{true, true}, /* Prefer non short
2014-04-10 Ramana Radhakrishnan
PR debug/60655
* config/arm/arm.c (TARGET_CONST_NOT_OK_FOR_DEBUG_P): Define
(arm_const_not_ok_for_debug_p): Reject MINUS with SYM_REF's
ameliorating the cases where it can be.
can I suppose be reverted too.
That was a
On 09/09/14 16:14, Kyrill Tkachov wrote:
Hi all,
As Christophe mentioned at
https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00202.html
These tests fail on big-endian. The reason is that the input is not
aligned to 128 bit forcing the use of a movmisalign which we don't
support on big-endian.
A
On 10/09/14 15:38, Jonathan Wakely wrote:
On 10/09/14 15:41 +0800, Tony Wang wrote:
-Original Message-
From: Jonathan Wakely [mailto:jwak...@redhat.com]
Sent: Tuesday, September 09, 2014 6:40 PM
To: Tony Wang
Cc: Ramana Radhakrishnan; gcc-patches; libstd...@gcc.gnu.org
Subject: Re
On 12/09/14 11:13, Richard Earnshaw wrote:
On 09/09/14 16:14, Kyrill Tkachov wrote:
Hi all,
As Christophe mentioned at
https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00202.html
These tests fail on big-endian. The reason is that the input is not
aligned to 128 bit forcing the use of a movmisali
On Wed, Sep 10, 2014 at 6:30 AM, Zhenqiang Chen wrote:
> Hi,
>
> Currently most thumb1_size_rtx_costs are "guessed" from performance view,
> not size.
>
> The patch adjusts some of them according the instruction patterns defined in
> thumb1.md. It also replaces several hard coded "4" to COSTS_N_IN
On Wed, Sep 24, 2014 at 6:17 AM, Terry Guo wrote:
> Hi there,
>
> The attached patch intends to provide option support to newly announced core
> Cortex-M7 and related FPU:
> http://www.arm.com/about/newsroom/arm-supercharges-mcu-market-with-high-perf
> ormance-cortex-m7-processor.php
> http://www.
On Wed, Oct 1, 2014 at 10:03 AM, Christian Bruel wrote:
> Hi Ramana,
>
> Your patch https://gcc.gnu.org/ml/gcc-patches/2012-02/msg01492.html
> seems to have not been applied for 4.10. Are there any stoppers or is it
> an omission ?
Short answer, no, not an omission. It could not be made to work
Hi,
I've been digging into why on AArch64 we generate pretty bad code
for the following testcase.
void g2(float, float, float, float, float, float, float, float);
void f2a(void)
{
float x0 = 1.0, x1 = 2.0, x2 = 3.0, x3 = 4.0, x4 = 5.0, x5 = 6.0, x6
= 7.0, x7 = 8.0;
float x8 = 0.5, x
On 06/17/13 10:24, Kyrylo Tkachov wrote:
Hi all,
This arm testsuite patch initialises an array in the
unaligned-memcpy-2.c test to ensure alignment, making the test pass.
This is similar to the patch
http://gcc.gnu.org/ml/gcc-patches/2013-06/msg00683.html.
Ok for trunk?
Ok - thanks for catchi
On 06/18/13 09:50, Zhenqiang Chen wrote:
Hi,
During expand, function vcond inverses some CMP, e.g.
a LE b -> b GE a
But if "b" is "CONST0_RTX", "b GE a" will be an illegal insn.
(insn 933 932 934 113 (set (reg:V4SI 1027)
(unspec:V4SI [
(const_vector:V4SI [
Thanks,
Julian
ChangeLog
gcc/
* config/arm/arm.c (neon_vector_mem_operand): Add strict argument.
Permit virtual register pre-reload if !strict.
(coproc_secondary_reload_class): Adjust for neon_vector_mem_operand
change.
* config/arm/arm-protos.h (neon_vector_m
On Mon, Jun 17, 2013 at 12:18 PM, Greta Yorsh wrote:
> This patch makes the following changes:
> * Define MAX_CONDITIONAL_EXECUTE in arm backend using max_insns_skipped,
> which is set based on the current tune.
> * Update max_insns_skipped for Cortex-A15 tune to be 2 (instead of 5).
> * Use max_i
On 06/26/13 09:37, Tom de Vries wrote:
On 18/10/12 18:48, Ramana Radhakrishnan wrote:
+(define_insn_reservation "cortex_a15_vfp_adds_subs" 6
+ (and (eq_attr "tune" "cortexa15")
+ (eq_attr "type" "fadds"))
+ "ca15_issue1,ca15_cx_vfp&
Ok.
Ramana
On Mon, Jun 10, 2013 at 11:52 AM, Kyrylo Tkachov wrote:
> Hi all,
>
> This patch makes the changes to the various floating point patterns in
> vfp.md. Since pretty much all floating point instruction are always
> encoded in 32 bits, they cannot be used inside an IT block by the
> -mre
> 2013-06-18 Kyrylo Tkachov
>
> * config/arm/arm.md (arm_mulsi3_v6): Add alternative for 16-bit
> encoding.
> (mulsi3addsi_v6): Disable predicable variant for
> arm_restrict_it.
> (mulsi3subsi): Likewise.
> (mulsidi3adddi): Likewise.
> (mulsidi3_v6): Likew
On Thu, Jun 20, 2013 at 2:38 PM, Kyrylo Tkachov wrote:
> Hi all,
>
> This patch adjusts the mov* patterns in the arm backend to generate code
> appropriate for -mrestrict-it. The rules are:
> moves between any two registers are allowed to be in IT blocks. mov immediate
> are allowed if the immedia
On 06/28/13 11:00, Terry Guo wrote:
Ping.
BR,
Terry
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
ow...@gcc.gnu.org] On Behalf Of Terry Guo
Sent: Monday, June 03, 2013 6:02 PM
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw; Ramana Radhakrishnan
Subject
On 06/28/13 11:00, Terry Guo wrote:
Ping.
BR,
Terry
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
ow...@gcc.gnu.org] On Behalf Of Terry Guo
Sent: Monday, June 03, 2013 6:02 PM
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw; Ramana Radhakrishnan
Subject
t arm_neon ?
regards
Ramana
On Wed, Jun 26, 2013 at 9:01 AM, Zhenqiang Chen
wrote:
> On 18 June 2013 17:41, Ramana Radhakrishnan wrote:
>> On 06/18/13 09:50, Zhenqiang Chen wrote:
>>>
>>> Hi,
>>>
>>> During expand, function vcond inverses some CMP,
On 07/17/13 09:53, Yvan Roux wrote:
Hi,
this patch fixes the issue described in PR57909, where we have an ICE
during the internal memcpy, as some UNSPEC_UNALIGNED insns are emitted
even if -mno-unaligned-access flag is passed. See the link below for a
more detailled description:
http://gcc.gnu.
OK for trunk?
This is OK.
Ramana
On Tue, Jul 16, 2013 at 2:15 PM, Sofiane Naci wrote:
> Hi,
>
> This patch is the part of the ongoing work of ARM instruction classification
> cleanup.
>
> This patch deletes redundant values "mrs", "msr", "xtab" and "sat" from the
> "insn" attribute, and moves the "clz" value to the "type" attribu
On 07/19/13 15:10, Sofiane Naci wrote:
Hi,
This patch is part of the ongoing work of ARM instruction classification
cleanup.
This patch deletes the "insn" attribute and moves the MOV/MVN instruction
classification to the "type" attribute, where it is split into several types
for a finer-grained
On 07/22/13 10:52, Sofiane Naci wrote:
Oops sorry.
Patch attached now.
Ok
Thanks,
Ramana
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
ow...@gcc.gnu.org] On Behalf Of Ramana Radhakrishnan
Sent: 22 July 2013 10:26
To: gcc-patches@gcc.gnu.org
Subject
LEGITIMATE_PIC_OPERAND_P
(operand)))
win = 1;
break;
and our definition of LEGITIMATE_PIC_OPERAND_P doesn't allow a symbol
ref. So be it.
Regression tested on arm-none-linux-gnueabi arm / thumb multilibs v7-a ,
bootstrapped and checked it all works fine. A
On Thu, Jul 25, 2013 at 12:40 PM, Bernd Edlinger
wrote:
> Hi Ramana,
>
> why did you leave the space before the bx?
> this ends up in the .s file making it look ugly..
Ooops - thanks for noticing - wasn't deliberate - fixed as obvious with this.
Ramana
Index: gcc/config/arm/arm.md
=
On 07/29/13 11:05, Mikael Pettersson wrote:
Ramana Radhakrishnan writes:
> Hi,
>
> This fixes up the issues with PR target/19599 and the issues we've had
> around it.
...
> 2013-07-25 Ramana Radhakrishnan
>
> PR target/19599
On 08/01/13 11:46, Vidya Praveen wrote:
Ping!
On Tue, Jul 23, 2013 at 10:21:52AM +0100, Vidya Praveen wrote:
Hello
gcc.dg/vect/vect-iv-5.c XPASSes for arm-*-* since gcc.dg/vect/*.c tests are
always run with -ffast-math for arm-*-*. This patch makes xfail conditional
for this test by adding eff
On 08/07/13 08:10, Bernd Edlinger wrote:
Hello,
in the discussion about the PR middle-end/57748 it became obvious that the ARM
target architecture should define a value for MALLOC_ABI_ALIGNMENT, because
otherwise the default is simply word aligned, which causes sub-optimal code, at
least for
On 08/01/13 03:04, Zhenqiang Chen wrote:
Thank you all for the comments. The patch is updated as:
1) Revert it to the original one.
2) For the testcase, replace the dg-options with
/* { dg-do compile } */
/* { dg-require-effective-target arm_neon } */
/* { dg-add-options arm_neon } */
/* { dg-opt
On 08/06/13 22:39, Benjamin De Kosnik wrote:
+# Filter out unsupported systems.
+case "${target}" in
+ x86_64-*-linux* | i?86-*-linux*)
+ VTV_SUPPORTED=yes
+ ;;
+ powerpc*-*-linux*)
+ ;;
+ sparc*-*-linux*)
+ ;;
+ arm*-*-linux*)
+ ;;
What about powerpc, sparc and arm? Why are they mention
On 08/08/13 15:44, Kyrylo Tkachov wrote:
Hi all,
The recently added gcc.target/arm/pr58041.c test exposed a bug in the backend.
When compiling for NEON and with -mno-unaligned-access we end up generating
the vld1.64 and vst1.64 instructions instead of doing the accesses one byte at
a time like -
arm*-*-linux* is broken currently for what looks like the same reasons as
the powerpc port.
Have you tried Benjamin Kosnik's patch? Does it fix the problem?
I hadn't but that seems to have fixed the issue. Thanks.
I spent some time this morning looking into what it would take to enabl
On 08/09/13 11:01, Julian Brown wrote:
On Thu, 8 Aug 2013 15:44:17 +0100
Kyrylo Tkachov wrote:
Hi all,
The recently added gcc.target/arm/pr58041.c test exposed a bug in the
backend. When compiling for NEON and with -mno-unaligned-access we
end up generating the vld1.64 and vst1.64 instruction
On 08/13/13 15:57, Kyrylo Tkachov wrote:
On 08/09/13 11:01, Julian Brown wrote:
On Thu, 8 Aug 2013 15:44:17 +0100
Kyrylo Tkachov wrote:
Hi all,
The recently added gcc.target/arm/pr58041.c test exposed a bug in the
backend. When compiling for NEON and with -mno-unaligned-access we
end up gen
qemu. Applied.
Thanks,
Ramana
2013-02-28 Ramana Radhakrishnan
* config/arm/arm.c (arm_output_mi_thunk): Call final_start_function and
final_end_function.
---
gcc/config/arm/arm.c |4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
On Wed, Mar 6, 2013 at 9:07 AM, Jakub Jelinek wrote:
> Hi!
>
> https://bugzilla.redhat.com/show_bug.cgi?id=910926
> reports that plugins aren't usable on arm, because arm-cores.def isn't
> installed into the plugins directory. arm-cores.def can't be included in
> tm_file list, because we don't wa
On 03/18/13 19:20, Meador Inge wrote:
Ping.
On 03/05/2013 12:15 PM, Meador Inge wrote:
Hi All,
This patch fixes a minor annoyance that causes backtraces to disappear
inside of aeabi_ldivmod and aeabi_uldivmod due to the lack of appropriate
DWARF information. I fixed the problem by adding the
On 03/18/13 12:09, Kyrylo Tkachov wrote:
Hi all,
Given code:
#define MAX(a, b) (a > b ? a : b)
void foo (int ilast, float* w, float* w2)
{
int i;
for (i = 0; i < ilast; ++i)
{
w[i] = MAX (0.0f, w2[i]);
}
}
compiled with
-O1 -funsafe-math-optimizations -ftree-vectorize -mfpu=ne
On Mon, Feb 25, 2013 at 2:23 AM, Terry Guo wrote:
> Hi,
>
> This patch is to enable GCC to accept new command line option
> -mcpu=cortex-r7. Is it OK to trunk?
>
> BR,
> Terry
>
> 2013-02-25 Terry Guo
>
> * config/arm/arm-cores.def: Added core cortex-r7.
> * config/arm/arm-tune.
On Wed, Feb 13, 2013 at 1:35 PM, Greta Yorsh wrote:
> This patch defines peephole2 patterns that merge two individual LDR
> instructions into LDRD instruction (resp. STR into STRD) whenever possible
> using the following transformations:
> * reorder two memory accesses,
> * rename registers when s
On Mon, Feb 18, 2013 at 6:38 PM, Greta Yorsh wrote:
> Convert define_insn into define_insn_and_split for various patterns that
> output multiple assembly instructions.
>
> It appears that preparation statements in define_insn_and_split sometimes
> are called with which_alternative set to -1 even a
On Mon, Feb 18, 2013 at 6:40 PM, Greta Yorsh wrote:
> This patch adds patterns to handle negation of an extended 32-bit value more
> efficiently.
>
> For example,
>
> (set (reg:DI r0) (neg:DI (sign_extend:DI (reg:SI r0)))
>
> The compiler currently generates
> mov r1, r0, asr #31
>
On Mon, Feb 18, 2013 at 6:42 PM, Greta Yorsh wrote:
> Convert define_insn into define_insn_and_split for various DImode shift
> operations that output multiple assembly instructions.
>
> This patch also adds a new pattern for RRX using a new UNSPEC. This pattern
> matches RTL insns emitted by arm_
On Wed, Mar 20, 2013 at 2:43 AM, Xinyu Qi wrote:
>>At 2013-01-22 19:58:43,"Ramana Radhakrishnan" wrote:>
>> > On 01/22/13 09:21, Xinyu Qi wrote:
>> > > Ping,
>> > >
>> > > Fix ChangeLog
>> >
>> > The ChangeLog for
On Tue, Mar 19, 2013 at 9:15 AM, Zhenqiang Chen wrote:
> Hi,
>
> libstdc++ configure will check "shl_load". If shared library is disabled in
> gcc and uclibc configure, the libstdc++ configure will fail for options like
> -mthumb -march=armv7-r. The fail logs like:
>
> .../libgcc.a(unwind-arm.o):
On Mon, Feb 18, 2013 at 6:44 PM, Greta Yorsh wrote:
> Convert define_insn into define_insn_and_split for various min and max
> patterns that output multiple assembly instructions. Use movsicc to emit
> RTL. A separate patch will split movsicc.
>
> gcc/
>
> 2013-02-14 Greta Yorsh
>
> * c
On 04/02/13 10:40, Xinyu Qi wrote:
Hi,
According to Vladimir Makarov's analysis, the root cause of PR target/54338
is that ALL_REGS doesn't contain IWMMXT_GR_REGS in REG_CLASS_CONTENTS.
It seems there is no reason to exclude the IWMMXT_GR_REGS from ALL_REGS as
IWMMXT_GR_REGS are the real
On Thu, Mar 21, 2013 at 7:03 AM, Zhenqiang Chen
wrote:
> Hi,
>
> The patch is to enable shrink-wrap for TARGET_ARM and TARGET_THUMB2.
>
> Bootstrapped and no make check regression.
> All previous Linaro shrink-wrap bugs (http://goo.gl/6fGg5) are verified.
>
> Is it OK?
The tests should be part of
On Thu, Mar 21, 2013 at 6:09 PM, Kyrylo Tkachov wrote:
> Hi all,
>
> This patch adds a splitter variant of the minmax_arithsi pattern for when
> the operator
> is non-commutative (MINUS) and the ordering of the operands is not
> canonical.
>
> That is, it will trigger for:
> #define MAX(a, b) (a >
for -march=armv8-a is now the Cortex-A53 rather than
the A15.
Applied to trunk.
regards
Ramana
2013-04-02 Ian Caulfield
Ramana Radhakrishnan
* config/arm/arm-arches.def (armv8-a): Default to cortex-a53.
* config/arm/t-arm (MD_INCLUDES): Depend on cor
On 04/03/13 16:07, Kyrylo Tkachov wrote:
Hi all,
This patch fixes an ICE that we encounter when building gcc on arm targets.
The jump table reorganisation exposed a bug in the backend.
This fixes it
by using next_active_insn instead of next_real_insn when looking for the
diff vector in the jump
On Wed, Apr 3, 2013 at 4:07 PM, Kyrylo Tkachov wrote:
>
> Hi all,
>
> This patch fixes a PR that was exposed in the recent jump table
> reorganisation.
> We should use next_active_insn instead of next_real_insn in the jump table
> handling code.
>
> This fixes the incorrect assembly generation tha
On 04/04/13 08:46, Richard Biener wrote:
On Wed, 3 Apr 2013, Matthew Gretton-Dann wrote:
Would it be possible for this patch and the others Kyrylo has recently done
for the new ARMv8 AArch32 instructions to be backported to 4.8?
In particular I'm refering to:
http://gcc.gnu.org/ml/gcc-patches
On 04/04/13 11:55, Kyrylo Tkachov wrote:
Hi all,
Can I backport the patch at
http://gcc.gnu.org/ml/gcc-patches/2013-03/msg00652.html
to 4.8?
It fixes PR 56720 on arm-*-* targets.
The trunk commits for this are r197040 and r197041.
It applies cleanly to 4.8 and regtests cleanly on arm-none-eab
Hi,
This backports the fix for PR48308 something that's slipped through the
cracks. I wrote the backport and then noticed that Mikael had a similar
solution - the only difference being around this guarded for HAVE_cc0
targets.
Tested cross arm-none-linux-gnueabi - no regressions.
Bootstrapp
On 04/04/13 14:16, Jakub Jelinek wrote:
On Thu, Apr 04, 2013 at 02:11:39PM +0100, Ramana Radhakrishnan wrote:
This backports the fix for PR48308 something that's slipped through
the cracks. I wrote the backport and then noticed that Mikael had a
similar solution - the only difference
Joseph pointed out the cortex-a53 wasn't documented in invoke.texi.
Fixed thusly.
Ramana
2013-04-05 Ramana Radhakrishnan
* doc/invoke.texi (ARM Options): Document cortex-a53 support.Index: gcc/doc/invoke
On 04/05/13 14:06, Kyrylo Tkachov wrote:
Hi all,
With r197491 I added testsuite support for vectorisation of rounding
functions on ARMv8 NEON, but the options set up
for vect.exp results in the testsuite trying to test all the vect tests with
ARMv8 NEON which does not work on
ARMv7 targets and s
On 04/05/13 15:55, Kyrylo Tkachov wrote:
Hi all
This patch fixes a warning in arm.c about a comparison between signed and
unsigned integers.
This is usually harmless, but during bootstrap we compile with -Werror and
this turns
into an error. The fix is a one-liner.
Tested to make sure warning g
On 04/05/13 16:26, Greta Yorsh wrote:
-Original Message-
From: Richard Earnshaw
Sent: 22 February 2013 16:30
To: Greta Yorsh
Cc: GCC Patches; Ramana Radhakrishnan; ni...@redhat.com;
p...@codesourcery.com
Subject: Re: [PATCH,ARM][1/n] New patterns for subtract with carry
On 18/02/13 18
On 03/15/13 18:16, Julian Brown wrote:
Hi,
At present, the libcall helpers implementing atomic operations
(__sync_val_compare_and_swap_X) for char and short types suffer from
a type mismatch. This is leading to test failures, i.e.:
FAIL: gcc.dg/atomic-compare-exchange-1.c execution test
FAIL: g
On 04/05/13 15:44, Kyrylo Tkachov wrote:
- -Original Message-
From: Ramana Radhakrishnan
Sent: 05 April 2013 15:06
To: Kyrylo Tkachov
Cc: gcc-patches@gcc.gnu.org; mikest...@comcast.net
Subject: Re: [PATCH][ARM][testsuite] Fix testsuite options for testing
rounding vectorisation on ARMv8
ChangeLog
2013-04-02 Xinyu Qi
PR target/54338
* config/arm/arm.h (REG_CLASS_CONTENTS): Include IWMMXT_GR_REGS in
ALL_REGS.
Thanks,
Xinyu
Thanks now applied to trunk.
For the future please consider creating patches at the top level
directory. Makes it easier for applic
On 12/20/12 09:53, Joey Ye wrote:
Current GCC thumb1 has an annoying problem that always assuming far branch.
So it forces to save lr, even when unnecessarily. The most extreme case
complained by partner is:
// compiled with "-mthumb -mcpu=cortex-m0 -Os".
void foo() { for (;;); }
=>
foo:
On Thu, Apr 24, 2014 at 5:50 PM, Kyrill Tkachov wrote:
> On 24/04/14 17:46, Ryan Mansfield wrote:
>>
>> On 14-04-24 12:12 PM, Kyrill Tkachov wrote:
>>>
>>> On 24/04/14 14:44, Ryan Mansfield wrote:
On 14-04-23 11:38 AM, Kyrill Tkachov wrote:
>
> http://gcc.gnu.org/ml/gcc-patches/2
abihf (Thumb-2) on qemu.
>
> OK to backport to 4.8 and 4.7?
Ok by me but give 24 "working" hours for an RM to object.
Ramana
>
> On 7 April 2014 16:02, Charles Baylis wrote:
>> On 4 April 2014 15:50, Ramana Radhakrishnan
>> wrote:
>>> Additionally the t
")
+ (unspec_volatile:SI [(const_int 0)] VUNSPEC_LDFPSCR))]
+ "TARGET_VFP"
+ "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @LDFPSCR"
+ [(set_attr "type" "mrs")])
+
+
;; Unimplemented insns:
;; fldm*
;; fstm*
Please respin.
Ramana
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
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