On Tue, Oct 8, 2019 at 4:21 PM Andre Vieira (lists)
wrote:
>
> Hi,
>
> This patch implements the TARGET_HOOK_SANITIZE_CLONE_ATTRIBUTES for the
> arm backend to remove the 'cmse_nonsecure_entry' attribute from cmse.
>
> Bootstrapped the series on x86_64 and built arm-none-eabi, running the
> cmse t
On Fri, Oct 11, 2019 at 5:17 PM Wilco Dijkstra wrote:
>
> Hi Ramana,
>
> >On Mon, Sep 9, 2019 at 6:03 PM Wilco Dijkstra wrote:
> >>
> >> Currently arm_legitimize_address doesn't handle Thumb-2 at all, resulting
> >> in
> >> inefficient code. Since Thumb-2 supports similar address offsets use th
On Fri, Oct 11, 2019 at 3:52 PM Wilco Dijkstra wrote:
>
> Hi Ramana,
>
> > My only question would be whether it's more suitable to use
> > optimize_function_for_size_p(cfun) instead as IIRC that gives us a
> > chance with lto rather than the global optimize_size.
>
> Yes that is even better and th
On Fri, Oct 11, 2019 at 6:19 PM Wilco Dijkstra wrote:
>
> Hi Ramana,
>
> > Can you see what happens with the Cortex-A8 or Cortex-A9 schedulers to
> > spread the range across some v7-a CPUs as well ? While they aren't that
> > popular today I
> > would suggest you look at them because the defaults
On Fri, Oct 11, 2019 at 10:42 PM Wilco Dijkstra wrote:
>
> Hi,
>
> > the defaults for v7-a are still to use the
> > Cortex-A8 scheduler
>
> I missed that part, but that's a serious bug btw - Cortex-A8 is 15 years old
> now so
> way beyond obsolete. Even Cortex-A53 is ancient now, but it has an
>
> Patch bootstrapped and regression tested on arm-none-linux-gnueabihf,
> however, on my native Aarch32 setup the test times out when run as part
> of a big "make check-gcc" regression, but not when run individually.
>
> 2019-10-11 Stamatis Markianos-Wright
>
> * config/arm/arm.md: U
On Fri, Oct 18, 2019 at 8:49 PM Richard Earnshaw
wrote:
>
>
> This series of patches rewrites all the DImode arithmetic patterns for
> the Arm backend when compiling for Arm or Thumb2 to split the
> operations during expand (the thumb1 code is unchanged and cannot
> benefit from early splitting as
On Fri, Jan 27, 2023 at 2:44 PM Andrea Corallo via Gcc-patches
wrote:
>
> gcc/
>
> * config/arm/arm.cc (arm_valid_target_attribute_rec): Add ARM function
> attribute 'branch-protection' and parse its options.
> * doc/extend.texi: Document ARM Function attribute
> 'branch-p
be in gcc/config/arm but its possibly ok given the usage
statistics.
Reviewed-by: Ramana Radhakrishnan.
regards
Ramana
>
> --
> Evandro Menezes
>
>
>
> gcc/ChangeLog:
>
> * config/a
Ping x 2
Ramana
On Thu, 17 Nov 2022, 20:15 Ramana Radhakrishnan,
wrote:
> On Fri, Nov 11, 2022 at 9:50 PM Ramana Radhakrishnan
> wrote:
> >
> > On Thu, Nov 10, 2022 at 7:46 PM Ramana Radhakrishnan
> > wrote:
> > >
> > > On Thu, Nov 10, 202
On Fri, Aug 10, 2018 at 11:09 AM, Yvan Roux wrote:
> Hi,
>
> This patch adds Linaro version string and release macros to ARM GCC 8
> vendor branch.
>
> Ok to commit?
>
Ok if no regressions. (I'm assuming you've built and eyeballed that
the pre-processor macros are being produced). (I have a patc
On Fri, Aug 10, 2018 at 3:35 PM, Yvan Roux wrote:
> On Fri, 10 Aug 2018 at 14:31, Yvan Roux wrote:
>>
>> On Fri, 10 Aug 2018 at 13:45, Ramana Radhakrishnan
>> wrote:
>> >
>> > On Fri, Aug 10, 2018 at 11:09 AM, Yvan Roux wrote:
>> > > Hi,
>
On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška wrote:
> PING^1
>
> On 07/24/2018 02:05 PM, Martin Liška wrote:
>> Hi.
>>
>> I'm sending updated version of the patch. It comes up with a new target
>> common hook
>> that provide option completion list. It's used both in --help=target and
>> with --
On Fri, Aug 10, 2018 at 5:00 PM, Yvan Roux wrote:
> On Fri, 10 Aug 2018 at 17:01, Ramana Radhakrishnan
> wrote:
>>
>> On Fri, Aug 10, 2018 at 3:35 PM, Yvan Roux wrote:
>> > On Fri, 10 Aug 2018 at 14:31, Yvan Roux wrote:
>> >>
>> >>
As $subject.
Ok ?
regards
Ramana
? htdocs/svn.html.~1.223.~
Index: htdocs/svn.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/svn.html,v
retrieving revision 1.223
diff -a -u -p -r1.223 svn.html
--- htdocs/svn.html 18 Jul 2018 18:17:
===
--- gcc/ChangeLog.arm (revision 263529)
+++ gcc/ChangeLog.arm (working copy)
@@ -1,3 +1,190 @@
+2018-08-14 Ramana Radhakrishnan
+
+ Backport spectre v1 mitigation patches.
+ 2018-08-06 John David Anglin
+ PR target/86785
+ * config/pa/pa.c
On Tue, Jun 6, 2017 at 1:56 PM, James Greenhalgh
wrote:
> On Tue, May 02, 2017 at 04:37:21PM +0100, Tamar Christina wrote:
>> Hi All,
>>
>> This patch adjusts the cost model for Cortex-A53 to increase the costs of
>> an integer division. The reason for this is that we want to always expand
>> the
Ping..
Ramana
On Tue, May 2, 2017 at 10:52 AM, Ramana Radhakrishnan
wrote:
> We unnecessarily align data to 8 byte alignments even when -Os is specified.
> This brings the logic in the AArch64 backend more in line with the ARM
> backend and helps gain some image size in a few places.
crtl->is_leaf has a comment above it referring to "Local Register
Allocation". However this is set by IRA and not LRA since the meaning of
Local Register Allocator in GCC has changed quite drastically since 1999
when this comment was introduced above the variable
current_function_is_leaf. From
On Fri, Jun 16, 2017 at 10:11 PM, Richard Earnshaw
wrote:
> On 13/06/17 18:35, Richard Earnshaw (lists) wrote:
>> On 09/06/17 13:53, Richard Earnshaw wrote:
>>>
>>> During the ARM BoF at the Cauldron last year I mentioned that I wanted
>>> to rework the way GCC on ARM handles the command line opti
On Tue, Jun 20, 2017 at 10:26 AM, Hurugalawadi, Naveen
wrote:
> Hi James,
>
> Thanks for the approval.
>
>>> From an AArch64 perspective, this is OK - but please wait for an ARM
>>> approval before you commit it.
>
> Can anyone from ARM comment on the patch so that it can be committed
> upstream i
Regenerate symbols file for aarch64-none-linux-gnu. Tested with make
check in libstdc++ and eyeballing outputs.
Applied as obvious.
Tested on aarch64-none-linux-gnu with no issues in libstdc++ tests.
regards
Ramana
* config/abi/post/aarch64-linux-gnu/baseline_symbols.txt: Regenerate
diff --
On 27/06/17 02:20, Kugan Vivekanandarajah wrote:
https://gcc.gnu.org/ml/gcc-patches/2016-03/msg00614.html added this
workaround to get kernel building with when TARGET_FIX_ERR_A53_843419
is enabled.
This was added to support building kernel loadable modules. In kernel,
when CONFIG_ARM64_ERRATUM
On Wed, Jun 14, 2017 at 2:55 PM, James Greenhalgh
wrote:
> On Fri, May 05, 2017 at 05:02:46PM +0100, Wilco Dijkstra wrote:
>> Richard Earnshaw (lists) wrote:
>>
>> > --- a/gcc/config/arm/aarch-common.c
>> > +++ b/gcc/config/arm/aarch-common.c
>> > @@ -254,12 +254,7 @@ arm_no_early_alu_shift_dep (r
On 6/28/17 1:49 PM, Wilco Dijkstra wrote:
Ramana Radhakrishnan wrote:
I'm about to run home for the day but this came in from
https://gcc.gnu.org/ml/gcc-patches/2013-09/msg02109.html and James
said in that email that this was put in to ensure no segfaults on
cortex-a15 / cortex-a7 t
On Wed, Jun 28, 2017 at 2:02 AM, Kugan Vivekanandarajah
wrote:
> Hi Ramana,
>
> On 27 June 2017 at 18:01, Ramana Radhakrishnan
> wrote:
>> On 27/06/17 02:20, Kugan Vivekanandarajah wrote:
>>>
>>> https://gcc.gnu.org/ml/gcc-patches/2016-03/msg00614.html add
On Thu, Jun 29, 2017 at 11:19 PM, Jan Hubicka wrote:
>> After this commit (r249800), GCC builds fail for arm and aarch64:
>>
>> /gccsrc/gcc/except.c: In function ???void
>> sjlj_emit_function_enter(rtx_code_label*)???:
>> /gcc-fsf/gccsrc/gcc/except.c:1183: error: conversion from ???int??? to
>> no
On Thu, Jun 29, 2017 at 11:24 PM, Jan Hubicka wrote:
>> On Thu, Jun 29, 2017 at 11:19 PM, Jan Hubicka wrote:
>> >> After this commit (r249800), GCC builds fail for arm and aarch64:
>> >>
>> >> /gccsrc/gcc/except.c: In function ???void
>> >> sjlj_emit_function_enter(rtx_code_label*)???:
>> >> /gcc
On Fri, Jun 30, 2017 at 2:36 PM, David Edelsohn wrote:
> Convert the rs6000 port to use the new API for branch probabilities.
>
> Okay?
>
> Thanks, David
>
> * config/rs6000/rs6000.c (emit_unlikely_jump): Adjust to new branch
> probability data type.
>
> Index: rs6000.c
> =
On Tue, Jul 4, 2017 at 1:56 PM, Arnaud Charlet wrote:
> On Tue, Jul 04, 2017 at 12:19:35PM +, Wilco Dijkstra wrote:
>> Andreas Schwab wrote:
>> > @@ -5207,6 +5209,7 @@ aarch64_print_operand (FILE *f, rtx x, int code)
>> >
>> >case MEM:
>> > output_address (GET_MODE (x), XEXP (
On Tue, Jul 4, 2017 at 2:53 PM, Michael Matz wrote:
> Hi,
>
> On Tue, 4 Jul 2017, Wilco Dijkstra wrote:
>
>> > You'll probably also have to set GNATBIND and GNATMAKE to the
>> > appropriately suffixed variants. Just saying, because that's what I'm
>> > usually forgetting and end up with strange e
On Wed, Nov 23, 2016 at 5:25 AM, Hurugalawadi, Naveen
wrote:
> Hi,
>
> Please find attached the patch that fixes PR71112.
>
> The current implementation that handles SYMBOL_SMALL_GOT_28K in
> aarch64_load_symref_appropriately access the high part of RTX for Big-Endian
> mode which results in ICE f
Why do we need fno-omit-frame-pointer on aarch64 ?
Ramana
From: James Greenhalgh
Sent: Friday, 17 November, 22:02
Subject: Re: [COMMITTED][AArch64] Fix frame tests
To: Wilco Dijkstra
Cc: GCC Patches, nd, Richard Earnshaw, Marcus Shawcroft, Ramana Radhakrishnan
On Thu, Nov 16, 2017 at 11:34
On 3 Nov 2017 16:55, "Wilco Dijkstra" wrote:
Almost all targets add an explict -fomit-frame-pointer in the target
specific
options. Rather than doing this in a target-specific way, do this in the
generic options so it works identically across all targets. In many cases
the
target no longer need
Hi,
I received a private report from a customer that gcc was putting out
calls to __divdf3 when compiling with +nosimd. When the reciprocal math
support was added this was probably an oversight or a typo.
The canonical examples is :
double
foo (double x, double y)
{
ret
On Thu, Nov 23, 2017 at 1:53 PM, Janne Blomqvist
wrote:
> On Thu, Nov 23, 2017 at 2:56 PM, Janne Blomqvist
> wrote:
>> On Wed, Nov 22, 2017 at 8:10 PM, Thomas Koenig wrote:
>>> Hi Janne,
>>>
> So, attached is a new version of the patch. No update
> on the ChangeLog. OK for trunk?
>>
The probe_stack pattern uses r0 as a fixed register. This can cause
issues if we have auto-increment instructions coming out that have r0 as
the base register.
Tested with a bootstrap and regression run. richi reports that the
original issue was fixed in the run. I did consider whether
probe_
ed on AArch64-none-linux-gnu but I see
one regression in gcc.c-torture/execute/960419-2.c which needs to be
looked at next (PR84528, thanks Kyrill).
Ok to put in and then look at PR84528 ?
gcc/ChangeLog:
2018-02-23 Ramana Radhakrishnan
PR target/84521
* common/config/aarch64/aa
On Wed, Feb 14, 2018 at 8:30 AM, Sameera Deshpande
wrote:
> Hi!
>
> Please find attached the patch to fix bug in branches with offsets over 1MiB.
> There has been an attempt to fix this issue in commit
> 050af05b9761f1979f11c151519e7244d5becd7c
>
> However, the far_branch attribute defined in abov
On Fri, Mar 9, 2018 at 9:48 AM, Bin.Cheng wrote:
> On Wed, Feb 28, 2018 at 6:17 AM, Alexandre Oliva wrote:
>> On Feb 21, 2018, Alexandre Oliva wrote:
>>
>>> On Feb 15, 2018, Szabolcs Nagy wrote:
i see assembler slow downs with these location view patches
i opened https://gcc.gnu.org/b
arch64*-*-linux*): New TARGET_DEFAULT_ASYNC_UNWIND_TABLES
common/config/aarch64/aarch64-common.c (aarch64_optimization_table[]):
Turn on fasynchronous-unwind-tables and funwind-tables.
commit ef1b5fa855a369b9996ccd7041255ff75a4b5b63
Author: Ramana Radhakrishnan
Date: Mon Mar 5 17:13:58 2018 +
On Mon, Mar 19, 2018 at 12:12 PM, James Greenhalgh
wrote:
> On Tue, Mar 13, 2018 at 01:35:56PM +0000, Ramana Radhakrishnan wrote:
>> Jakub commented here that
>> https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01325.html we don't turn
>> on fasynchronous-unwind-table
in a day or so.
regards
Ramana
* config/arm/arm.c (arm_valid_symbolic_address): Handle
arm_word_relocations
gcc/testsuite
* gcc.target/arm/pr81863.c: New test.
commit 22e3c20b7e6b5027f07b71ca31c9f65e66537b0b
Author: Ramana Radhakrishnan
Date: Tue Mar 13 10:54:04 2018 +
[
On 06/04/2018 16:54, Thomas Preudhomme wrote:
> Instruction pattern for setting the FPSCR expects the input value to be
> in a register. However, __builtin_arm_set_fpscr expander does not ensure
> that this is the case and as a result GCC ICEs when the builtin is
> called with a constant literal.
>
On Tue, 11 Sep 2018, 14:38 Vlad Lazar, wrote:
> Hi.
>
> This patch makes the scheduler prefer instructions with higher cost if two
> given instructions are equally good.
> Issuing more restricted instructions first is particularly useful on
> in-order cores because it increases the
> number of du
>
> > This to me feels like the wrong approach as it feels like you are assuming
> > INSN_COST is latency in some way ? Surely, we shouldn't be introducing
> > INSN_COST based stuff into the scheduler.
> >
> > Have you investigated using TARGET_SCHED_ADJUST_COST (IIRC, look for the
> > right name
On Mon, 17 Sep 2018, 23:56 Christophe Lyon,
wrote:
> On Fri, 14 Sep 2018 at 12:04, Sam Tebbs wrote:
> >
> >
> >
> > On 08/28/2018 11:54 PM, James Greenhalgh wrote:
> >
> >
> > >
> > > OK once the other one is approved, with the obvious rebase over the
> renamed
> > > function.
> > >
> > > James
On 27/09/2018 09:26, Kyrill Tkachov wrote:
Hi Thomas,
On 26/09/18 18:39, Thomas Preudhomme wrote:
Hi,
GCC ICEs under -mslow-flash-data and -mword-relocations because there
is no way to load an address, both literal pools and MOVW/MOVT being
forbidden. This patch gives an error message when bot
Graf of SuSE, and Ramana Radhakrishnan of ARM, at last week's
Linaro Connect in Vancouver.
The current state of the world is that one could distribute two
different copies of a given shared library and place the LSE-enabled
version in /lib64/atomics/ and it will be selected over the /lib64/
ve
On 27/09/2018 17:40, Richard Henderson wrote:
On 9/27/18 6:07 AM, Ramana Radhakrishnan wrote:
I do have an additional concern that I forgot to mention in Vancouver -
Thanks Wilco for reminding me that this now replaces a bunch of inline
instructions with effectively a library call therefore
On 26/09/2018 06:03, rth7...@gmail.com wrote:
From: Richard Henderson
This is the libgcc part of the interface -- providing the functions.
Rationale is provided at the top of libgcc/config/aarch64/lse.c.
* config/aarch64/lse.c: New file.
* config/aarch64/t-lse: New file.
On 02/10/2018 11:42, Thomas Preudhomme wrote:
Hi Ramana,
On Thu, 27 Sep 2018 at 11:14, Ramana Radhakrishnan
wrote:
On 27/09/2018 09:26, Kyrill Tkachov wrote:
Hi Thomas,
On 26/09/18 18:39, Thomas Preudhomme wrote:
Hi,
GCC ICEs under -mslow-flash-data and -mword-relocations because there
On 09/10/2018 09:27, Mihail Ionescu wrote:
> Hi all,
>
> This patch removes some of the machine mode checks from the arm backend when
> emitting instructions by using the '@' construct (Parameterized Names[2]). It
> is based on the previous AArch64 patch[1].
>
> [1]https://gcc.gnu.org/ml/gcc-patc
On Fri, Apr 13, 2018 at 7:08 AM, wrote:
> From: Vladimir Mezentsev
>
> When weakref_targets is not empty a target cannot be removed from weak_decls.
> A small example is below when 'wv12' is removed from the weak list on aarch64:
> static vtype Wv12 __attribute__((weakref ("wv12")));
> exter
On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang
wrote:
> tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes
> L1 Icache which can access L1 Dcache.
> Therefore, DC CVAU is not necessary in __aarch64_sync_cache_range for
> tsv110, is there any good idea to skip DC CVAU operation f
On 23/05/2018 03:50, Zhangshaokun wrote:
Hi Ramana,
On 2018/5/22 18:28, Ramana Radhakrishnan wrote:
On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang
wrote:
tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes
L1 Icache which can access L1 Dcache.
Therefore, DC CVAU is not
>
> Minor nit was reg. tested.
Another minor nit - please send the patch you committed to be archived
on the mailing list.
regards
Ramana
>
>
> On 08/06/2014 06:44 PM, Richard Earnshaw wrote:
>>
>> On 06/08/14 15:14, Ramana Radhakrishnan wrote:
>>>
>
On Tue, Aug 5, 2014 at 10:31 AM, Zhenqiang Chen
wrote:
> Hi,
>
> For some large constants, ARM will split them during expanding, which
> makes impossible to hoist them out the loop or shared by different
> references (refer the test case in the patch).
>
> The patch keeps some constants in registe
On Mon, Aug 11, 2014 at 3:35 AM, Zhenqiang Chen
wrote:
> On 8 August 2014 23:22, Ramana Radhakrishnan
> wrote:
>> On Tue, Aug 5, 2014 at 10:31 AM, Zhenqiang Chen
>> wrote:
>>> Hi,
>>>
>>> For some large constants, ARM will split them during expand
ing on armv7-a, neon,
float-abi=hard, arm state and will backport to 4.9 after suitable
testing there along with the afore mentioned testcase.
regards
Ramana
2014-08-12 Ramana Radhakrishnan
PR target/62098
* config/arm/vfp.md (*combine_vcvtf2i): Fix constraint.
Remove un
Hi,
The ACLE
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf
expects this macro to be defined in terms of byte sizes but we return
bit sizes *and* additionally do not handle -fshort-wchar.
Applied to trunk.
regards
Ramana
2014-08-12 Ramana Radhakrishnan
On Mon, Aug 11, 2014 at 11:01 PM, Janis Johnson
wrote:
> The check for effective target arm_v8_neon_ok passes even if __ARM_ARCH
> is not 8 or greater, but then some tests fail because intrinsic functions
> used in the test have not been declared. This patch requires that
> __ARM_ARCH be 8 or gre
On 14/08/14 19:25, Steve Ellcey wrote:
On Thu, 2014-08-14 at 10:21 -0600, Jeff Law wrote:
On 08/14/14 10:12, David Malcolm wrote:
On Thu, 2014-08-14 at 09:56 -0600, Jeff Law wrote:
On 08/14/14 04:32, Richard Biener wrote:
You'll note in a separate thread Steve and I discussed this during Ca
On Wed, Aug 20, 2014 at 4:45 PM, Evandro Menezes wrote:
> This is a trivial patch. However, without it, the addressing mode cost is
> incorrectly calculated, since the cost intended for HI end up being used for
> SI on A57.
Pinging patches every day isn't going to help :). Pinging weekly is
the
On 02/09/14 16:34, Kyrill Tkachov wrote:
Hi all,
This patch implements the {lceil, lfloor, lround}si{sf, df}2 optabs in a
similar way to fcvt in aarch64. We use the new ARMv8 FP convert with
rounding instructions vcvt{a,p,m} for that.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Ok f
On 02/09/14 16:34, Kyrill Tkachov wrote:
Hi all,
In continuation of patch [1/2]...
We can use the vector forms of the vcvt{a,p,m} instructions to vectorise
the l{round, ceil, floor}f functions.
Builtins are added and the TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
implementation is updated to
On 02/09/14 16:28, Richard Henderson wrote:
Is it intentional or not that AArch64 does not define __ARM_NEON__?
Yes I remember so, __ARM_NEON__ is not ACLE compatible so we haven't
defined it for AArch64 - on AArch32 and AArch64 we now have __ARM_NEON
defined so that's the macro to be used.
gt;>> 2) Some XPASS'es due to unexpected loop versioning (e.g.
>>>>>>> gcc.dg/vect/pr33804.c).
>>>>>>> 3) After predicate fix some passing tests which require unaligned
>>>>>>> vector support become NA (th
test run was also done for aarch64-none-linux-gnu.
Ok for trunk ?
regards
Ramana
gcc/Changelog
2014-09-04 Marcus Shawcroft
Ramana Radhakrishnan
* config/aarch64/aarch64-elf-raw.h (ENDFILE_SPEC): Add
crtfastmath.o.
* config/aarch64/aarch64-li
On Thu, Sep 4, 2014 at 6:33 AM, Bin Cheng wrote:
> Hi,
> This patch is to fix a potential bug in arm pattern "arm_movqi_insn".
>
> For the pattern,
> (define_insn "*arm_movqi_insn"
> [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m")
> (match_operand:QI 1 "general_op
On Thu, Sep 4, 2014 at 7:08 AM, Bin Cheng wrote:
> Hi,
> This patch is posted/approved before at
> https://gcc.gnu.org/ml/gcc-patches/2014-07/msg01398.html
> Unfortunately, it was reverted because a latent bug revealed causing glibc
> build failure and I didn't have enough time to fix back at that
On 04/09/14 18:12, Richard Henderson wrote:
On 09/04/2014 07:04 AM, Ramana Radhakrishnan wrote:
gcc/Changelog
2014-09-04 Marcus Shawcroft
Ramana Radhakrishnan
* config/aarch64/aarch64-elf-raw.h (ENDFILE_SPEC): Add
crtfastmath.o.
* config/aarch64
On 05/09/14 10:01, Kyrill Tkachov wrote:
Hi all,
We didn't schedule alu_ext and alus_ext anywhere for Cortex-A53 so this
patch handles it.
Tested arm-none-eabi and aarch64-none-elf.
Ok for trunk?
Ok - thanks.
Ramana
Thanks,
Kyrill
2014-09-05 Kyrylo Tkachov
* config/arm/cortex-a
On Fri, Aug 22, 2014 at 11:36 AM, Kyrill Tkachov wrote:
> Hi all,
>
> The Cortex-A53 scheduler description is missing rules for insn types used by
> instructions such as vrint*, vmaxnm, vminnm causing them to be assigned to
> the "nothing" unit.
>
> This patch causes such instructions to be treate
ChangeLog:
2013-11-01 Julian Brown
Joey Ye
* config/arm/arm.c (arm_cortex_m_branch_cost): New.
(arm_v7m_tune): New.
(arm_*_tune): Add comments for Sched adj cost.
List all names here please rather than a regexp.
* config/arm/arm-cores.def (cortex-m4, cortex
On 11/06/13 09:45, James Greenhalgh wrote:
Hi,
This patch is a respin of the aarch-common improvements to use a generic
search to find SETs and the variety of shifts, rather than relying on the
hope that we will find something well formed.
I've bootstrapped the patch on a chromebook with -mcpu
On 11/08/13 13:34, Kyrill Tkachov wrote:
Hi all,
In arm_new_rtx_costs we need a break; statement after handling the comparisons
cases. Otherwise we fall through and compute garbage. This small patch adds
that.
Tested arm-none-eabi on qemu.
Ok for trunk?
Ok - thanks.
Ramana
On 11/11/13 11:11, Eric Botcazou wrote:
Hi,
this is something I forgot to submit right after submitting
http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01906.html
We want to use the standard t-elf fragment on VxWorks as well.
Tested on ARM/VxWorks, OK for the mainline?
Ok, please apply.
rega
On 11/11/13 13:48, Kyrill Tkachov wrote:
Hi all,
My patch last Friday introduced a warning about reaching the end of a non-void
function which breaks bootstrap. On second thought, instead of breaking at the
end of the comparisons handling, we should just return instead.
Tested arm-none-eabi on
On Thu, Nov 21, 2013 at 5:09 PM, Martin Jambor wrote:
> Hi,
>
> the patch below enables IRA live-range splitting that later
> facilitates shrink-wrapping also work on ppc64. The difference is
> that while on x86_64 it was enough to look for single sets from a hard
> register to a pseudo in the fi
>> If the port has a splitter to rip apart a douple-word load into single-word
>> loads, then we'd obviously only want to do that in cases where the
>> double-word load actually generates > 1 assembly instruction.
Or indeed if it is really a performance win. And I think that should
purely be a p
What do you prefer me to do for these tests? I can think of:
- do not include them at all until fp16 is fully supported on both
AArch32 and AArch64
- include only those with float16x4_t
- include both float16x4_t and float16x8_t tests, leaving float16x8_t commented
I would include them both an
Hi Christian,
Thanks for looking at this. I will need to read the code in detail but
this is a first top level reivew.
On 09/29/14 12:03, Christian Bruel wrote:
Hi Ramana, Richard,
This patch implements the attribute target (and pragma) to allow
function based interworking.
as in the updat
and __ARM_ARCH_ISA_THUMB macros
with the M profile cores. Those probably also need handling please.
I'll review this again when the next patch set arrives with the
different parts.
regards
Ramana
Best Regards
Christian
On 10/08/2014 03:05 PM, Ramana Radhakrishnan wrote:
Hi Christian
On 16/10/14 21:43, Andrew Pinski wrote:
On Thu, Oct 16, 2014 at 1:38 PM, Sebastian Pop wrote:
Richard Biener wrote:
I have posted 5 patches as part of a larger series to merge
(parts) from the match-and-simplify branch. While I think
there was overall consensus that the idea behind the pro
On Wed, Oct 15, 2014 at 5:29 PM, Kyrill Tkachov wrote:
>
> On 15/10/14 14:00, Richard Biener wrote:
>>
>>
>> Any comments and reviews welcome (I don't think that
>> my maintainership covers enough to simply check this in
>> without approval).
>>
> Hi Richard,
>
> The match-and-simplify branch boot
On Mon, Oct 20, 2014 at 10:17 PM, Richard Sandiford
wrote:
> Maxim Kuvyrkov writes:
>> [Adding ARM maintainers to CC]
>>
>> On Oct 21, 2014, at 9:44 AM, Sebastian Pop wrote:
>>
>>> Hi Maxim,
>>>
>>> Maxim Kuvyrkov wrote:
Thanks, benchmarking results are welcome! AArch64 doesn't use reg_pre
On 21/10/14 14:48, Jiong Wang wrote:
this patch update arm testcases for recently gnu11 change.
ok for trunk?
This is OK bar the minor nit in the ChangeLog below - as a follow up it
would be nice to see if we can use the ACLE feature macros instead of
hard-coding some of the functions int
On Mon, Oct 13, 2014 at 3:15 PM, Renlin Li wrote:
> Hi all,
>
> This is a simple patch to add missing __ARM_FEATURE_IDIV__ predefined
> marco(ACLE 2.0) into TARGET_CPU_CPP_BUILTINS.
> Is it Okay to commit?
>
>
> gcc/ChangeLog:
>
> 2014-10-13 Renlin Li
>
> * config/arm/arm.h (TARGET_CPU_CPP_
On Wed, Oct 22, 2014 at 11:02 AM, Jiong Wang wrote:
>
> On 21/10/14 15:30, Ramana Radhakrishnan wrote:
>>
>> On Mon, Oct 13, 2014 at 3:15 PM, Renlin Li wrote:
>>>
>>> Hi all,
>>>
>>> This is a simple patch to add missing __
On Fri, Oct 24, 2014 at 12:47 PM, Jiong Wang wrote:
> we should not add explicit declaration there.
>
> arm_neon.h contains those prototype already. they will be available if the
> compiler configuration is with related builtin predefine, for example
> __ARM_FEATURE_CRYPTO.
>
> so, actually, if th
On Mon, Jun 2, 2014 at 8:56 AM, Jakub Jelinek wrote:
> On Mon, Jun 02, 2014 at 10:22:11AM +0400, Yury Gribov wrote:
>> Looks like now function does not return anything for ARM case? I'd
>> say we should replace this pc = ... with return like all other
>> cases, the code is just asking for trouble.
On Mon, Jun 2, 2014 at 10:44 AM, Yury Gribov wrote:
>>> Why the -1 ? No ARM or Thumb instruction is 1 byte long. Instructions
>>> are 4 bytes long if in ARM state and could be 2 or 4 bytes if Thumb
>>> state.
>>
>>
>> The -1 just points to the middle of previous instruction,
>> so that supposedly
On Mon, Jun 2, 2014 at 5:47 PM, Charles Baylis
wrote:
> This patch adds support for post-indexed addressing for NEON structure
> memory accesses.
>
> For example VLD1.8 {d0}, [r0], r1
>
>
> Bootstrapped and checked on arm-unknown-gnueabihf using Qemu.
>
> Ok for trunk?
This looks like a reasonabl
/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2014-06-03 Ramana Radhakrishnan
+
+ * config/arm/arm.md (enabled): Remove opt_enabled.
+
2014-06-02 Ramana Radhakrishnan
PR target/61154
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index bec889a..f58a79b 100644
>
> Thanks Richard for the comments. My primary intention here is to use
> TARGET_SPILL_CLASS to make FP_REGS as spill registers.
> Do you think
> AArch64 can benefit from TARGET_SPILL_CLASS hook. I agree that just
> increasing GP2FP and FP2GP for all the modes as I am doing is not the
> right thi
On Wed, May 28, 2014 at 2:09 PM, Evgeny Stupachenko wrote:
> Hi,
>
> The patch introduces alternative way of permutations for load groups
> of size 2 and 3 which should be faster on architectures with low
> parallelism.
> The patch gives 2 times gain on Silvermont to the test from PR52252
> (in ad
>> I don't think increasing GP2FP and FP2GP costs is a bad thing. In a
>> number of benchmarks we've seen increased moves between FP and integer
>> registers and having this fix appears to help some of them. However
>> moving this to generic model needs more benchmarking across a variety
>> of core
people
reading the documentation to understand at a glance what purpose it serves.
Ramana
Thanks,
Evgeny
On Thu, Jun 5, 2014 at 2:04 PM, Ramana Radhakrishnan
wrote:
On Wed, May 28, 2014 at 2:09 PM, Evgeny Stupachenko wrote:
Hi,
The patch introduces alternative way of permutations for load gr
On Fri, Jun 6, 2014 at 3:16 PM, Marc Glisse wrote:
> Hello,
>
> here is a new try on adding __float128 typeinfo to libsupc++. The front-end
> part is based on the discussion with Jason yesterday. The libstdc++ part is
> copied from:
> https://gcc.gnu.org/ml/libstdc++/2014-04/msg00077.html
> (which
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