Applied to master. Thanks!
Philipp.
On Tue, 5 Sept 2023 at 08:22, Jeff Law wrote:
>
>
> On 9/1/23 04:20, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Recently, these xtheadcondmov tests regressed with -Oz:
> > * FAIL: gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
> > * FAIL: g
Applied to master. Thanks!
Philipp.
On Tue, 5 Sept 2023 at 18:10, Jeff Law wrote:
>
>
> On 9/5/23 09:42, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Some constants can be built up using rotate-right instructions.
> > The code that enables this can be found in riscv_build_integ
Applied to master. Thanks!
Philipp.
On Tue, 5 Sept 2023 at 23:57, Jeff Law wrote:
>
>
> On 9/5/23 15:15, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Some constants can be built up using LI+RORI instructions.
> > The current implementation requires one of the upper 32-bits
> >
Committed as "obvious" to master.
--Philipp.
On Wed, 6 Sept 2023 at 12:04, Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> The test was introduced recently and tests a RV64-only feature.
> However, when testing an RV32 compiler, the test gets executed as we
Committed as 'obvious' to master. Thanks!
Philipp.
On Fri, 8 Sept 2023 at 08:53, Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> We currently have two identical zero_extendhi2 patterns:
> * '*zero_extendhi2_zbb'
> * '*zero_extendhi2_bitmanip'
>
> This patch
Applied to master. Thanks!
Philipp.
On Fri, 8 Sept 2023 at 10:13, Kito Cheng wrote:
> LGTM
>
> Christoph Muellner 於 2023年9月8日 週五 14:16 寫道：
>
>> From: Christoph Müllner
>>
>> The mode attribute of an extension pattern is usually set to the target
>> type.
>> Let's follow this convention consist
Applied to master. Thanks!
Philipp.
On Fri, 8 Sept 2023 at 14:17, Kito Cheng wrote:
> LGTM
>
> Christoph Muellner 於 2023年9月8日 週五，14:00寫道：
>
>> From: Christoph Müllner
>>
>> Recently three SPEC CPU 2017 benchmarks broke when using xtheadbb:
>> * 500.perlbench_r
>> * 525.x264_r
>> * 557.xz_r
>>
>
instruction.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_rtx_costs): Support
idioms matching to CSSC instructions, if target CSSC is
present
Signed-off-by: Philipp Tomsich
---
gcc/config/aarch64/aarch64.cc | 34 --
1 file changed, 24
: Document -mcpu=ampere1b
Signed-off-by: Philipp Tomsich
---
gcc/config/aarch64/aarch64-cores.def | 1 +
gcc/config/aarch64/aarch64-cost-tables.h | 107 +++
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aarch64/aarch64.cc| 89
wrote:
>
>
>
> > -Original Message-
> > From: Richard Earnshaw
> > Sent: Thursday, November 16, 2023 8:53 AM
> > To: Philipp Tomsich ; gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov
> > Subject: Re: [PATCH] aarch64: costs: update for TARGET_CSSC
> >
On Fri, 17 Nov 2023 at 22:47, Jeff Law wrote:
>
>
>
> On 11/17/23 04:39, juzhe.zh...@rivai.ai wrote:
> > 90% theadvector extension reusing current RVV 1.0 instructions patterns:
> > Just change ASM, For example:
> >
> > @@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh_scalar"
> >(match_o
/aarch64/tuning_models/ampere1b.h: New file.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- moved ampere1b model to a separated file
- regenerated aarch64-tune.md after rebase
gcc/config/aarch64/aarch64-cores.def| 1 +
gcc/config/aarch64/aarch64-cost-tables.h| 107
Applied to master, thanks!
Philipp,
On Thu, 23 Nov 2023 at 04:48, Jeff Law wrote:
>
>
>
> On 11/21/23 11:04, Manolis Tsamis wrote:
> > This code used to handle SUBREG for register replacement when ifcvt was
> > doing
> > the replacements manually. This special handling is not needed anymore
> >
On Tue, 28 Nov 2023 at 12:21, Richard Sandiford
wrote:
>
> Philipp Tomsich writes:
> > This patch adds initial support for Ampere-1B core.
> >
> > The Ampere-1B core implements ARMv8.7 with the following (compiler
> > visible) extensions:
> > - CSS
On Tue, 28 Nov 2023 at 20:31, Palmer Dabbelt wrote:
>
> On Wed, 22 Nov 2023 14:27:50 PST (-0800), jeffreya...@gmail.com wrote:
> > ...
>
> [Trimming everything else, as this is a big change. I'm also making it
> a new subject/thread, so folks can see.]
>
> > More generally, I think I need to soft
These build-ins are used internally for the
TARGET_ATOMIC_ASSIGN_EXPAND_FENV expansion (and therefore can not be
removed):
/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
void
riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
Applied to master, thanks!
Philipp.
On Tue, 28 Nov 2023 at 12:57, Richard Sandiford
wrote:
>
> Philipp Tomsich writes:
> > On Tue, 28 Nov 2023 at 12:21, Richard Sandiford
> > wrote:
> >>
> >> Philipp Tomsich writes:
> >> > This patch adds initi
Applied to master. Thanks!
Philipp.
On Tue, 12 Sept 2023 at 05:34, Jeff Law wrote:
>
>
>
> On 9/6/23 10:07, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > This patch implements expansions for the cmpstrsi and cmpstrnsi
> > builtins for RV32/RV64 for xlen-aligned strings if Zbb or
Applied to master. Thanks!
Philipp.
On Wed, 6 Sept 2023 at 18:07, Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This patch implements the expansion of the strlen builtin for RV32/RV64
> for xlen-aligned aligned strings if Zbb or XTheadBb instructions are
> available.
> The inserted
On Mon, 25 Sept 2023 at 21:54, Andrew Pinski wrote:
>
> On Mon, Sep 25, 2023 at 12:50 PM Manos Anagnostakis
> wrote:
> >
> > This patch implements the following TODO in gcc/config/aarch64/aarch64.cc
> > to provide the requested behaviour for handling ldp and stp:
> >
> > /* Allow the tuning str
rg
> > Cc: Kyrylo Tkachov ; Tamar Christina
> > ; Philipp Tomsich ;
> > Manos Anagnostakis
> > Subject: [PATCH v4] aarch64: Fine-grained policies to control ldp-stp
> > formation.
> >
> > This patch implements the following TODO in gcc/config/aarch64
Manos,
Please submit a follow-on patch implementing the requested
improvements of the code structure (as this reduces the maintenance
burden).
Thanks,
Philipp.
On Thu, 28 Sept 2023 at 15:33, Manos Anagnostakis
wrote:
>
> Hey Richard,
>
> Thanks for taking the time to review this, but it has be
On Thu, 23 May 2024 at 18:18, Andrew Pinski wrote:
>
> On Thu, May 23, 2024 at 8:01 AM Manolis Tsamis
> wrote:
> >
> > This pass detects cases of expensive store forwarding and tries to avoid
> > them
> > by reordering the stores and using suitable bit insertion sequences.
> > For example it ca
On Fri, 24 May 2024 at 13:02, Richard Biener wrote:
>
> On Fri, 24 May 2024, Manolis Tsamis wrote:
>
> > The match.pd patterns to merge two vector permutes into one fail when a
> > potentially no-op view convert expressions is between the two permutes.
> > This change lifts this restriction.
>
> O
On Thu, 11 Jul 2024 at 00:10, Jeff Law wrote:
>
>
>
> On 6/3/24 5:34 AM, Manolis Tsamis wrote:
> > Currently the operations allowed for if conversion of a basic block with
> > multiple sets are few, namely REG, SUBREG and CONST_INT (as controlled by
> > bb_ok_for_noce_convert_multiple_sets).
> >
>
Applied to master, thanks.
--Philipp.
On Tue, 13 Aug 2024 at 21:48, Jeff Law wrote:
>
>
> On 8/13/24 5:57 AM, Manolis Tsamis wrote:
> > Now that more operations are allowed for noce_convert_multiple_sets, we
> need to
> > check noce_can_force_operand on the sequence before calling
> try_emit_cmo
Applied to master, thanks!
--Philipp.
On Thu, 22 Aug 2024 at 20:30, Jeff Law wrote:
>
>
>
> On 8/22/24 5:04 AM, Manolis Tsamis wrote:
> > Similar to not allowing jump instructions in the generated code, we also
> > shouldn't allow call instructions in noce_convert_multiple_sets.
> > In the case
As reported on https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116372,
this change restores bootstrap.
Committing as obvious.
--Philipp.
On Tue, 20 Aug 2024 at 21:57, Manolis Tsamis wrote:
>
> Now that more operations are allowed for noce_convert_multiple_sets, it is
> possible that the same regist
On Mon, 10 Jun 2024 at 20:03, Jeff Law wrote:
>
>
>
> On 6/10/24 1:55 AM, Manolis Tsamis wrote:
>
> >>
> > There was an older submission of a load-pair specific pass but this is
> > a complete reimplementation and indeed significantly more general.
> > Apart from being target independant, it addre
On Tue, 11 Jun 2024 at 15:37, Jeff Law wrote:
>
>
>
> On 6/11/24 1:22 AM, Richard Biener wrote:
>
> >> Absolutely. But forwarding from a smaller store to a wider load is
> >> painful
> >> from a hardware standpoint and if we can avoid it from a codegen
> >> standpoint,
> >> we should.
> >
> >
Nitpick: a typo slipped into the comment — "regsiter" -> "register".
On Fri, 26 Jul 2024 at 16:18, Jeff Law wrote:
>
> pr116085 is a long standing (since late 2022) regression on the riscv
> port.
>
> A patch introduced a pattern to avoid unnecessary extensions when doing
> a min/max operation w
Sam, Jakub & Robin,
We had an "OK for trunk" from Jeff for v4 (see
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/656907.html) and
it has been two more weeks for this RESEND.
I'll push this by end of this week unless I hear otherwise.
Thanks,
Philipp.
On Fri, 26 Jul 2024 at 12:50, Sam Jame
Feng,
This looks good from our side and has shown useful (combined with the other 2
patches) in
our testing with SPEC2017.
Given that this looks final: what is the plan for getting this merged?
Thanks,
Philipp.
> On 12.09.2019, at 12:23, Feng Xue OS
> wrote:
>
> ---
> diff --git a/gcc/doc/in
Feng,
this now looks fine to me: what is the current schedule to get this merged?
Thanks,
Philipp.
> On 19.09.2019, at 16:30, Feng Xue OS
> wrote:
>
> Fix a bug on unary/binary operation check.
>
> Feng
> ---
> diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c
> index 33d52fe5537..f218f1093b8 100644
The Zihintpause extension uses an opcode from the 'fence' opcode range
to add a true hint instruction (i.e. if it is not supported on any
given platform, the 'fence' that is encoded will not enforce any
specific ordering on memory accesses) for entering a low-power state
(e.g. in an idle thread).
Kito:
We had originally considered to guard this with a -march, but decided
against it
eventually: this instruction will be (among other cases) used in the
cpu_relax() of
the Linux kernel. For cases like that, we should consider this the
baseline (i.e.
either there's no pause—in which case, the e
Jeff,
On Tue, 17 Nov 2020 at 00:38, Jeff Law wrote:
>
> On 11/16/20 11:57 AM, Philipp Tomsich wrote:
> > From: Philipp Tomsich
> >
> > While most shifts wider than the bitwidth of a type will be caught by
> > other passes, it is possible that these show up for V
e:
> > On Tue, Nov 17, 2020 at 05:29:57PM +0100, Philipp Tomsich wrote:
> >>>> In other words, the change to VRP canonicalizes what a lshift_expr
> with an
> >>>> shift-amount outside of the type width means... it doesn't assume
> anything
> >>&
Richard,
Could you review this series and let us know if this is acceptable for Phase 3?
This is a security-relevant (a Spectre variant 2 mitigation) for the Ampere
eMAG…
Thanks,
Philipp.
> On 09.12.2020, at 18:21, Christoph Müllner
> wrote:
>
> aarch64 already uses a C-function for indirect
Alexander,
I had missed your comment until now.
On Tue, 6 Sept 2022 at 13:39, Alexander Monakov wrote:
>
> On Mon, 5 Sep 2022, Philipp Tomsich wrote:
>
> > +riscv_mode_rep_extended (scalar_int_mode mode, scalar_int_mode
mode_rep)
> > +{
> > + /* On 64-bit targets,
The BSWAP operation is not handled in rtx_costs. Add it.
With Zbb, BSWAP for XLEN is a single instruction; for smaller modes,
it will expand into two.
gcc/ChangeLog:
* config/riscv/riscv.c (rtx_costs): Add BSWAP.
---
gcc/config/riscv/riscv.cc | 10 ++
1 file changed, 10 insert
The strength-reduction implementation in expmed.c will assess the
profitability of using shift-and-add using a RTL expression that wraps
a MULT (with a power-of-2) in a PLUS. Unless the RISC-V rtx_costs
function recognizes this as expressing a sh[123]add instruction, we
will return an inflated cos
If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
not a5,a0
sraia5,a5,63
and a0,a1,a5
missing the opportunity to combine the NOT and AND into an ANDN.
This adds a define_split to help the combiner reassociate the NOT with
the AND.
gcc/Chan
If we are testing a register or a paradoxical subreg (i.e. anything that is not
a partial subreg) for equality/non-equality with zero, we can generate a branch
that compares against $zero. This will work for QI, HI, SI and DImode, so we
enable this for ANYI.
2020-08-30 gcc/ChangeLog:
*
Consider creating a polarity-reversed mask from a set-bit (i.e., if
the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb,
this can be expressed as bexti, followed by an addi of minus-one. To
enable the combiner to discover this opportunity, we need to split the
canonical expression
-by: Philipp Tomsich
---
gcc/config/riscv/bitmanip.md | 17 +
gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c | 11 +++
2 files changed, 28 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c
diff --git a/gcc/config/riscv
gcc/ChangeLog:
* config/riscv/bitmanip.md: Handle corner-cases for combine
when chaining slli(.uw)? + addw
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zba-shNadd-04.c: New test.
---
gcc/config/riscv/bitmanip.md | 49 +++
gcc/config/risc
:
* gcc.target/riscv/zbs-bexti-02.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/bitmanip.md | 12 +
gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c | 25 +++
2 files changed, 37 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbs
test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/predicates.md| 23 ++
gcc/config/riscv/riscv.md | 51 +++
gcc/testsuite/gcc.target/riscv/branch-1.c | 37
3 files changed, 111 insertions(+)
create mode 100644 gcc
max against constants that are extension-invariant.
* config/riscv/iterators.md (minmax_optab): Add an iterator
that has only min and max rtl.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-02.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/ri
On Mon, 7 Nov 2022 at 14:55, Alexander Monakov wrote:
>
>
>
> On Sat, 5 Nov 2022, Philipp Tomsich wrote:
>
> > Alexander,
> >
> > I had missed your comment until now.
>
> Please make sure to read replies from Jeff and Palmer as well (their responses
&
max against constants that are extension-invariant.
* config/riscv/iterators.md (minmax_optab): Add an iterator
that has only min and max rtl.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-02.c: New test.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- fixes
On Wed, 9 Nov 2022 at 05:43, Andrew Pinski wrote:
>
> On Tue, Nov 8, 2022 at 7:16 PM Palmer Dabbelt wrote:
> >
> > On Tue, 08 Nov 2022 18:57:26 PST (-0800), jeffreya...@gmail.com wrote:
> > >
> > > On 11/8/22 12:54, Philipp Tomsich wrote:
> > >>
wrote:
> >
> > On 11/8/22 12:54, Philipp Tomsich wrote:
> >> The BSWAP operation is not handled in rtx_costs. Add it.
> >>
> >> With Zbb, BSWAP for XLEN is a single instruction; for smaller modes,
> >> it will expand into two.
> >>
> >> g
On Wed, 9 Nov 2022 at 04:00, Palmer Dabbelt wrote:
>
> On Tue, 08 Nov 2022 05:40:10 PST (-0800), christoph.muell...@vrull.eu wrote:
> > On Mon, Nov 7, 2022 at 8:01 PM Palmer Dabbelt wrote:
> >
> >> The docs say we take ISA strings, but that's never really been the case:
> >> at a bare minimum we'
w expander that handles the basic and fancy
(such as li+sh[123]add, addi+addi, ...) cases for adding
register-register and register-const_int.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/addi.c: New test.
* gcc.target/riscv/zba-shNadd-06.c: New test.
Signed-off-by:
C CPU 2017.
gcc/ChangeLog:
* config/riscv/riscv.md (movmisalign): Implement.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/movmisalign-1.c: New test.
* gcc.target/riscv/movmisalign-2.c: New test.
* gcc.target/riscv/movmisalign-3.c: New test.
Signed-off-by: Philipp To
recognize_single_bit_test): Add
detection for tests against the sign-bit of the relevant
type as a single-bit test.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/ssa-ifcombine-14.c: New test.
Signed-off-by: Philipp Tomsich
---
.../gcc.dg/tree-ssa/ssa-ifcombine-14.c|
ty.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/ssa-ifcombine-15.c: New test.
Signed-off-by: Philipp Tomsich
---
.../gcc.dg/tree-ssa/ssa-ifcombine-15.c| 14 +
gcc/tree-ssa-ifcombine.cc | 56 +++
2 files changed, 70 insertions(+)
create mode 100644 g
applying these, I'll take care to pull that part out of the other
patch if needed.
Version-changes: 2
- refactor
- optimise for additional corner cases and deal with fallout
Signed-off-by: Philipp Tomsich
---
(no changes since v1)
gcc/config/riscv/bitmanip.md
applying these, I'll take care to pull that part out of the other
patch if needed.
Version-changes: 2
- refactor
- optimise for additional corner cases and deal with fallout
Version-changes: 3
- removed the [WIP] from the commit message (no other changes)
Signed-off-by: Philipp
ISC-V: Support --target-help for -mcpu/-mtune")
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Update
sifive-7-series to point to the sifive_7 pipeline
description.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/riscv-cores.def | 2 +-
1 file
the
close of phase 1.
—Philipp.
>
> On Wed, Nov 9, 2022 at 3:08 PM Philipp Tomsich
> wrote:
> >
> > The default implementation of support_vector_misalignment() checks
> > whether movmisalign is present for the requested mode. This
> > will be used by vect_supportabl
Applied to master, thank you!
On Thu, 10 Nov 2022 at 02:03, Kito Cheng wrote:
>
> LGTM, thank you for catching that!!
>
> On Wed, Nov 9, 2022 at 3:50 PM Philipp Tomsich
> wrote:
> >
> > A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
> &g
On Thu, 10 Nov 2022 at 02:46, Palmer Dabbelt wrote:
>
> On Tue, 08 Nov 2022 11:54:34 PST (-0800), philipp.toms...@vrull.eu wrote:
> > The strength-reduction implementation in expmed.c will assess the
> > profitability of using shift-and-add using a RTL expression that wraps
> > a MULT (with a powe
On Thu, 10 Nov 2022 at 21:47, Palmer Dabbelt wrote:
>
> On Thu, 10 Nov 2022 07:09:35 PST (-0800), philipp.toms...@vrull.eu wrote:
> > On Thu, 10 Nov 2022 at 02:46, Palmer Dabbelt wrote:
> >>
> >> On Tue, 08 Nov 2022 11:54:34 PST (-0800), philipp.toms...@vrull.eu wrote:
> >> > The strength-reducti
for MINUS from PLUS.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zba-shNadd-07.c: New test.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- Split rtx_costs calculation for MINUS from PLUS to ensure that
(minus reg (ashift reg SHAMT)) is not mistaken for a shNadd
- Add testcase
scv/bitmanip.md (*bseti_extrabit): New pattern
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bseti.c: New test.
Signed-off-by: Philipp Tomsich
---
- Depends on a predicate posted in "RISC-V: Optimize branches testing
a bit-range or a shifted immediate". Depending on the order
scv/bitmanip.md (*binvi_extrabit): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-binvi.c: New test.
Signed-off-by: Philipp Tomsich
---
- Depends on a predicate posted in "RISC-V: Optimize branches testing
a bit-range or a shifted immediate". Depending on the
(const_nottwobits_operand):
New predicate.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bclri.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/bitmanip.md | 38 ++
gcc/config/riscv/predicates.md | 5 +++
gcc/testsuite
also match
some typical programming idioms. This series includes backend support
for XVentanaCondops and infrastructure to handle conditional-zero
constructions in if-conversion.
Tested against SPEC CPU 2017.
Philipp Tomsich (7):
RISC-V: Recognize xventanacondops extension
RISC-V: Generate
RISCV_CORE): Enable
"xventanacondops" by default for "ventana-vt1".
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
(TARGET_XVENTANACONDOPS): Define.
* config/riscv/riscv.opt: Add "riscv_xventanacondops".
Signed-off-by: Philip
ntanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/riscv.cc
immediates for
vt.maskc/vt.maskcn through a splitter.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ifconv-imm.c: New test.
Signed-off-by: Philipp Tomsich
Reviewed-by: Henry Brausen
---
Ref #204
gcc/config/riscv/xventanacondops.md
as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/xven
maskc.
Signed-off-by: Philipp Tomsich
Ref vrull/gcc#157
RISC-V: Recognize 'ge'/'le' operators as 'slt'/'sgt'
During if-conversion, if noce_try_store_flag_mask succeeds, we may see
if (cur < next) {
next = 0;
}
transformed into
27: r82:S
a5,a5
and a5,a5,a1
due to how the sequence presents to the combine pass.
This adds an additional splitter to reassociate the polarity reversed
case into bexti + addi, if Zbs is present.
Signed-off-by: Philipp Tomsich
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Add split to reassociat
e-01.c: New test.
* gcc.target/riscv/xventanacondops-xor-01.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/ifcvt.cc | 214 ++
.../gcc.target/riscv/xventanacondops-and-01.c | 16 ++
.../gcc.target/riscv/xventanacondops-and-02.c |
On Sat, 12 Nov 2022 at 22:47, Andrew Pinski wrote:
>
> On Sat, Nov 12, 2022 at 1:34 PM Philipp Tomsich
> wrote:
> >
> > Some architectures, as it the case on RISC-V with the proposed
> > ZiCondOps and the vendor-defined XVentanaCondOps, define a
> > con
Applied to master. Thanks!
Note that the multiply-by-200 (in the testcase) originates from Dhrystone.
Philipp.
On Sun, 13 Nov 2022 at 02:23, Jeff Law wrote:
>
>
> On 11/10/22 14:34, Philipp Tomsich wrote:
> > The strength-reduction implementation in expmed.cc will assess the
&g
Applied to master as obvious.
ChangeLog:
* doc/contrib.rst: Update Jeff Law's email address.
Signed-off-by: Philipp Tomsich
---
doc/contrib.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/contrib.rst b/doc/contrib.rst
index 96bf2a56af4..15e358b7903 1
Applied to master. Thanks!
--Philipp.
On Sun, 13 Nov 2022 at 01:24, Jeff Law wrote:
>
>
> On 11/8/22 12:54, Philipp Tomsich wrote:
> > If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
> > not a5,a0
> > sraia5,a5,6
ion_pair_p): Implement
idiom-matcher for the new fusion pair.
Signed-off-by: Philipp Tomsich
---
gcc/config/aarch64/aarch64-cores.def| 1 +
gcc/config/aarch64/aarch64-cost-tables.h| 107
gcc/config/aarch64/aarch64-fusion-pairs.def | 1 +
gcc/conf
Implement.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/riscv.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 2d0d170645c..c216173cf6b 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
uage-family/target-builtins/risc-v-built-in-functions.rst:
Document.
* optabs.cc (maybe_gen_insn): Allow nops == 0 (void -> void).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/builtin_pause.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/riscv-bu
es in v2:
- Rebased and changed over to .rst-based documentation
- Updated to catch more fusion cases
- Signals support for Zifencei
Philipp Tomsich (2):
RISC-V: Add basic support for the Ventana-VT1 core
RISC-V: Add instruction fusion (for ventana-vt1)
gcc/config/riscv/riscv-core
tions/machine-dependent-options/risc-v-options.rst:
Document -mcpu= and -mtune with ventana-vt1.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- Rebased and changed over to .rst-based documentation
- Updated to catch more fusion cases
- Signals support for Zifencei
- Rebase to m
nfig/riscv/bitmanip.md (*bext): Add an additional
pattern that allows the 3rd argument to zero_extract to be
an Xmode register operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext.c: Add testcases.
* gcc.target/riscv/zbs-bexti.c: Add testcases.
Signed-off-b
.
(TARGET_SCHED_MACRO_FUSION_P): Point to riscv_macro_fusion_p.
(TARGET_SCHED_MACRO_FUSION_PAIR_P): Point to riscv_macro_fusion_pair_p.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- Update fusion patterns and catch some missing idioms/fusion pairs.
gcc/config/riscv/riscv.cc
n T has 2 bits set and C has
one
of these tow bits set.
* config/riscv/predicates.md (const_twobits_operand): New predicate.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-if_then_else-01.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/bitma
, then invert bit'.
This change improves the previously generated
srl a0,a0,a1
not a0,a0
andi a0,a0,1
into
bext a0,a0,a1
xori a0,a0,1
Signed-off-by: Philipp Tomsich
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add split covering
"(a & (1 << B
scv-opts.h (MASK_XVENTANACONDOPS): Define.
(TARGET_XVENTANACONDOPS): Define.
* config/riscv/riscv.opt: Add "riscv_xventanacondops".
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- Restore a (during rebase) dropped line to xventanacondops.md
- Include the change to add xventanacon
ntanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- Ran whitespace-cleanup on
as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Signed-off-by: Philipp Tomsich
---
(no changes since v1)
the change to add xventanacondops to the VT1 code definition]
as a separate patch.
Philipp Tomsich (8):
RISC-V: Recognize xventanacondops extension
RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion
RISC-V: Support noce_try_store_flag_mask as vt.maskc
RISC-V: Recognize
immediates for
vt.maskc/vt.maskcn through a splitter.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ifconv-imm.c: New test.
Signed-off-by: Philipp Tomsich
Reviewed-by: Henry Brausen
---
Ref #204
(no changes since v1)
gcc/config/riscv/xventanacondops.md
(anyle_operator): Define.
(anylt_operator): Define.
* config/riscv/riscv.md: Helpers for ge(u) & le(u).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-le-01.c: New test.
* gcc.target/riscv/xventanacondops-lt-03.c: New test.
Signed-off-by: Phi
+ neg" into "bexti + addi".
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- Removed spurious empty line at the end of xventanacondops.md.
gcc/config/riscv/xventanacondops.md | 10 ++
1 file changed, 10 insertions(+)
diff --git a/gcc/config/riscv/xventanacondops.md
b/g
e-01.c: New test.
* gcc.target/riscv/xventanacondops-xor-01.c: New test.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- Ran whitespace-cleanup on xventanacondops-ne-01.c.
gcc/ifcvt.cc | 214 ++
.../gcc.target/riscv/xventanacondops-an
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_CORE): Update the
Ventana-VT1 definition to include the xventanacondops
extension.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- New in v2.
gcc/config/riscv/riscv-cores.def | 2 +-
1 file changed, 1 insertion
101 - 200 of 371 matches
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